forked from Imagelibrary/binutils-gdb
Fix failures in the GAS testsuite for the ARC architecture.
gas * config/tc-arc.c (arc_option): Sets all internal gas options when parsing .cpu directive. (declare_register_set): Declare all 64 registers. (md_section_align): Refactor. (md_pcrel_from_section): Remove assert. (pseudo_operand_match): Fix pseudo operand match. (find_reloc): Use flags filed, extend matching. * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT relocation. testsuite * gas/arc/bic.d: Update test. * gas/arc/add_s-err.s: New file. * gas/arc/cpu-warn1.s: Likewise. * gas/arc/pcl-relocs.d: Likewise. * gas/arc/pcl-relocs.s: Likewise. * gas/arc/pcrel-relocs.d: Likewise. * gas/arc/pcrel-relocs.s: Likewise. * gas/arc/pic-relocs.d: Likewise. * gas/arc/pic-relocs.s: Likewise. * gas/arc/plt-relocs.d: Likewise. * gas/arc/plt-relocs.s: Likewise. * gas/arc/pseudos.d: Likewise. * gas/arc/pseudos.s: Likewise. * gas/arc/sda-relocs.d: Likewise. * gas/arc/sda-relocs.s: Likewise. * gas/arc/sda-relocs2.d: Likewise. * gas/arc/sda-relocs2.s: Likewise. * gas/arc/tls-relocs.d: Likewise. * gas/arc/tls-relocs.s: Likewise. opcode * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32]. opcodes * arc-dis.c (special_flag_p): Match full mnemonic. * arc-opc.c (print_insn_arc): Check section size to read appropriate number of bytes. Fix printing. * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without arguments.
This commit is contained in:
Claudiu Zissulescu
committed by
Nick Clifton
Nick Clifton
parent
5cc854a862
commit
24b368f853
@@ -1,3 +1,11 @@
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2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
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* arc-dis.c (special_flag_p): Match full mnemonic.
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* arc-opc.c (print_insn_arc): Check section size to read
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appropriate number of bytes. Fix printing.
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* arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
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arguments.
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2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
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@@ -82,15 +82,13 @@ special_flag_p (const char *opname,
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const char *flgname)
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{
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const struct arc_flag_special *flg_spec;
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size_t len;
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unsigned i, j, flgidx;
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for (i = 0; i < arc_num_flag_special; i++)
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{
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flg_spec = &arc_flag_special_cases[i];
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len = strlen (flg_spec->name);
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if (strncmp (opname, flg_spec->name, len) != 0)
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if (strcmp (opname, flg_spec->name))
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continue;
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/* Found potential special case instruction. */
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@@ -127,7 +125,7 @@ print_insn_arc (bfd_vma memaddr,
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int flags;
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bfd_boolean need_comma;
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bfd_boolean open_braket;
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int size;
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lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
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highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
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@@ -148,8 +146,46 @@ print_insn_arc (bfd_vma memaddr,
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break;
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}
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/* This variable may be set by the instruction decoder. It suggests
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the number of bytes objdump should display on a single line. If
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the instruction decoder sets this, it should always set it to
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the same value in order to get reasonable looking output. */
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info->bytes_per_line = 8;
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/* In the next lines, we set two info variables control the way
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objdump displays the raw data. For example, if bytes_per_line is
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8 and bytes_per_chunk is 4, the output will look like this:
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00: 00000000 00000000
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with the chunks displayed according to "display_endian". */
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if (info->section
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&& !(info->section->flags & SEC_CODE))
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{
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/* This is not a CODE section. */
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switch (info->section->size)
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{
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case 1:
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case 2:
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case 4:
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size = info->section->size;
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break;
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default:
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size = (info->section->size & 0x01) ? 1 : 4;
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break;
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}
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info->bytes_per_chunk = 1;
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info->display_endian = info->endian;
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}
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else
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{
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size = 2;
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info->bytes_per_chunk = 2;
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info->display_endian = info->endian;
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}
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/* Read the insn into a host word. */
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status = (*info->read_memory_func) (memaddr, buffer, 2, info);
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status = (*info->read_memory_func) (memaddr, buffer, size, info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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@@ -159,20 +195,29 @@ print_insn_arc (bfd_vma memaddr,
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if (info->section
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&& !(info->section->flags & SEC_CODE))
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{
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/* Sort of data section, just print a 32 bit number. */
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insnLen = 4;
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status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
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if (status != 0)
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/* Data section. */
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unsigned long data;
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data = bfd_get_bits (buffer, size * 8,
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info->display_endian == BFD_ENDIAN_BIG);
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switch (size)
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{
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(*info->memory_error_func) (status, memaddr + 2, info);
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return -1;
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case 1:
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(*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
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break;
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case 2:
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(*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
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break;
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case 4:
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(*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
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break;
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default:
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abort ();
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}
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insn[0] = ARRANGE_ENDIAN (info, buffer);
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(*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
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return insnLen;
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return size;
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}
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if ((((buffer[lowbyte] & 0xf8) > 0x38)
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if ( (((buffer[lowbyte] & 0xf8) > 0x38)
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&& ((buffer[lowbyte] & 0xf8) != 0x48))
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|| ((info->mach == bfd_mach_arc_arcv2)
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&& ((buffer[lowbyte] & 0xF8) == 0x48)) /* FIXME! ugly. */
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@@ -196,20 +241,6 @@ print_insn_arc (bfd_vma memaddr,
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insn[0] = ARRANGE_ENDIAN (info, buffer);
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}
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/* This variable may be set by the instruction decoder. It suggests
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the number of bytes objdump should display on a single line. If
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the instruction decoder sets this, it should always set it to
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the same value in order to get reasonable looking output. */
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info->bytes_per_line = 8;
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/* The next two variables control the way objdump displays the raw data.
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For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the
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output will look like this:
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00: 00000000 00000000
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with the chunks displayed according to "display_endian". */
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info->bytes_per_chunk = 2;
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info->display_endian = info->endian;
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/* Set some defaults for the insn info. */
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info->insn_info_valid = 1;
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info->branch_delay_insns = 0;
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@@ -1240,38 +1240,52 @@ const struct arc_flag_special arc_flag_special_cases[] =
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const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
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/* Relocations. */
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#undef DEF
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#define DEF(NAME, EXC1, EXC2, RELOC1, RELOC2) \
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{ #NAME, EXC1, EXC2, RELOC1, RELOC2}
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const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
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{
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DEF (sda, "ld", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
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DEF (sda, "st", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2),
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DEF (sda, "ldw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
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DEF (sda, "ldh", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
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DEF (sda, "stw", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
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DEF (sda, "sth", F_AS9, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1),
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{ "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
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{ "sda", "st", { F_ASFAKE, F_H1, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
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{ "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
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{ "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
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/* Next two entries will cover the undefined behavior ldb/stb with
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address scaling. */
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{ "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
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{ "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
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{ "sda", "ld", { F_ASFAKE, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
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{ "sda", "st", { F_ASFAKE, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
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{ "sda", "ldd", { F_ASFAKE, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
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{ "sda", "std", { F_ASFAKE, F_NULL },
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BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
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/* Short instructions. */
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DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD),
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DEF (sda, 0, F_NULL, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1),
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DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2),
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DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2),
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{ "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
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{ "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
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{ "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
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{ "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
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DEF (sda, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME),
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DEF (sda, 0, F_NULL, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST),
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{ "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
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{ "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
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DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25H_PCREL,
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BFD_RELOC_ARC_S25H_PCREL_PLT),
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DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21H_PCREL,
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BFD_RELOC_ARC_S21H_PCREL_PLT),
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DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S25W_PCREL,
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BFD_RELOC_ARC_S25W_PCREL_PLT),
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DEF (plt, 0, F_NULL, BFD_RELOC_ARC_S21W_PCREL,
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BFD_RELOC_ARC_S21W_PCREL_PLT),
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{ "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
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BFD_RELOC_ARC_S25H_PCREL_PLT },
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{ "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
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BFD_RELOC_ARC_S21H_PCREL_PLT },
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{ "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
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BFD_RELOC_ARC_S25W_PCREL_PLT },
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{ "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
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BFD_RELOC_ARC_S21W_PCREL_PLT },
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DEF (plt, 0, F_NULL, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32),
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{ "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
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};
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const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
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@@ -1871,10 +1871,10 @@
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{ "brhs", 0x0E017F85, 0xFF017FF7, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE, { LIMM, LIMMdup, SIMM9_A16_8 }, { C_T }},
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/* brk 00100101011011110000000000111111. */
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{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
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{ "brk", 0x256F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
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/* brk_s 0111111111111111. */
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{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
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{ "brk_s", 0x00007FFF, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
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/* brlo<.d> b,c,s9 00001bbbsssssss1SBBBCCCCCCN00100. */
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{ "brlo", 0x08010004, 0xF801001F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, BRANCH, NONE, { RB, RC, SIMM9_A16_8 }, { C_D }},
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@@ -2272,12 +2272,12 @@
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/* clri c 00100111001011110000CCCCCC111111. */
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{ "clri", 0x272F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { RC }, { 0 }},
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/* clri 0 00100111001011110000111110111111. */
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{ "clri", 0x272F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { ZA }, { 0 }},
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/* clri u6 00100111011011110000uuuuuu111111. */
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{ "clri", 0x276F003F, 0xFFFFF03F, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { UIMM6_20 }, { 0 }},
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/* clri 00100111011011110000uuuuuu111111. */
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{ "clri", 0x276F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
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/* cmacchfr a,b,c 00110bbb000010011BBBCCCCCCAAAAAA. */
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{ "cmacchfr", 0x30098000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
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@@ -6179,7 +6179,7 @@
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{ "dsubh22", 0x36FB7F80, 0xFFFF7FE0, ARC_OPCODE_ARCv2EM, FLOAT, DP, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
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/* dsync 00100010011011110001RRRRRR111111. */
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{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
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{ "dsync", 0x226F103F, 0xFFFFF03F, ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
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/* ei_s u10 010111uuuuuuuuuu. */
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{ "ei_s", 0x00005C00, 0x0000FC00, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, JUMP, CD2, { UIMM10_6_S }, { 0 }},
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@@ -7761,100 +7761,100 @@
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{ "iaddr", 0x30E70F80, 0xF8FF0FE0, ARC_OPCODE_ARC700, ARITH, NONE, { RB, RBdup, LIMM }, { C_F, C_CC }},
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/* invld042e 00100RRRRR101110RRRRRRRRRRRRRRRR. */
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{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
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{ "invld042e", 0x202E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
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/* invld042f0e 00100RRRRR101111RRRRRRRRRR00111R. */
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{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
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{ "invld042f0e", 0x202F000E, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
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/* invld042f12 00100RRRRR101111RRRRRRRRRR01001R. */
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{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
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{ "invld042f12", 0x202F0012, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
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/* invld042f14 00100RRRRR101111RRRRRRRRRR0101RR. */
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{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
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{ "invld042f14", 0x202F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
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/* invld042f18 00100RRRRR101111RRRRRRRRRR011RRR. */
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{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
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{ "invld042f18", 0x202F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
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/* invld042f20 00100RRRRR101111RRRRRRRRRR10RRRR. */
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{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
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{ "invld042f20", 0x202F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
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/* invld042f30 00100RRRRR101111RRRRRRRRRR110RRR. */
|
||||
{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f30", 0x202F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld042f38 00100RRRRR101111RRRRRRRRRR1110RR. */
|
||||
{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f38", 0x202F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld042f3c 00100RRRRR101111RRRRRRRRRR11110R. */
|
||||
{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f3c", 0x202F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld042f3e 00100RRRRR101111RRRRRRRRRR111110. */
|
||||
{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f3e", 0x202F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld042f3f08 00100RRRRR101111R001RRRRRR111111. */
|
||||
{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f3f08", 0x202F103F, 0xF83F703F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld042f3f10 00100RRRRR101111R01RRRRRRR111111. */
|
||||
{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f3f10", 0x202F203F, 0xF83F603F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld042f3f20 00100RRRRR101111R1RRRRRRRR111111. */
|
||||
{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld042f3f20", 0x202F403F, 0xF83F403F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld0506 00101RRRRR00011RRRRRRRRRRRRRRRRR. */
|
||||
{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld0506", 0x28060000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld050a 00101RRRRR00101RRRRRRRRRRRRRRRRR. */
|
||||
{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld050a", 0x280A0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld050c 00101RRRRR00110RRRRRRRRRRRRRRRRR. */
|
||||
{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld050c", 0x280C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld051e 00101RRRRR01111RRRRRRRRRRRRRRRRR. */
|
||||
{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld051e", 0x281E0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld0520 00101RRRRR100RRRRRRRRRRRRRRRRRRR. */
|
||||
{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld0520", 0x28200000, 0xF8380000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld0528 00101RRRRR1010RRRRRRRRRRRRRRRRRR. */
|
||||
{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld0528", 0x28280000, 0xF83C0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052c 00101RRRRR10110RRRRRRRRRRRRRRRRR. */
|
||||
{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052c", 0x282C0000, 0xF83E0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052e 00101RRRRR101110RRRRRRRRRRRRRRRR. */
|
||||
{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052e", 0x282E0000, 0xF83F0000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f02 00101RRRRR101111RRRRRRRRRR00001R. */
|
||||
{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f02", 0x282F0002, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f04 00101RRRRR101111RRRRRRRRRR0001RR. */
|
||||
{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f04", 0x282F0004, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f14 00101RRRRR101111RRRRRRRRRR0101RR. */
|
||||
{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f14", 0x282F0014, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f18 00101RRRRR101111RRRRRRRRRR011RRR. */
|
||||
{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f18", 0x282F0018, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f20 00101RRRRR101111RRRRRRRRRR10RRRR. */
|
||||
{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f20", 0x282F0020, 0xF83F0030, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f30 00101RRRRR101111RRRRRRRRRR110RRR. */
|
||||
{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f30", 0x282F0030, 0xF83F0038, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f38 00101RRRRR101111RRRRRRRRRR1110RR. */
|
||||
{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f38", 0x282F0038, 0xF83F003C, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f3c 00101RRRRR101111RRRRRRRRRR11110R. */
|
||||
{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f3c", 0x282F003C, 0xF83F003E, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f3e 00101RRRRR101111RRRRRRRRRR111110. */
|
||||
{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f3e", 0x282F003E, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld052f3f00 00101RRRRR101111RRRRRRRRRR111111. */
|
||||
{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld052f3f00", 0x282F003F, 0xF83F003F, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* invld07 00111RRRRRRRRRRRRRRRRRRRRRRRRRRR. */
|
||||
{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { }, { 0 }},
|
||||
{ "invld07", 0x38000000, 0xF8000000, ARC_OPCODE_ARCv2HS, INVALID, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* j c 00100RRR001000000RRRCCCCCCRRRRRR. */
|
||||
{ "j", 0x20200000, 0xF8FF8000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, JUMP, NONE, { BRAKET, RC, BRAKETdup }, { 0 }},
|
||||
@@ -12790,10 +12790,10 @@
|
||||
{ "neg_s", 0x00007813, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB_S, RC_S }, { 0 }},
|
||||
|
||||
/* nop 00100110010010100111000000000000. */
|
||||
{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
|
||||
{ "nop", 0x264A7000, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* nop_s 0111100011100000. */
|
||||
{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
|
||||
{ "nop_s", 0x000078E0, 0x0000FFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* norm<.f> b,c 00101bbb00101111FBBBCCCCCC000001. */
|
||||
{ "norm", 0x282F0001, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, BTSCN, { RB, RC }, { C_F }},
|
||||
@@ -13768,7 +13768,7 @@
|
||||
{ "rsub", 0x26CE7F80, 0xFFFF7FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, LIMM, LIMMdup }, { C_F, C_CC }},
|
||||
|
||||
/* rtie 00100100011011110000000000111111. */
|
||||
{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
|
||||
{ "rtie", 0x246F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* rtsc b,0 00110bbb01101111RBBB000000011010. */
|
||||
{ "rtsc", 0x306F001A, 0xF8FF0FFF, ARC_OPCODE_ARC700, CONTROL, NONE, { RB, ZB }, { 0 }},
|
||||
@@ -13909,13 +13909,13 @@
|
||||
{ "scond", 0x262F7F91, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM, MEMORY, NONE, { LIMM, BRAKET, LIMMdup, BRAKETdup }, { C_DI16 }},
|
||||
|
||||
/* scondd<.di> b,c 00100bbb00101111DBBBCCCCCC010011. */
|
||||
{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, RC }, { C_DI16 }},
|
||||
{ "scondd", 0x202F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, RC, BRAKETdup }, { C_DI16 }},
|
||||
|
||||
/* scondd<.di> b,u6 00100bbb01101111DBBBuuuuuu010011. */
|
||||
{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, UIMM6_20 }, { C_DI16 }},
|
||||
{ "scondd", 0x206F0013, 0xF8FF003F, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, UIMM6_20, BRAKETdup }, { C_DI16 }},
|
||||
|
||||
/* scondd<.di> b,limm 00100bbb00101111DBBB111110010011. */
|
||||
{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, LIMM }, { C_DI16 }},
|
||||
{ "scondd", 0x202F0F93, 0xF8FF0FFF, ARC_OPCODE_ARCv2HS, MEMORY, NONE, { RB, BRAKET, LIMM, BRAKETdup }, { C_DI16 }},
|
||||
|
||||
/* setacc a,b,c 00101bbb000011011BBBCCCCCCAAAAAA. */
|
||||
{ "setacc", 0x280D8000, 0xF8FF8000, ARC_OPCODE_ARCv2EM, DSP, NONE, { RA, RB, RC }, { 0 }},
|
||||
@@ -14226,6 +14226,9 @@
|
||||
/* seti limm 00100110001011110000111110111111. */
|
||||
{ "seti", 0x262F0FBF, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { LIMM }, { 0 }},
|
||||
|
||||
/* seti 00100110011011110000uuuuuu111111. */
|
||||
{ "seti", 0x266F003F, 0xFFFFFFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* setle<.f> a,b,c 00100bbb00111110FBBBCCCCCCAAAAAA. */
|
||||
{ "setle", 0x203E0000, 0xF8FF0000, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, CD1, { RA, RB, RC }, { C_F }},
|
||||
|
||||
@@ -15196,19 +15199,19 @@
|
||||
{ "swape", 0x2E2F7F89, 0xFFFF7FFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, SWAP, { ZA, LIMM }, { C_F }},
|
||||
|
||||
/* swi 00100010011011110000000000111111. */
|
||||
{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
|
||||
{ "swi", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* swi_s 0111101011100000. */
|
||||
{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
|
||||
{ "swi_s", 0x00007AE0, 0x0000FFFF, ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* swi_s u6 01111uuuuuu11111. */
|
||||
{ "swi_s", 0x0000781F, 0x0000F81F, ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
|
||||
|
||||
/* sync 00100011011011110000000000111111. */
|
||||
{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { }, { 0 }},
|
||||
{ "sync", 0x236F003F, 0xFFFFFFFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, CONTROL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* trap0 00100010011011110000000000111111. */
|
||||
{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { }, { 0 }},
|
||||
{ "trap0", 0x226F003F, 0xFFFFFFFF, ARC_OPCODE_ARC700, KERNEL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* trap_s u6 01111uuuuuu11110. */
|
||||
{ "trap_s", 0x0000781E, 0x0000F81F, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { UIMM6_5_S }, { 0 }},
|
||||
@@ -15277,7 +15280,7 @@
|
||||
{ "tst_s", 0x0000780B, 0x0000F81F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, LOGICAL, NONE, { RB_S, RC_S }, { 0 }},
|
||||
|
||||
/* unimp_s 0111100111100000. */
|
||||
{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { }, { 0 }},
|
||||
{ "unimp_s", 0x000079E0, 0x0000FFFF, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, KERNEL, NONE, { 0 }, { 0 }},
|
||||
|
||||
/* upkqb<.f> a,b,c 00110bbb00100001FBBBCCCCCCAAAAAA. */
|
||||
{ "upkqb", 0x30210000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, RC }, { C_F }},
|
||||
|
||||
Reference in New Issue
Block a user