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Add ABFD argument to sim_open call. Pass through to sim_config so

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that image properties such as endianness can be checked.

More strongly document the expected behavour of each of the sim_*
interfaces.

Add default endian argument to simulator config macro
SIM_AC_OPTION_ENDIAN.  Use in sim_config.
This commit is contained in:
Andrew Cagney
1997-08-25 23:14:25 +00:00
parent 04f295b648
commit 247fccdeb5
41 changed files with 3429 additions and 518 deletions
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23
sim/mips/ChangeLog
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@@ -1,3 +1,26 @@
Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
* config.in: Ditto.
Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_open): Add ABFD argument.
(sim_load): Move call to sim_config from here.
(sim_open): To here. Check return status.
start-sanitize-r5900
* gencode.c (build_instruction): Do not define x8000000000000000,
x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
end-sanitize-r5900
start-sanitize-r5900
Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
* gencode.c (build_instruction): For "pdivw", "pdivbw" and
"pdivuw" check for overflow due to signed divide by -1.
end-sanitize-r5900
Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
* gencode.c (build_instruction): Two arg MADD should

609
sim/mips/configure vendored
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File diff suppressed because it is too large Load Diff

3
sim/mips/gencode.c
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@@ -3927,9 +3927,6 @@ build_instruction (doisa, features, mips16, insn)
printf(" signed64 t = ((unsigned64)HI_UW(0) << 32) | (unsigned64)LO_UW(0);\n");
printf(" signed64 u = ((unsigned64)HI_UW(2) << 32) | (unsigned64)LO_UW(2);\n");
printf(" signed64 x000000007FFFFFFF = LSMASK64 (31);\n");
printf(" signed64 xFFFFFFFF80000000 = MSMASK64 (33);\n");
printf(" signed64 x7FFFFFFFFFFFFFFF = LSMASK64 (63);\n");
printf(" signed64 x8000000000000000 = MSMASK64 (1);\n");
printf(" signed64 x0000000080000000 = x000000007FFFFFFF + 1;\n");
printf(" signed64 minus0000000080000000 = -x0000000080000000;\n");
printf(" if ( t > x000000007FFFFFFF )\n");

44
sim/mips/interp.c
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@@ -283,7 +283,14 @@ SUB_REG_FETCH - return as lvalue some sub-part of a "register"
A - low part of "register"
A1 - high part of register
*/
#define SUB_REG_FETCH(T,TC,A,A1,I) (*(((T*)(((I) < (TC)) ? (A) : (A1))) + ((I) % (TC))))
#define SUB_REG_FETCH(T,TC,A,A1,I) \
(*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
+ (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
? ((TC) - 1 - (I) % (TC)) \
: ((I) % (TC)) \
) \
) \
)
/*
GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
@@ -292,18 +299,16 @@ GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
2 is B=byte H=halfword W=word D=doubleword
*/
#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed char, BYTES_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed short, HALFWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed int, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed long long, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned char, BYTES_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned short, HALFWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned int, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned long long,DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8, BYTES_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8, BYTES_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS, A, A1, I)
#define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
#define GPR_SB(R,I) SUB_REG_SB(&registers[R], &registers1[R], I)
#define GPR_SH(R,I) SUB_REG_SH(&registers[R], &registers1[R], I)
#define GPR_SW(R,I) SUB_REG_SW(&registers[R], &registers1[R], I)
@@ -769,9 +774,10 @@ interrupt_event (SIM_DESC sd, void *data)
/*---------------------------------------------------------------------------*/
SIM_DESC
sim_open (kind,cb,argv)
sim_open (kind, cb, abfd, argv)
SIM_OPEN_KIND kind;
host_callback *cb;
struct _bfd *abfd;
char **argv;
{
SIM_DESC sd = &simulator;
@@ -814,6 +820,14 @@ sim_open (kind,cb,argv)
return 0;
}
/* Configure/verify the target byte order and other runtime
configuration options */
if (sim_config (sd, abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
@@ -1315,10 +1329,6 @@ sim_load (sd,prog,abfd,from_tty)
return SIM_RC_FAIL;
sim_analyze_program (sd, prog_bfd);
/* Configure/verify the target byte order and other runtime
configuration options */
sim_config (sd, PREFERED_TARGET_BYTE_ORDER(prog_bfd));
/* (re) Write the monitor trap address handlers into the monitor
(eeprom) address space. This can only be done once the target
endianness has been determined. */