Toolchain/binutils-gdb
1
0
Fork 0
forked from Imagelibrary/binutils-gdb
Code Pull Requests Activity

This patch introduces TRBE (Trace Buffer Extension) system registers for the AArch64 architecture.

Browse Source 
gas           * testsuite/gas/aarch64/trbe-invalid.d: New test.
              * testsuite/gas/aarch64/trbe-invalid.l: New test.
              * testsuite/gas/aarch64/trbe-invalid.s: New test.
              * testsuite/gas/aarch64/trbe.d: New test.
              * testsuite/gas/aarch64/trbe.s: New test.

opcodes       * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
              TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
This commit is contained in:
Przemyslaw Wirkus
2020-09-28 15:37:50 +01:00
committed by Nick Clifton
parent 9bede61ce5
commit 1ff8e40105
8 changed files with 65 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
opcodes/ChangeLog
View File

@@ -1,3 +1,8 @@
2020-09-28 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
2020-09-26 Alan Modra <amodra@gmail.com>
* csky-opc.h: Formatting.

8
opcodes/aarch64-opc.c
View File

@@ -4311,6 +4311,14 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_V8_R ("prselr_el2", CPENC (3,4,C6,C2,1), 0),
SR_V8_R ("vsctlr_el2", CPENC (3,4,C2,C0,0), 0),
SR_CORE("trbbaser_el1", CPENC (3,0,C9,C11,2), 0),
SR_CORE("trbidr_el1", CPENC (3,0,C9,C11,7), F_REG_READ),
SR_CORE("trblimitr_el1", CPENC (3,0,C9,C11,0), 0),
SR_CORE("trbmar_el1", CPENC (3,0,C9,C11,4), 0),
SR_CORE("trbptr_el1", CPENC (3,0,C9,C11,1), 0),
SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0),
SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0),
{ 0, CPENC (0,0,0,0,0), 0, 0 }
};