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aarch64: Add support for Common Short Sequence Compression extension

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This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.

gas/ChangeLog:

        * config/tc-aarch64.c (parse_operands): Handle new operand types.
        * doc/c-aarch64.texi: Document new extension.
        * testsuite/gas/aarch64/cssc.d: New test.
        * testsuite/gas/aarch64/cssc.s: New test.

include/ChangeLog:

        * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
        (enum aarch64_opnd): New operand types.
        (enum aarch64_insn_class): New instruction class.

opcodes/ChangeLog:

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-opc.c (operand_general_constraint_met_p): Update for new
	operand types.
	(aarch64_print_operand): Likewise.
	* aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
	* aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
	(CSSC): Define new feature set Macro.
	(CSSC_INSN): Define new instruction type.
	(aarch64_opcode_table): Add new instructions.
This commit is contained in:
Andre Vieira
2022-11-14 16:47:22 +00:00
parent 255571cdbf
commit 1f7b42d52a
11 changed files with 511 additions and 50 deletions
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2
gas/doc/c-aarch64.texi
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@@ -186,6 +186,8 @@ automatically cause those extensions to be disabled.
@tab Enable floating-point extensions.
@item @code{hbc} @tab @tab Armv8.8-A or later
@tab Enable Armv8.8-A hinted conditional branch instructions
@item @code{cssc} @tab @tab Armv8.7-A or later
@tab Enable Armv8.9-A Common Short Sequence Compression instructions.
@item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
@tab Enable Int8 Matrix Multiply extension.
@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later