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gas/

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* config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p
	instructions to loose any special insn->architecture mask.

	* config/tc-sparc.c (v9a_asr_table): Add v9b ASRs.
	(sparc_md_end, sparc_arch_types, sparc_arch,
	sparc_elf_final_processing): Handle v8plusb and v9b architectures.
	(sparc_ip): Handle siam mode operands. Support v9b ASRs (and
	request v9b architecture if they are used).

bfd/
	* elf32-sparc.c (elf32_sparc_merge_private_bfd_data,
	elf32_sparc_object_p, elf32_sparc_final_write_processing):
	Support v8plusb.
	* elf64-sparc.c (sparc64_elf_merge_private_bfd_data,
	sparc64_elf_object_p): Support v9b.
	* archures.c: Declare v8plusb and v9b machines.
	* bfd-in2.h: Ditto.
	* cpu-sparc.c: Ditto.

include/opcode/
	* sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B.
	Note that '3' is used for siam operand.

opcodes/
	* sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs.
	(compute_arch_mask): Add v8plusb and v9b machines.
	(print_insn_sparc): siam mode decoding, accept ASRs up to 25.
	* opcodes/sparc-opc.c: Support for Cheetah instruction set.
	(prefetch_table): Add #invalidate.
This commit is contained in:
Jakub Jelinek
2000-10-20 10:38:47 +00:00
parent bb160f3e2d
commit 19f7b01094
13 changed files with 215 additions and 95 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
opcodes/sparc-opc.c
View File

@@ -1,5 +1,5 @@
/* Table of opcodes for the sparc.
Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999
Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
Free Software Foundation, Inc.
This file is part of the BFD library.
@@ -35,27 +35,30 @@ Boston, MA 02111-1307, USA. */
#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
/* Bit masks of architectures supporting the insn. */
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A)
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
/* v6 insns not supported on the sparclet */
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A)
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A)
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
/* Although not all insns are implemented in hardware, sparclite is defined
to be a superset of v8. Unimplemented insns trap and are then theoretically
implemented in software.
It's not clear that the same is true for sparclet, although the docs
suggest it is. Rather than complicating things, the sparclet assembler
recognizes all v8 insns. */
#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE | MASK_V9 | MASK_V9A)
#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B)
#define sparclet (MASK_SPARCLET)
#define sparclite (MASK_SPARCLITE)
#define v9 (MASK_V9 | MASK_V9A)
#define v9a (MASK_V9A)
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
#define v9a (MASK_V9A | MASK_V9B)
#define v9b (MASK_V9B)
/* v6 insns not supported by v9 */
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
| MASK_SPARCLET | MASK_SPARCLITE)
@@ -76,6 +79,8 @@ const struct sparc_opcode_arch sparc_opcode_archs[] = {
{ "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
/* v9 with ultrasparc additions */
{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
/* v9 with cheetah additions */
{ "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
{ NULL, 0 }
};
@@ -843,6 +848,10 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */
{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
@@ -862,6 +871,8 @@ const struct sparc_opcode sparc_opcodes[] = {
{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
@@ -1814,6 +1825,19 @@ SLCBCC("cbnefr", 15),
{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
/* Cheetah instructions */
{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
/* More v9 specific insns, these need to come last so they do not clash
with v9a instructions such as "edge8" which looks like impdep1. */
@@ -1976,6 +2000,7 @@ static arg prefetch_table[] =
{ 2, "#n_writes" },
{ 3, "#one_write" },
{ 4, "#page" },
{ 16, "#invalidate" },
{ 0, 0 }
};