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* cgen-engine.h (EXTRACT_MSB0_LGSINT, EXTRACT_MSB0_LGUINT): Define.

Browse Source 
(EXTRACT_LSB0_LGSINT, EXTRACT_LSB0_LGUINT): Define.
	(EXTRACT_FN, SEMANTIC_FN): Use CGEN_INSN_WORD in prototype
	instead of CGEN_INSN_INT.
plus, cgen files: Regenerate.
This commit is contained in:
Doug Evans
2009-11-23 04:12:17 +00:00
parent 1fbb9298a4
commit 197fa1aa2c
43 changed files with 1072 additions and 957 deletions
Download Patch File Download Diff File Expand all files Collapse all files

208
sim/cris/decodev32.c
View File

@@ -320,14 +320,14 @@ crisv32f_init_idesc_table (SIM_CPU *cpu)
const IDESC *
crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
CGEN_INSN_INT base_insn,
CGEN_INSN_WORD base_insn,
ARGBUF *abuf)
{
/* Result of decoder. */
CRISV32F_INSN_TYPE itype;
{
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
{
unsigned int val = (((insn >> 4) & (255 << 0)));
@@ -1923,7 +1923,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -1951,7 +1951,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -1979,7 +1979,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_moveq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_moveq.f
UINT f_operand2;
INT f_s6;
@@ -2006,7 +2006,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@@ -2034,7 +2034,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -2064,7 +2064,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -2094,7 +2094,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movecdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -2124,7 +2124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movscbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
UINT f_operand2;
INT f_indir_pc__byte;
@@ -2154,7 +2154,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movscwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
UINT f_operand2;
INT f_indir_pc__word;
@@ -2184,7 +2184,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movucbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
UINT f_operand2;
INT f_indir_pc__byte;
@@ -2214,7 +2214,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movucwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
UINT f_operand2;
INT f_indir_pc__word;
@@ -2244,7 +2244,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addq.f
UINT f_operand2;
UINT f_u6;
@@ -2272,7 +2272,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_r_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@@ -2300,7 +2300,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2332,7 +2332,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2364,7 +2364,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmp_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2396,7 +2396,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -2426,7 +2426,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -2456,7 +2456,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpcdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -2486,7 +2486,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_andq.f
UINT f_operand2;
INT f_s6;
@@ -2513,7 +2513,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpucbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -2543,7 +2543,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_cmpucwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -2573,7 +2573,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2605,7 +2605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2637,7 +2637,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2669,7 +2669,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2701,7 +2701,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movs_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -2733,7 +2733,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_sprv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_operand1;
@@ -2761,7 +2761,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_spr_rv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
UINT f_operand1;
@@ -2789,7 +2789,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_m_sprv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_memmode;
@@ -2821,7 +2821,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_c_sprv32_p2:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -2851,7 +2851,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_spr_mv32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_memmode;
@@ -2883,7 +2883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_ss_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_operand1;
@@ -2910,7 +2910,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_ss:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
UINT f_operand1;
@@ -2937,7 +2937,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_r_m_v32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f
UINT f_operand2;
UINT f_memmode;
@@ -2985,7 +2985,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_movem_m_r_v32:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f
UINT f_operand2;
UINT f_memmode;
@@ -3033,7 +3033,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3062,7 +3062,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3091,7 +3091,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3124,7 +3124,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3157,7 +3157,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_add_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3190,7 +3190,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -3221,7 +3221,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -3252,7 +3252,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addcdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcdr.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -3283,7 +3283,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_adds_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3316,7 +3316,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_adds_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3349,7 +3349,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addscbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -3380,7 +3380,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addscwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -3411,7 +3411,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addc_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3444,7 +3444,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lapc_d:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_lapc_d.f
SI f_indir_pc__dword_pcrel;
UINT f_operand2;
@@ -3474,7 +3474,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lapcq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_lapcq.f
UINT f_operand2;
SI f_qo;
@@ -3501,7 +3501,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3530,7 +3530,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_neg_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3558,7 +3558,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_neg_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3586,7 +3586,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_memmode;
UINT f_operand1;
@@ -3614,7 +3614,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_memmode;
UINT f_operand1;
@@ -3642,7 +3642,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_test_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_memmode;
UINT f_operand1;
@@ -3670,7 +3670,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3702,7 +3702,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3734,7 +3734,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_move_r_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3766,7 +3766,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_muls_b:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@@ -3796,7 +3796,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_mcp:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
UINT f_operand1;
@@ -3825,7 +3825,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_dstep:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@@ -3854,7 +3854,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3883,7 +3883,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -3912,7 +3912,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3945,7 +3945,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -3978,7 +3978,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_and_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_add_m_b_m.f
UINT f_operand2;
UINT f_memmode;
@@ -4011,7 +4011,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcbr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcbr.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -4042,7 +4042,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcwr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcwr.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -4073,7 +4073,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andcdr:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addcdr.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -4104,7 +4104,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_andq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_andq.f
UINT f_operand2;
INT f_s6;
@@ -4132,7 +4132,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_swap:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_operand1;
@@ -4160,7 +4160,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_asrq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_asrq.f
UINT f_operand2;
UINT f_u5;
@@ -4188,7 +4188,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lsrr_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -4217,7 +4217,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_lsrr_d_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_operand1;
@@ -4246,7 +4246,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btst:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@@ -4274,7 +4274,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_btstq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_asrq.f
UINT f_operand2;
UINT f_u5;
@@ -4301,7 +4301,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_setf:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_setf.f
UINT f_operand2;
UINT f_operand1;
@@ -4423,7 +4423,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcc_b:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_b.f
UINT f_operand2;
UINT f_disp9_lo;
@@ -4459,7 +4459,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ba_b:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_b.f
UINT f_disp9_lo;
INT f_disp9_hi;
@@ -4492,7 +4492,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bcc_w:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_w.f
SI f_indir_pc__word_pcrel;
UINT f_operand2;
@@ -4521,7 +4521,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_ba_w:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bcc_w.f
SI f_indir_pc__word_pcrel;
/* Contents of trailing part of insn. */
@@ -4547,7 +4547,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jas_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_operand1;
@@ -4575,7 +4575,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jas_c:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -4605,7 +4605,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jump_p:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand2;
@@ -4629,7 +4629,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bas_c:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bas_c.f
SI f_indir_pc__dword_pcrel;
UINT f_operand2;
@@ -4659,7 +4659,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_jasc_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f
UINT f_operand2;
UINT f_operand1;
@@ -4687,7 +4687,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_break:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_break.f
UINT f_u4;
@@ -4710,7 +4710,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cb:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -4741,7 +4741,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cw:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -4772,7 +4772,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_bound_cd:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -4803,7 +4803,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_scc:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f
UINT f_operand2;
UINT f_operand1;
@@ -4830,7 +4830,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addoq:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addoq.f
UINT f_operand2;
INT f_s8;
@@ -4857,7 +4857,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_b_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -4889,7 +4889,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_w_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -4921,7 +4921,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_m_d_m:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_addc_m.f
UINT f_operand2;
UINT f_memmode;
@@ -4953,7 +4953,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cb:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cb.f
INT f_indir_pc__byte;
UINT f_operand2;
@@ -4983,7 +4983,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cw:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cw.f
INT f_indir_pc__word;
UINT f_operand2;
@@ -5013,7 +5013,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addo_cd:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_bound_cd.f
INT f_indir_pc__dword;
UINT f_operand2;
@@ -5043,7 +5043,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_addi_acr_b_r:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_muls_b.f
UINT f_operand2;
UINT f_operand1;
@@ -5071,7 +5071,7 @@ crisv32f_decode (SIM_CPU *current_cpu, IADDR pc,
extract_sfmt_fidxi:
{
const IDESC *idesc = &crisv32f_insn_data[itype];
CGEN_INSN_INT insn = base_insn;
CGEN_INSN_WORD insn = base_insn;
#define FLD(f) abuf->fields.sfmt_mcp.f
UINT f_operand1;