diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index df94e7514b9..1d747a7ad90 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,12 @@
+2019-02-26  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* features/riscv/32bit-cpu.xml: Add register numbers.
+	* features/riscv/32bit-fpu.c: Regenerate.
+	* features/riscv/32bit-fpu.xml: Add register numbers.
+	* features/riscv/64bit-cpu.xml: Add register numbers.
+	* features/riscv/64bit-fpu.c: Regenerate.
+	* features/riscv/64bit-fpu.xml: Add register numbers.
+
 2019-02-26  Kevin Buettner  <kevinb@redhat.com>
 
 	* NEWS: Mention two argument form of gdb.Value constructor.
diff --git a/gdb/features/riscv/32bit-cpu.xml b/gdb/features/riscv/32bit-cpu.xml
index 466f2c06485..0d07aaec857 100644
--- a/gdb/features/riscv/32bit-cpu.xml
+++ b/gdb/features/riscv/32bit-cpu.xml
@@ -5,9 +5,13 @@
      are permitted in any medium without royalty provided the copyright
      notice and this notice are preserved.  -->
 
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.riscv.cpu">
-  <reg name="zero" bitsize="32" type="int"/>
+  <reg name="zero" bitsize="32" type="int" regnum="0"/>
   <reg name="ra" bitsize="32" type="code_ptr"/>
   <reg name="sp" bitsize="32" type="data_ptr"/>
   <reg name="gp" bitsize="32" type="data_ptr"/>
diff --git a/gdb/features/riscv/32bit-fpu.c b/gdb/features/riscv/32bit-fpu.c
index 22e80d640e5..a19780aab0c 100644
--- a/gdb/features/riscv/32bit-fpu.c
+++ b/gdb/features/riscv/32bit-fpu.c
@@ -9,6 +9,7 @@ create_feature_riscv_32bit_fpu (struct target_desc *result, long regnum)
   struct tdesc_feature *feature;
 
   feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.fpu");
+  regnum = 33;
   tdesc_create_reg (feature, "ft0", regnum++, 1, NULL, 32, "ieee_single");
   tdesc_create_reg (feature, "ft1", regnum++, 1, NULL, 32, "ieee_single");
   tdesc_create_reg (feature, "ft2", regnum++, 1, NULL, 32, "ieee_single");
@@ -41,6 +42,7 @@ create_feature_riscv_32bit_fpu (struct target_desc *result, long regnum)
   tdesc_create_reg (feature, "ft9", regnum++, 1, NULL, 32, "ieee_single");
   tdesc_create_reg (feature, "ft10", regnum++, 1, NULL, 32, "ieee_single");
   tdesc_create_reg (feature, "ft11", regnum++, 1, NULL, 32, "ieee_single");
+  regnum = 66;
   tdesc_create_reg (feature, "fflags", regnum++, 1, NULL, 32, "int");
   tdesc_create_reg (feature, "frm", regnum++, 1, NULL, 32, "int");
   tdesc_create_reg (feature, "fcsr", regnum++, 1, NULL, 32, "int");
diff --git a/gdb/features/riscv/32bit-fpu.xml b/gdb/features/riscv/32bit-fpu.xml
index 6a44b842b86..1eaae9119e3 100644
--- a/gdb/features/riscv/32bit-fpu.xml
+++ b/gdb/features/riscv/32bit-fpu.xml
@@ -5,9 +5,13 @@
      are permitted in any medium without royalty provided the copyright
      notice and this notice are preserved.  -->
 
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.riscv.fpu">
-  <reg name="ft0" bitsize="32" type="ieee_single"/>
+  <reg name="ft0" bitsize="32" type="ieee_single" regnum="33"/>
   <reg name="ft1" bitsize="32" type="ieee_single"/>
   <reg name="ft2" bitsize="32" type="ieee_single"/>
   <reg name="ft3" bitsize="32" type="ieee_single"/>
@@ -40,7 +44,7 @@
   <reg name="ft10" bitsize="32" type="ieee_single"/>
   <reg name="ft11" bitsize="32" type="ieee_single"/>
 
-  <reg name="fflags" bitsize="32" type="int"/>
-  <reg name="frm" bitsize="32" type="int"/>
-  <reg name="fcsr" bitsize="32" type="int"/>
+  <reg name="fflags" bitsize="32" type="int" regnum="66"/>
+  <reg name="frm" bitsize="32" type="int" regnum="67"/>
+  <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
 </feature>
diff --git a/gdb/features/riscv/64bit-cpu.xml b/gdb/features/riscv/64bit-cpu.xml
index c4d83de09b9..b8aa424ae4b 100644
--- a/gdb/features/riscv/64bit-cpu.xml
+++ b/gdb/features/riscv/64bit-cpu.xml
@@ -5,9 +5,13 @@
      are permitted in any medium without royalty provided the copyright
      notice and this notice are preserved.  -->
 
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.riscv.cpu">
-  <reg name="zero" bitsize="64" type="int"/>
+  <reg name="zero" bitsize="64" type="int" regnum="0"/>
   <reg name="ra" bitsize="64" type="code_ptr"/>
   <reg name="sp" bitsize="64" type="data_ptr"/>
   <reg name="gp" bitsize="64" type="data_ptr"/>
diff --git a/gdb/features/riscv/64bit-fpu.c b/gdb/features/riscv/64bit-fpu.c
index 8cbd7484ab3..b93cb4ec03b 100644
--- a/gdb/features/riscv/64bit-fpu.c
+++ b/gdb/features/riscv/64bit-fpu.c
@@ -17,6 +17,7 @@ create_feature_riscv_64bit_fpu (struct target_desc *result, long regnum)
   field_type = tdesc_named_type (feature, "ieee_double");
   tdesc_add_field (type_with_fields, "double", field_type);
 
+  regnum = 33;
   tdesc_create_reg (feature, "ft0", regnum++, 1, NULL, 64, "riscv_double");
   tdesc_create_reg (feature, "ft1", regnum++, 1, NULL, 64, "riscv_double");
   tdesc_create_reg (feature, "ft2", regnum++, 1, NULL, 64, "riscv_double");
@@ -49,6 +50,7 @@ create_feature_riscv_64bit_fpu (struct target_desc *result, long regnum)
   tdesc_create_reg (feature, "ft9", regnum++, 1, NULL, 64, "riscv_double");
   tdesc_create_reg (feature, "ft10", regnum++, 1, NULL, 64, "riscv_double");
   tdesc_create_reg (feature, "ft11", regnum++, 1, NULL, 64, "riscv_double");
+  regnum = 66;
   tdesc_create_reg (feature, "fflags", regnum++, 1, NULL, 32, "int");
   tdesc_create_reg (feature, "frm", regnum++, 1, NULL, 32, "int");
   tdesc_create_reg (feature, "fcsr", regnum++, 1, NULL, 32, "int");
diff --git a/gdb/features/riscv/64bit-fpu.xml b/gdb/features/riscv/64bit-fpu.xml
index fd14ebced85..794854cc011 100644
--- a/gdb/features/riscv/64bit-fpu.xml
+++ b/gdb/features/riscv/64bit-fpu.xml
@@ -5,6 +5,10 @@
      are permitted in any medium without royalty provided the copyright
      notice and this notice are preserved.  -->
 
+<!-- Register numbers are hard-coded in order to maintain backward
+     compatibility with older versions of tools that didn't use xml
+     register descriptions.  -->
+
 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
 <feature name="org.gnu.gdb.riscv.fpu">
 
@@ -13,7 +17,7 @@
     <field name="double" type="ieee_double"/>
   </union>
 
-  <reg name="ft0" bitsize="64" type="riscv_double"/>
+  <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
   <reg name="ft1" bitsize="64" type="riscv_double"/>
   <reg name="ft2" bitsize="64" type="riscv_double"/>
   <reg name="ft3" bitsize="64" type="riscv_double"/>
@@ -46,7 +50,7 @@
   <reg name="ft10" bitsize="64" type="riscv_double"/>
   <reg name="ft11" bitsize="64" type="riscv_double"/>
 
-  <reg name="fflags" bitsize="32" type="int"/>
-  <reg name="frm" bitsize="32" type="int"/>
-  <reg name="fcsr" bitsize="32" type="int"/>
+  <reg name="fflags" bitsize="32" type="int" regnum="66"/>
+  <reg name="frm" bitsize="32" type="int" regnum="67"/>
+  <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
 </feature>