sim: testsuite: flatten tree

Now that all port tests live under testsuite/sim/*/, and none live
in testsuite/ directly, flatten the structure by moving all of the
dirs under testsuite/sim/ to testsuite/ directly.

We need to stop passing --tool to dejagnu so that it searches all
dirs and not just ones that start with "sim".  Since we have no
other dirs in this tree, and no plans to add any, should be fine.

sim/testsuite/m32r/ChangeLog

@@ -0,0 +1,126 @@
+2021-01-15  Mike Frysinger  <vapier@gentoo.org>
+
+	* exit47.ms: New testcase from ../../m32r-elf/.
+
+1999-04-21  Doug Evans  <devans@casey.cygnus.com>
+
+	* nop.cgs: Add missing nop insn.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* allinsn.exp: Set all_machs.
+	* misc.exp: Likewise.
+
+1998-12-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* hello.ms: Add trailing \n to expected output.
+	* hw-trap.ms: Ditto.
+
+	* trap.cgs: Properly align trap2_handler.
+
+	* uread16.ms: New testcase.
+	* uread32.ms: New testcase.
+	* uwrite16.ms: New testcase.
+	* uwrite32.ms: New testcase.
+
+Tue Sep 15 14:56:22 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* testutils.inc (test_h_gr): Use mvaddr_h_gr.
+	* rte.cgs: Test bbpc,bbpsw.
+	* trap.cgs: Test bbpc,bbpsw.
+
+Wed Jul  1 15:57:54 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* hw-trap.ms: New testcase.
+
+Wed Jun 10 10:53:20 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* addx.cgs: Add another test.
+	* jmp.cgs: Add another test.
+
+Mon Jun  8 16:08:27 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* trap.cgs: Test trap 2.
+
+Tue Apr 21 10:49:03 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* addx.cgs: Test (-1)+(-1)+1.
+
+Fri Apr 17 16:00:52 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* mv[ft]achi.cgs: Fix expected result
+	(sign extension of top 8 bits).
+
+Fri Feb 20 11:00:02 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* unlock.cgs: Fixed test.
+	* mvfc.cgs: Fixed test.
+	* remu.cgs: Fixed test.
+	* bnc24.cgs: Test long BNC instruction.
+	* bnc8.cgs: Test short BNC instruction.
+	* ld-plus.cgs: Test LD instruction.
+	* macwhi.cgs: Test MACWHI instruction.
+	* macwlo.cgs: Test MACWLO instruction.
+	* mulwhi.cgs: Test MULWHI instruction.
+	* mulwlo.cgs: Test MULWLO instruction.
+	* mvfachi.cgs: Test MVFACHI instruction.
+	* mvfaclo.cgs: Test MVFACLO instruction.
+	* mvtaclo.cgs: Test MVTACLO instruction.
+	* addv.cgs: Test ADDV instruction.
+	* addv3.cgs: Test ADDV3 instruction.
+	* addx.cgs: Test ADDX instruction.
+	* lock.cgs: Test LOCK instruction.
+	* neg.cgs: Test NEG instruction.
+	* not.cgs: Test NOT instruction.
+	* unlock.cgs: Test UNLOCK instruction.
+
+Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* testutils.inc (mvaddr_h_gr): new macro to load an
+	address into a general register.
+
+	* or3.cgs: Test OR3 instruction.
+	* rach.cgs: Test RACH instruction.
+	* rem.cgs: Test REM instruction.
+	* sub.cgs: Test SUB instruction.
+	* mv.cgs: Test MV instruction.
+	* mul.cgs: Test MUL instruction.
+	* bl24.cgs: Test long BL instruction.
+	* bl8.cgs: Test short BL instruction.
+	* blez.cgs: Test BLEZ instruction.
+	* bltz.cgs: Test BLTZ instruction.
+	* bne.cgs: Test BNE instruction.
+	* bnez.cgs: Test BNEZ instruction.
+	* bra24.cgs: Test long BRA instruction.
+	* bra8.cgs: Test short BRA instruction.
+	* jl.cgs: Test JL instruction.
+	* or.cgs: Test OR instruction.
+	* jmp.cgs: Test JMP instruction.
+	* and.cgs: Test AND instruction.
+	* and3.cgs: Test AND3 instruction.
+	* beq.cgs: Test BEQ instruction.
+	* beqz.cgs: Test BEQZ instruction.
+	* bgez.cgs: Test BGEZ instruction.
+	* bgtz.cgs: Test BGTZ instruction.
+	* cmp.cgs: Test CMP instruction.
+	* cmpi.cgs: Test CMPI instruction.
+	* cmpu.cgs: Test CMPU instruction.
+	* cmpui.cgs: Test CMPUI instruction.
+	* div.cgs: Test DIV instruction.
+	* divu.cgs: Test DIVU instruction.
+	* cmpeq.cgs: Test CMPEQ instruction.
+	* sll.cgs: Test SLL instruction.
+	* sll3.cgs: Test SLL3 instruction.
+	* slli.cgs: Test SLLI instruction.
+	* sra.cgs: Test SRA instruction.
+	* sra3.cgs: Test SRA3 instruction.
+	* srai.cgs: Test SRAI instruction.
+	* srl.cgs: Test SRL instruction.
+	* srl3.cgs: Test SRL3 instruction.
+	* srli.cgs: Test SRLI instruction.
+	* xor3.cgs: Test XOR3 instruction.
+	* xor.cgs: Test XOR instruction.
+
+Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* *: m32r dejagnu simulator testsuite.

sim/testsuite/m32r/add.cgs

@@ -0,0 +1,16 @@
+# m32r testcase for add $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global add
+add:
+
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 2
+	add r4, r5
+	test_h_gr r4, 3
+
+	pass

sim/testsuite/m32r/add3.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for add3 $dr,$sr,#$slo16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global add3
+add3:
+
+	mvi_h_gr r5, 1
+	add3 r4, r5, 2
+	test_h_gr r4, 3
+
+	pass

sim/testsuite/m32r/addi.cgs

@@ -0,0 +1,16 @@
+# m32r testcase for addi $dr,#$simm8
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global addi
+addi:
+
+	mvi_h_gr r5, 1
+	addi r5, 2
+	test_h_gr r5, 3
+
+	pass
+

sim/testsuite/m32r/addv.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for addv $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global addv
+addv:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 0x80000000
+	mvi_h_gr r5, 0x80000000
+
+	addv r4, r5
+
+	bnc not_ok
+	test_h_gr r4, 0
+	
+	pass
+not_ok:
+	fail

sim/testsuite/m32r/addv3.cgs

@@ -0,0 +1,28 @@
+# m32r testcase for addv3 $dr,$sr,#$simm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global addv3
+addv3:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 1
+
+	addv3 r4, r5, #2
+
+	bc not_ok
+
+	test_h_gr r4, 3
+
+	mvi_h_gr r5, 0x7fff8001
+
+	addv3 r4, r5, #0x7fff
+
+	bnc not_ok
+
+	pass
+not_ok:
+	fail

sim/testsuite/m32r/addx.cgs

@@ -0,0 +1,42 @@
+# m32r testcase for addx $dr,$sr
+# mach(): m32r m32rx
+# timeout(): 42
+
+# timeout is set to test it
+
+	.include "testutils.inc"
+
+	start
+
+	.global addx
+addx:
+	mvi_h_condbit 1
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 2
+	addx r4, r5
+	bc not_ok
+	test_h_gr r4, 4
+
+	mvi_h_gr r4, 0xfffffffe
+	addx r4, r5
+	bnc not_ok
+	test_h_gr r4, 0
+
+	mvi_h_gr r4, -1
+	mvi_h_gr r5, -1
+	mvi_h_condbit 1
+	addx r4,r5
+	bnc not_ok
+	test_h_gr r4, -1
+
+	mvi_h_gr r4,-1
+	mvi_h_gr r5,0x7fffffff
+	mvi_h_condbit 1
+	addx r5,r4
+	bnc not_ok
+	test_h_gr r5,0x7fffffff
+
+	pass
+
+not_ok:
+	fail

sim/testsuite/m32r/allinsn.exp

@@ -0,0 +1,21 @@
+# M32R simulator testsuite.
+
+if [istarget m32r*-*-*] {
+    # load support procs
+    # load_lib cgen.exp
+
+    # all machines
+    set all_machs "m32r"
+
+
+    # The .cgs suffix is for "cgen .s".
+    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
+	# If we're only testing specific files and this isn't one of them,
+	# skip it.
+	if ![runtest_file_p $runtests $src] {
+	    continue
+	}
+
+	run_sim_test $src $all_machs
+    }
+}

sim/testsuite/m32r/and.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for and $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global and
+and:
+	mvi_h_gr r4, 3
+	mvi_h_gr r5, 6
+
+	and r4, r5
+
+	test_h_gr r4, 2
+
+	pass

sim/testsuite/m32r/and3.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for and3 $dr,$sr,#$uimm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global and3
+and3:
+	mvi_h_gr r4, 0
+	mvi_h_gr r5, 6
+
+	and3 r4, r5, #3
+
+	test_h_gr r4, 2
+
+	pass

sim/testsuite/m32r/bc24.cgs

@@ -0,0 +1,24 @@
+# m32r testcase for bc $disp24
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bc24
+bc24:
+
+	mvi_h_condbit 0
+	bc.l test0fail
+	bra test0pass
+test0fail:
+	fail
+test0pass:
+
+	mvi_h_condbit 1
+	bc.l test1pass
+	fail
+test1pass:
+
+	pass
+

sim/testsuite/m32r/bc8.cgs

@@ -0,0 +1,23 @@
+# m32r testcase for bc $disp8
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bc8
+bc8:
+
+	mvi_h_condbit 0
+	bc.s test0fail
+	bra test0pass
+test0fail:
+	fail
+test0pass:
+
+	mvi_h_condbit 1
+	bc.s test1pass
+	fail
+test1pass:
+
+	pass

sim/testsuite/m32r/beq.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for beq $src1,$src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global beq
+beq:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 12
+	mvi_h_gr r5, 12
+	beq r4, r5, ok
+not_ok:
+	fail
+ok:
+	mvi_h_gr r5, 11
+	beq r4, r5, not_ok
+
+	pass

sim/testsuite/m32r/beqz.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for beqz $src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global beqz
+beqz:
+	mvi_h_gr r4, 0
+	beqz r4, ok
+not_ok:
+	fail
+ok:
+	mvi_h_gr r4, 1
+	beqz r4, not_ok
+
+	pass

sim/testsuite/m32r/bgez.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for bgez $src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bgez
+bgez:
+	mvi_h_gr r4, 1
+	bgez r4, ok
+not_ok:
+	fail
+ok:
+	mvi_h_gr r4, -1
+	bgez r4, not_ok
+
+	pass

sim/testsuite/m32r/bgtz.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for bgtz $src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bgtz
+bgtz:
+	mvi_h_gr r4, 1
+	bgtz r4, ok
+not_ok:
+	fail
+ok:
+	mvi_h_gr r4, 0
+	bgtz r4, not_ok
+
+	pass

sim/testsuite/m32r/bl24.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for bl $disp24
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bl24
+bl24:
+	bl.l test0pass
+test1fail:
+	fail
+
+test0pass:
+	mvaddr_h_gr r4, test1fail
+	bne  r4, r14, test1fail
+
+	pass

sim/testsuite/m32r/bl8.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for bl $disp8
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bl8
+bl8:
+	bl.s test0pass
+test1fail:
+	fail
+
+test0pass:
+	mvaddr_h_gr r4, test1fail
+	bne  r4, r14, test1fail
+
+	pass

sim/testsuite/m32r/blez.cgs

@@ -0,0 +1,19 @@
+# m32r testcase for blez $src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global blez
+blez:
+	mvi_h_gr r4, 0
+	blez r4, test0pass
+test1fail:
+	fail
+
+test0pass:
+	mvi_h_gr r4, 1
+	blez r4, test1fail
+
+	pass

sim/testsuite/m32r/bltz.cgs

@@ -0,0 +1,19 @@
+# m32r testcase for bltz $src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bltz
+bltz:
+	mvi_h_gr r4, -1
+	bltz r4, test0pass
+test1fail:
+	fail
+
+test0pass:
+	mvi_h_gr r4, 0
+	bltz r4, test1fail
+
+	pass

sim/testsuite/m32r/bnc24.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for bnc $disp24
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bnc24
+bnc24:
+	mvi_h_condbit 0
+	bnc.l test0pass
+
+test1fail:
+	fail
+test0pass:
+
+	mvi_h_condbit 1
+	bnc.l test1fail
+
+	pass

sim/testsuite/m32r/bnc8.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for bnc $disp8
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bnc8
+bnc8:
+	mvi_h_condbit 0
+	bnc.s test0pass
+
+test1fail:
+	fail
+
+test0pass:
+	mvi_h_condbit 1
+	bnc.s test1fail
+
+	pass

sim/testsuite/m32r/bne.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for bne $src1,$src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bne
+bne:
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 2
+	bne r4, r5, test0pass
+test1fail:
+	fail
+
+test0pass:
+	mvi_h_gr r4, 2
+	bne r4, r5, test1fail
+
+	pass

sim/testsuite/m32r/bnez.cgs

@@ -0,0 +1,19 @@
+# m32r testcase for bnez $src2,$disp16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bnez
+bnez:
+	mvi_h_gr r4, 1
+	bnez r4, test0pass
+test1fail:
+	fail
+
+test0pass:
+	mvi_h_gr r4, 0
+	bnez r4, test1fail
+
+	pass

sim/testsuite/m32r/bra24.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for bra $disp24
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bra24
+bra24:
+	bra.l ok
+
+	fail
+
+ok:
+	pass

sim/testsuite/m32r/bra8.cgs

@@ -0,0 +1,14 @@
+# m32r testcase for bra $disp8
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global bra8
+bra8:
+	bra.s ok
+
+	fail
+ok:
+	pass

sim/testsuite/m32r/cmp.cgs

@@ -0,0 +1,23 @@
+# m32r testcase for cmp $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global cmp
+cmp:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 2
+	cmp r4, r5
+	bc ok
+not_ok:
+	fail
+ok:
+	mvi_h_condbit 1
+	mvi_h_gr r4, 2
+	cmp r4, r5
+	bc not_ok
+
+	pass

sim/testsuite/m32r/cmpi.cgs

@@ -0,0 +1,24 @@
+# m32r testcase for cmpi $src2,#$simm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global cmpi
+cmpi:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+
+	cmpi r4, #2
+	bc ok
+not_ok:
+	fail
+ok:
+	mvi_h_condbit 1
+	mvi_h_gr r4, 2
+	cmpi r4, #2
+	bc not_ok
+
+
+	pass

sim/testsuite/m32r/cmpu.cgs

@@ -0,0 +1,23 @@
+# m32r testcase for cmpu $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global cmpu
+cmpu:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, -2
+	cmpu r4, r5
+	bc ok
+not_ok:
+	fail
+ok:
+	mvi_h_condbit 1
+	mvi_h_gr r4, -1
+	cmpu r4, r5
+	bc not_ok
+
+	pass

sim/testsuite/m32r/cmpui.cgs

@@ -0,0 +1,22 @@
+# m32r testcase for cmpui $src2,#$simm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global cmpui
+cmpui:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+	cmpui r4, #2
+	bc ok
+not_ok:
+	fail
+ok:
+	mvi_h_condbit 1
+	mvi_h_gr r4, -1
+	cmpui r4, #2
+	bc not_ok
+
+	pass

sim/testsuite/m32r/div.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for div $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global div
+div:
+	mvi_h_gr r4, 0x18000
+	mvi_h_gr r5, 8
+
+	div r4, r5
+
+	test_h_gr r4, 0x3000
+
+	pass

sim/testsuite/m32r/divu.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for divu $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global divu
+divu:
+	mvi_h_gr r4, 0x18000
+	mvi_h_gr r5, 8
+
+	divu r4, r5
+
+	test_h_gr r4, 0x3000
+
+	pass

sim/testsuite/m32r/exit47.ms

@@ -0,0 +1,11 @@
+# mach(): m32r m32rx
+# status: 47
+# output:
+
+	;; Return with exit code 47.
+
+	.globl _start
+_start:
+	ldi8 r1,#47
+	ldi8 r0,#1
+	trap #0

sim/testsuite/m32r/hello.ms

@@ -0,0 +1,19 @@
+# output(): Hello world!\n
+# mach(): m32r m32rx
+
+	.globl _start
+_start:
+
+; write (hello world)
+	ldi8 r3,#14
+	ld24 r2,#hello
+	ldi8 r1,#1
+	ldi8 r0,#5
+	trap #0
+; exit (0)
+	ldi8 r1,#0
+	ldi8 r0,#1
+	trap #0
+
+length:	.long 14
+hello:	.ascii "Hello world!\r\n"

sim/testsuite/m32r/hw-trap.ms

@@ -0,0 +1,31 @@
+# mach(): m32r m32rx
+# output(): pass\n
+
+	.include "testutils.inc"
+
+	start
+
+; construct bra trap2_handler in trap 2 slot
+	ld24 r0,#bra_insn
+	ld r0,@r0
+	ld24 r1,#trap2_handler
+	addi r1,#-0x48 ; pc relative address from trap 2 slot to handler
+	srai r1,#2
+	or r0,r1
+	ld24 r2,#0x48 ; address of trap 2 slot
+	st r0,@r2
+
+; perform trap
+	ldi r4,#0
+	trap #2
+	test_h_gr r4,42
+
+	pass
+
+; trap 2 handler
+trap2_handler:
+	ldi r4,#42
+	rte
+
+bra_insn:
+	bra.l 0

sim/testsuite/m32r/jl.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for jl $sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global jl
+jl:
+	mvaddr_h_gr r4, ok
+	jl   r4
+not_ok:
+	fail
+ok:
+	mvaddr_h_gr r4, not_ok
+	bne  r4, r14, not_ok
+
+	pass

sim/testsuite/m32r/jmp.cgs

@@ -0,0 +1,19 @@
+# m32r testcase for jmp $sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global jmp
+jmp:
+	mvaddr_h_gr r4, ok1
+	jmp  r4
+	fail
+ok1:
+	mvaddr_h_gr r4, ok2
+	addi r4,#1
+	jmp r4
+	fail
+ok2:
+	pass

sim/testsuite/m32r/ld-d.cgs

@@ -0,0 +1,22 @@
+# m32r testcase for ld $dr,@($slo16,$sr)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ld_d
+ld_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ld r5, @(#4, r4)
+
+	test_h_gr r5, 0x12345678 
+
+	pass
+
+data_loc:
+	.word 0x11223344
+	.word 0x12345678
+

sim/testsuite/m32r/ld-plus.cgs

@@ -0,0 +1,28 @@
+# m32r testcase for ld $dr,@$sr+
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ld_plus
+ld_plus:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ld r5, @r4+
+
+	test_h_gr r5, 0x12345678
+
+	mvaddr_h_gr r5, data_loc2
+	bne r4, r5, not_ok
+
+	pass
+not_ok:
+	fail
+
+data_loc:
+	.word 0x12345678
+data_loc2:
+	.word 0x11223344
+

sim/testsuite/m32r/ld.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for ld $dr,@$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ld
+ld:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ld r5, @r4
+
+	test_h_gr r5, 0x12345678
+
+	pass
+
+data_loc:
+	.word 0x12345678
+

sim/testsuite/m32r/ld24.cgs

@@ -0,0 +1,14 @@
+# m32r testcase for ld24 $dr,#$uimm24
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ld24
+ld24:
+	ld24 r4, #0x123456
+
+	test_h_gr r4, 0x123456
+
+	pass

sim/testsuite/m32r/ldb-d.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for ldb $dr,@($slo16,$sr)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldb_d
+ldb_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ldb r5, @(#2, r4)
+
+	test_h_gr r5, 0x56 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x12345678

sim/testsuite/m32r/ldb.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for ldb $dr,@$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldb
+ldb:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ldb r5, @r4
+
+	test_h_gr r5, 0x12 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x12345678
+

sim/testsuite/m32r/ldh-d.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for ldh $dr,@($slo16,$sr)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldh_d
+ldh_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ldh r5, @(#2, r4)
+
+	test_h_gr r5, 0x5678 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x12345678
+

sim/testsuite/m32r/ldh.cgs

@@ -0,0 +1,22 @@
+# m32r testcase for ldh $dr,@$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldh
+ldh:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ldh r5, @r4
+
+	test_h_gr r5, 0x1234 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x12345678
+
+	pass

sim/testsuite/m32r/ldi16.cgs

@@ -0,0 +1,14 @@
+# m32r testcase for ldi $dr,$slo16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldi16
+ldi16:
+	ldi r4, #0x1234
+
+	test_h_gr r4, 0x1234
+
+	pass

sim/testsuite/m32r/ldi8.cgs

@@ -0,0 +1,14 @@
+# m32r testcase for ldi $dr,#$simm8
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldi8
+ldi8:
+	ldi r4, #0x78
+
+	test_h_gr r4, 0x78
+
+	pass

sim/testsuite/m32r/ldub-d.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for ldub $dr,@($slo16,$sr)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldub_d
+ldub_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ldub r5, @(#2, r4)
+
+	test_h_gr r5, 0xa0 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x8090a0b0
+

sim/testsuite/m32r/ldub.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for ldub $dr,@$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global ldub
+ldub:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	ldub r5, @r4
+
+	test_h_gr r5, 0x80 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x800000f0
+

sim/testsuite/m32r/lduh-d.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for lduh $dr,@($slo16,$sr)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global lduh_d
+lduh_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	lduh r5, @(#2, r4)
+
+	test_h_gr r5, 0xf000 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x8000f000

sim/testsuite/m32r/lduh.cgs

@@ -0,0 +1,22 @@
+# m32r testcase for lduh $dr,@$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global lduh
+lduh:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	lduh r5, @r4
+
+	test_h_gr r5, 0x8010 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0x8010f020
+
+	pass

sim/testsuite/m32r/lock.cgs

@@ -0,0 +1,25 @@
+# m32r testcase for lock $dr,@$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global lock
+lock:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0
+
+	lock r5, @r4
+
+	test_h_gr r5, 0x12345678
+
+	; There is no way to test the lock bit
+
+	unlock r5, @r4 	; Unlock the processor
+
+	pass
+
+data_loc:
+	.word 0x12345678
+

sim/testsuite/m32r/machi.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for machi $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global machi
+machi:
+
+	mvi_h_accum0 0, 1
+	mvi_h_gr r4, 0x10123
+	mvi_h_gr r5, 0x20456
+	machi r4, r5
+	test_h_accum0 0, 0x20001
+
+	pass

sim/testsuite/m32r/maclo.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for maclo $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global maclo
+maclo:
+
+	mvi_h_accum0 0, 1
+	mvi_h_gr r4, 0x1230001
+	mvi_h_gr r5, 0x4560002
+	maclo r4, r5
+	test_h_accum0 0, 0x20001
+
+	pass

sim/testsuite/m32r/macwhi.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for macwhi $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global macwhi
+macwhi:
+	mvi_h_accum0 0, 1
+	mvi_h_gr r4, 0x10123
+	mvi_h_gr r5, 0x20456
+
+	macwhi r4, r5
+
+	test_h_accum0 0, 0x20247
+
+	pass

sim/testsuite/m32r/macwlo.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for macwlo $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global macwlo
+macwlo:
+	mvi_h_accum0 0, 1
+	mvi_h_gr r4, 0x10123
+	mvi_h_gr r5, 0x40002
+
+	macwlo r4, r5
+
+	test_h_accum0 0, 0x20247
+
+	pass

sim/testsuite/m32r/misc.exp

@@ -0,0 +1,21 @@
+# Miscellaneous M32R simulator testcases
+
+if [istarget m32r*-*-*] {
+    # load support procs
+    # load_lib cgen.exp
+
+    # all machines
+    set all_machs "m32r"
+
+
+    # The .ms suffix is for "miscellaneous .s".
+    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.ms]] {
+	# If we're only testing specific files and this isn't one of them,
+	# skip it.
+	if ![runtest_file_p $runtests $src] {
+	    continue
+	}
+
+	run_sim_test $src $all_machs
+    }
+}

sim/testsuite/m32r/mul.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for mul $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mul
+mul:
+	mvi_h_gr r4, 3
+	mvi_h_gr r5, 7
+
+	mul r5, r4
+
+	test_h_gr r5, 21
+
+	pass

sim/testsuite/m32r/mulhi.cgs

@@ -0,0 +1,16 @@
+# m32r testcase for mulhi $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mulhi
+mulhi:
+
+	mvi_h_gr r4, 0x40000
+	mvi_h_gr r5, 0x50000
+	mulhi r4, r5
+	test_h_accum0 0, 0x140000
+
+	pass

sim/testsuite/m32r/mullo.cgs

@@ -0,0 +1,16 @@
+# m32r testcase for mullo $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mullo
+mullo:
+
+	mvi_h_gr r4, 4
+	mvi_h_gr r5, 5
+	mullo r4, r5
+	test_h_accum0 0, 0x140000
+
+	pass

sim/testsuite/m32r/mulwhi.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for mulwhi $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mulwhi
+mulwhi:
+	mvi_h_accum0 0, 1
+	mvi_h_gr r4, 0x10123
+	mvi_h_gr r5, 0x20456
+
+	mulwhi r4, r5
+
+	test_h_accum0 0, 0x20246
+
+	pass

sim/testsuite/m32r/mulwlo.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for mulwlo $src1,$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mulwlo
+mulwlo:
+	mvi_h_accum0 0, 1
+	mvi_h_gr r4, 0x10123
+	mvi_h_gr r5, 0x40002
+
+	mulwlo r4, r5
+
+	test_h_accum0 0, 0x20246
+
+	pass

sim/testsuite/m32r/mv.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for mv $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mv
+mv:
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 0
+
+	mv r5, r4
+
+	test_h_gr r5, 1
+
+	pass

sim/testsuite/m32r/mvfachi.cgs

@@ -0,0 +1,22 @@
+# m32r testcase for mvfachi $dr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvfachi
+mvfachi:
+	mvi_h_accum0 0x11223344, 0x55667788
+	mvi_h_gr r4, 0
+
+	mvfachi r4
+	test_h_gr r4, 0x223344
+
+	mvi_h_accum0 0x99aabbcc, 0x55667788
+	mvi_h_gr r4, 0
+
+	mvfachi r4
+	test_h_gr r4, 0xffaabbcc
+
+	pass

sim/testsuite/m32r/mvfaclo.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for mvfaclo $dr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvfaclo
+mvfaclo:
+	mvi_h_accum0 0x11223344, 0x55667788
+	mvi_h_gr r4, 0
+
+	mvfaclo r4
+
+	test_h_gr r4, 0x55667788
+
+	pass

sim/testsuite/m32r/mvfacmi.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for mvfacmi $dr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvfacmi
+mvfacmi:
+
+	mvi_h_accum0 0x12345678, 0x87654321
+	mvfacmi r4
+	test_h_gr r4, 0x56788765
+
+	pass

sim/testsuite/m32r/mvfc.cgs

@@ -0,0 +1,23 @@
+# m32r testcase for mvfc $dr,$scr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvfc
+mvfc:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+
+	mvfc r4, cr1
+
+	test_h_gr r4, 0
+
+	mvi_h_condbit 1
+
+	mvfc r4, cr1
+
+	test_h_gr r4, 1
+
+	pass

sim/testsuite/m32r/mvtachi.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for mvtachi $src1
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvtachi
+mvtachi:
+	mvi_h_accum0 0, 0
+
+	mvi_h_gr r4, 0x11223344
+	mvtachi r4
+	test_h_accum0 0x223344, 0x0
+
+	mvi_h_gr r4, 0x99aabbcc
+	mvtachi r4
+	test_h_accum0 0xffaabbcc, 0x0
+
+	pass

sim/testsuite/m32r/mvtaclo.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for mvtaclo $src1
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvtaclo
+mvtaclo:
+	mvi_h_accum0 0, 0
+	mvi_h_gr r4, 0x11223344
+
+	mvtaclo r4
+
+	test_h_accum0 0, 0x11223344
+
+	pass

sim/testsuite/m32r/mvtc.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for mvtc $sr,$dcr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global mvtc
+mvtc:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 1
+
+	mvtc r4, cr1
+	bc ok
+
+	fail
+ok:
+	pass

sim/testsuite/m32r/neg.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for neg $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global neg
+neg:
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 2
+
+	neg r4, r5
+
+	test_h_gr r4, -2
+
+	pass

sim/testsuite/m32r/nop.cgs

@@ -0,0 +1,11 @@
+# m32r testcase for nop
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global nop
+nop:
+	nop
+	pass

sim/testsuite/m32r/not.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for not $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global not
+not:
+	mvi_h_gr r4, 1
+	mvi_h_gr r5, 2
+
+	not r4, r5
+
+	test_h_gr r4, 0xfffffffd
+
+	pass

sim/testsuite/m32r/or.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for or $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global or
+or:
+	mvi_h_gr r4, 3
+	mvi_h_gr r5, 6
+
+	or r4, r5
+
+	test_h_gr r4, 7
+
+	pass

sim/testsuite/m32r/or3.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for or3 $dr,$sr,#$ulo16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global or3
+or3:
+	mvi_h_gr r4, 0
+	mvi_h_gr r5, 6
+
+	or3 r4, r5, #3
+
+	test_h_gr r4, 7
+
+	pass

sim/testsuite/m32r/rac.cgs

@@ -0,0 +1,23 @@
+# m32r testcase for rac
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global rac
+rac:
+
+	mvi_h_accum0 1, 0x4001
+	rac
+	test_h_accum0 2, 0x10000
+
+	mvi_h_accum0 0x3fff, 0xffff4000
+	rac
+	test_h_accum0 0x7fff, 0xffff0000
+
+	mvi_h_accum0 0xffff8000, 0
+	rac
+	test_h_accum0 0xffff8000, 0
+
+	pass

sim/testsuite/m32r/rach.cgs

@@ -0,0 +1,22 @@
+# m32r testcase for rach
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global rach
+rach:
+	mvi_h_accum0 1, 0x40004001
+	rach
+	test_h_accum0 3, 0
+
+	mvi_h_accum0 0x3fff, 0xc0000000
+	rach
+	test_h_accum0 0x7fff, 0
+
+	mvi_h_accum0 0xffff8000, 0
+	rach
+	test_h_accum0 0xffff8000, 0
+
+	pass

sim/testsuite/m32r/rem.cgs

@@ -0,0 +1,17 @@
+# m32r testcase for rem $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global rem
+rem:
+	mvi_h_gr r4, 12345678
+	mvi_h_gr r5, 7
+
+	rem r4, r5
+
+	test_h_gr r4, 2
+
+	pass

sim/testsuite/m32r/remu.cgs

@@ -0,0 +1,23 @@
+# m32r testcase for remu $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global remu
+remu:
+	mvi_h_gr r4, 17
+	mvi_h_gr r5, 7
+
+	remu r4, r5
+
+	test_h_gr r4, 3
+
+	mvi_h_gr r4, -17
+
+	remu r4, r5
+
+	test_h_gr r4, 1
+
+	pass

sim/testsuite/m32r/rte.cgs

@@ -0,0 +1,87 @@
+# m32r testcase for rte
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global rte
+rte:
+
+; Test 1: bbpsw = 0, bpsw = 1, psw = 0
+
+	; bbsm = 0, bie = 0, bbcond = 0
+	mvi_h_gr r4, 0
+	mvtc r4, cr8
+
+	; bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
+	mvi_h_gr r4, 0xc100
+	mvtc r4, cr0
+
+	; bbpc = 0
+	mvaddr_h_gr r4, 0
+	mvtc r4, bbpc
+
+	; bpc = ret1
+	mvaddr_h_gr r4, ret1
+	mvtc r4, bpc
+
+	rte
+	fail
+
+ret1:
+	; test bbsm = 0, bbie = 0, bbcond = 0
+	mvfc r4, cr8
+	test_h_gr r4, 0
+
+	; test bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
+	mvfc r4, cr0
+	test_h_gr r4, 0xc1
+
+	; test bbpc = 0
+	mvfc r4, bbpc
+	test_h_gr r4, 0
+
+	; test bpc = 0
+	mvfc r4, bpc
+	test_h_gr r4, 0
+
+; Test 2: bbpsw = 1, bpsw = 0, psw = 1
+
+	; bbsm = 1, bie = 1, bbcond = 1
+	mvi_h_gr r4, 0xc1
+	mvtc r4, cr8
+
+	; bsm = 0, bie = 0, bcond = 0, sm = 1, ie = 1, cond = 1
+	mvi_h_gr r4, 0xc1
+	mvtc r4, cr0
+
+	; bbpc = 42
+	mvaddr_h_gr r4, 42
+	mvtc r4, bbpc
+
+	; bpc = ret2 + 2
+	mvaddr_h_gr r4, ret2 + 2
+	mvtc r4, bpc
+
+	rte
+	fail
+
+ret2:
+	; test bbsm = 1, bbie = 1, bbcond = 1
+	mvfc r4, cr8
+	test_h_gr r4, 0xc1
+
+	; test bsm = 1, bie = 1, bcond = 1, sm = 0, ie = 0, cond = 0
+	mvfc r4, cr0
+	test_h_gr r4, 0xc100
+
+	; test bbpc = 42
+	mvfc r4, bbpc
+	test_h_gr r4, 42
+
+	; test bpc = 42
+	mvfc r4, bpc
+	test_h_gr r4, 42
+
+	pass

sim/testsuite/m32r/seth.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for seth $dr,#$hi16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global seth
+seth:
+	seth      r4, #0x1234
+
+	; do not use test_h_gr macro since this uses seth
+
+	srli      r4, #16
+	ld24	  r5, #0x1234
+	beq       r4, r5, ok
+
+	fail
+ok:
+	pass

sim/testsuite/m32r/sll.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for sll $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sll
+sll:
+	mvi_h_gr  r4, 6
+	mvi_h_gr  r5, 1
+	sll       r4, r5
+	test_h_gr r4, 12
+
+	pass

sim/testsuite/m32r/sll3.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for sll3 $dr,$sr,#$simm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sll3
+sll3:
+	mvi_h_gr  r4, 1
+	mvi_h_gr  r5, 6
+	sll3      r4, r5, #1
+	test_h_gr r4, 12
+
+	pass

sim/testsuite/m32r/slli.cgs

@@ -0,0 +1,14 @@
+# m32r testcase for slli $dr,#$uimm5
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global slli
+slli:
+	mvi_h_gr  r4, 6
+	slli      r4, #1
+	test_h_gr r4, 12
+
+	pass

sim/testsuite/m32r/sra.cgs

@@ -0,0 +1,16 @@
+# m32r testcase for sra $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sra
+sra:
+
+	mvi_h_gr  r4, 0xf0f0f0ff
+	mvi_h_gr  r5, 4
+	sra       r4, r5
+	test_h_gr r4, 0xff0f0f0f
+
+	pass

sim/testsuite/m32r/sra3.cgs

@@ -0,0 +1,16 @@
+# m32r testcase for sra3 $dr,$sr,#$simm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sra3
+sra3:
+
+	mvi_h_gr  r4, 0
+	mvi_h_gr  r5, 0xf0f0f0ff
+	sra3      r4, r5, #4
+	test_h_gr r4, 0xff0f0f0f
+
+	pass

sim/testsuite/m32r/srai.cgs

@@ -0,0 +1,14 @@
+# m32r testcase for srai $dr,#$uimm5
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global srai
+srai:
+	mvi_h_gr  r5, 0xf0f0f0ff
+	srai      r5, #4
+	test_h_gr r5, 0xff0f0f0f
+
+	pass

sim/testsuite/m32r/srl.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for srl $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global srl
+srl:
+	mvi_h_gr  r4, 6
+	mvi_h_gr  r5, 1
+	srl       r4, r5
+	test_h_gr r4, 3
+
+	pass

sim/testsuite/m32r/srl3.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for srl3 $dr,$sr,#$simm16
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global srl3
+srl3:
+	mvi_h_gr  r4, 0
+	mvi_h_gr  r5, 6
+	srl3      r4, r5, #1
+	test_h_gr r4, 3
+
+	pass

sim/testsuite/m32r/srli.cgs

@@ -0,0 +1,15 @@
+# m32r testcase for srli $dr,#$uimm5
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global srli
+srli:
+	mvi_h_gr  r5, 6
+	srli      r5, #1
+	test_h_gr r5, 3
+
+
+	pass

sim/testsuite/m32r/st-d.cgs

@@ -0,0 +1,26 @@
+# m32r testcase for st $src1,@($slo16,$src2)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global st_d
+st_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 1
+
+	st r5, @(#8,r4)
+
+	mvaddr_h_gr r4, data_loc2
+	ld r4, @r4
+	test_h_gr r4, 1
+
+	pass
+
+data_loc:
+	.word 0
+	.word 0
+data_loc2:
+	.word 0
+

sim/testsuite/m32r/st-minus.cgs

@@ -0,0 +1,29 @@
+# m32r testcase for st $src1,@-$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global st_minus
+st_minus:
+	mvaddr_h_gr r4, data_loc2
+	mvi_h_gr    r5, 1
+
+	st r5, @-r4
+
+	mvaddr_h_gr r5, data_loc
+
+	bne r4, r5, not_ok
+	ld r4, @r4
+	test_h_gr r4, 1
+
+	pass
+not_ok:
+	fail
+
+data_loc:
+	.word 0
+data_loc2:
+	.word 0
+

sim/testsuite/m32r/st-plus.cgs

@@ -0,0 +1,28 @@
+# m32r testcase for st $src1,@+$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global st_plus
+st_plus:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 1
+
+	st r5, @+r4
+
+	mvaddr_h_gr r5, data_loc2
+
+	bne r4, r5, not_ok
+	ld r4, @r4
+	test_h_gr r4, 1
+
+	pass
+not_ok:
+	fail
+
+data_loc:
+	.word 0
+data_loc2:
+	.word 0

sim/testsuite/m32r/st.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for st $src1,@$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global st
+st:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 1
+
+	st r5, @r4
+
+	ld r4, @r4
+	test_h_gr r4, 1
+
+	pass
+
+data_loc:
+	.word 0

sim/testsuite/m32r/stb-d.cgs

@@ -0,0 +1,25 @@
+# m32r testcase for stb $src1,@($slo16,$src2)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global stb_d
+stb_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0x1234
+
+	stb r5, @(#8,r4)
+
+	mvaddr_h_gr r4, data_loc2
+	ld r4, @r4
+	test_h_gr r4, 0x34000000 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0
+	.word 0
+data_loc2:
+	.word 0

sim/testsuite/m32r/stb.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for stb $src1,@$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global stb
+stb:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0x1234
+
+	stb r5, @r4
+
+	ld r4, @r4
+	test_h_gr r4, 0x34000000 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0

sim/testsuite/m32r/sth-d.cgs

@@ -0,0 +1,25 @@
+# m32r testcase for sth $src1,@($slo16,$src2)
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sth_d
+sth_d:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0x123456
+
+	sth r5, @(#8,r4)
+
+	mvaddr_h_gr r4, data_loc2
+	ld r4, @r4
+	test_h_gr r4, 0x34560000 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0
+	.word 0
+data_loc2:
+	.word 0

sim/testsuite/m32r/sth.cgs

@@ -0,0 +1,21 @@
+# m32r testcase for sth $src1,@$src2
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sth
+sth:
+	mvaddr_h_gr r4, data_loc
+	mvi_h_gr    r5, 0x123456
+
+	sth r5, @r4
+
+	ld r4, @r4
+	test_h_gr r4, 0x34560000 ; big endian processor
+
+	pass
+
+data_loc:
+	.word 0

sim/testsuite/m32r/sub.cgs

@@ -0,0 +1,18 @@
+# m32r testcase for sub $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global sub
+sub:
+
+	mvi_h_gr r4, 7
+	mvi_h_gr r5, 3
+
+	sub r4, r5
+
+	test_h_gr r4, 4
+
+	pass

sim/testsuite/m32r/subv.cgs

@@ -0,0 +1,20 @@
+# m32r testcase for subv $dr,$sr
+# mach(): m32r m32rx
+
+	.include "testutils.inc"
+
+	start
+
+	.global subv
+subv:
+	mvi_h_condbit 0
+	mvi_h_gr r4, 0x80000000
+	mvi_h_gr r5, 3
+
+	subv r4, r5
+
+	bc ok
+
+	fail
+ok:
+	pass