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aarch64: Define RME system registers

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This patch introduces RME (Realm Management Extension) system registers.

gas/ChangeLog:

2021-03-01  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* testsuite/gas/aarch64/rme-invalid.d: New test.
	* testsuite/gas/aarch64/rme-invalid.l: New test.
	* testsuite/gas/aarch64/rme-invalid.s: New test.
	* testsuite/gas/aarch64/rme.d: New test.
	* testsuite/gas/aarch64/rme.s: New test.

opcodes/ChangeLog:

2021-03-01  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c: Add RME system registers.
This commit is contained in:
Przemyslaw Wirkus
2021-04-16 15:33:38 +01:00
parent 1b6b755e91
commit 100e914da3
8 changed files with 49 additions and 0 deletions
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8
gas/ChangeLog
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@@ -1,3 +1,11 @@
2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/rme-invalid.d: New test.
* testsuite/gas/aarch64/rme-invalid.l: New test.
* testsuite/gas/aarch64/rme-invalid.s: New test.
* testsuite/gas/aarch64/rme.d: New test.
* testsuite/gas/aarch64/rme.s: New test.
2021-04-16 Nelson Chu <nelson.chu@sifive.com> 2021-04-16 Nelson Chu <nelson.chu@sifive.com>
PR 27436 PR 27436

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gas/testsuite/gas/aarch64/rme-invalid.d Normal file
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@@ -0,0 +1,3 @@
#name: Invalid RME System registers usage
#source: rme-invalid.s
#warning_output: rme-invalid.l

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gas/testsuite/gas/aarch64/rme-invalid.l Normal file
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@@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Warning: specified register cannot be written to at operand 1 -- `msr mfar_el3,x0'

4
gas/testsuite/gas/aarch64/rme-invalid.s Normal file
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@@ -0,0 +1,4 @@
/* Realm Management Extension. */
/* Illegal write to RME system registers. */
msr mfar_el3, x0

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gas/testsuite/gas/aarch64/rme.d Normal file
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@@ -0,0 +1,14 @@
#name: RME System registers
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
0: d53e60a0 mrs x0, mfar_el3
4: d53e21c0 mrs x0, gpccr_el3
8: d53e2180 mrs x0, gptbr_el3
c: d51e21c0 msr gpccr_el3, x0
10: d51e2180 msr gptbr_el3, x0

10
gas/testsuite/gas/aarch64/rme.s Normal file
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@@ -0,0 +1,10 @@
/* Realm Management Extension. */
/* Read from RME system registers. */
mrs x0, mfar_el3
mrs x0, gpccr_el3
mrs x0, gptbr_el3
/* Write to RME system registers. */
msr gpccr_el3, x0
msr gptbr_el3, x0

4
opcodes/ChangeLog
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@@ -1,3 +1,7 @@
2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add RME system registers.
2021-04-16 Lifang Xia <lifang_xia@c-sky.com> 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
* riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress

4
opcodes/aarch64-opc.c
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@@ -4682,6 +4682,10 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0), SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0),
SR_CORE ("mfar_el3", CPENC (3,6,C6,C0,5), F_REG_READ),
SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0),
SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0),
{ 0, CPENC (0,0,0,0,0), 0, 0 } { 0, CPENC (0,0,0,0,0), 0, 0 }
}; };