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MIPS: Remove remnants of 48-bit microMIPS instruction support

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The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.

This complements commit a6c7053929 ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").

References:

[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
    Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
    Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
    Major Opcode Field", p. 578

	gas/
	* config/tc-mips.c (micromips_insn_length): Remove the mention
	of 48-bit microMIPS instructions.

	gdb/
	* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
	instruction support.
	(micromips_next_pc): Likewise.
	(micromips_scan_prologue): Likewise.
	(micromips_deal_with_atomic_sequence): Likewise.
	(micromips_stack_frame_destroyed_p): Likewise.
	(mips_breakpoint_from_pc): Likewise.

	opcodes/
	* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
	instruction support.
This commit is contained in:
Maciej W. Rozycki
2016-01-18 21:29:37 +00:00
parent 3d304f48ca
commit 100b4f2e9f
6 changed files with 27 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
gdb/mips-tdep.c
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@@ -1518,10 +1518,8 @@ mips_insn_size (enum mips_isa isa, ULONGEST insn)
switch (isa)
{
case ISA_MICROMIPS:
if (micromips_op (insn) == 0x1f)
return 3 * MIPS_INSN16_SIZE;
else if (((micromips_op (insn) & 0x4) == 0x4)
|| ((micromips_op (insn) & 0x7) == 0x0))
if ((micromips_op (insn) & 0x4) == 0x4
|| (micromips_op (insn) & 0x7) == 0x0)
return 2 * MIPS_INSN16_SIZE;
else
return MIPS_INSN16_SIZE;
@@ -1881,12 +1879,6 @@ micromips_next_pc (struct frame_info *frame, CORE_ADDR pc)
pc += MIPS_INSN16_SIZE;
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
/* 48-bit instructions. */
case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
/* No branch or jump instructions in this category. */
pc += 2 * MIPS_INSN16_SIZE;
break;
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
insn <<= 16;
@@ -2993,13 +2985,6 @@ micromips_scan_prologue (struct gdbarch *gdbarch,
loc += MIPS_INSN16_SIZE;
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
/* 48-bit instructions. */
case 3 * MIPS_INSN16_SIZE:
/* No prologue instructions in this category. */
this_non_prologue_insn = 1;
loc += 2 * MIPS_INSN16_SIZE;
break;
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
insn <<= 16;
@@ -4041,11 +4026,6 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
its destination address. */
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
/* 48-bit instructions. */
case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */
loc += 2 * MIPS_INSN16_SIZE;
break;
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
switch (micromips_op (insn))
@@ -6769,11 +6749,6 @@ micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
loc += MIPS_INSN16_SIZE;
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
/* 48-bit instructions. */
case 3 * MIPS_INSN16_SIZE:
/* No epilogue instructions in this category. */
return 0;
/* 32-bit instructions. */
case 2 * MIPS_INSN16_SIZE:
insn <<= 16;
@@ -7122,9 +7097,7 @@ mips_breakpoint_from_pc (struct gdbarch *gdbarch,
int size;
insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err);
size = (err != 0
? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2
? 2 : 4));
size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn);
*pcptr = unmake_compact_addr (pc);
*lenptr = size;
return (size == 2) ? micromips16_big_breakpoint
@@ -7174,9 +7147,7 @@ mips_breakpoint_from_pc (struct gdbarch *gdbarch,
int size;
insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err);
size = (err != 0
? 2 : (mips_insn_size (ISA_MICROMIPS, insn) == 2
? 2 : 4));
size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn);
*pcptr = unmake_compact_addr (pc);
*lenptr = size;
return (size == 2) ? micromips16_little_breakpoint