forked from Imagelibrary/binutils-gdb
* Removed short_hand field from opcode table and
refactored assembler/disassember accordingly.
Testsuite checkout OK.
This commit is contained in:
Sean Keys
@@ -1,3 +1,9 @@
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2013-10-10 Sean Keys <skeys@ipdatasys.com>
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* xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
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table.
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* xgate-dis.c (print_insn): Refactor to work with table change.
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2013-10-10 Roland McGrath <mcgrathr@google.com>
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* i386-dis.c (oappend_maybe_intel): New function.
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@@ -124,83 +124,69 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info)
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(*info->fprintf_func)(info->stream, "%s", decodePTR->opcodePTR->name);
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/* First we compare the shorthand format of the constraints. If we
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still are unable to pinpoint the operands
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we analyze the opcodes constraint string. */
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switch (decodePTR->opcodePTR->sh_format)
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{
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case XG_R_C:
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(*info->fprintf_func)(info->stream, " R%x, CCR",
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(raw_code >> 8) & 0x7);
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break;
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case XG_C_R:
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(*info->fprintf_func)(info->stream, " CCR, R%x",
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(raw_code >> 8) & 0x7);
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break;
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case XG_R_P:
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(*info->fprintf_func)(info->stream, " R%x, PC",
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(raw_code >> 8) & 0x7);
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break;
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case XG_INH:
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break;
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case XG_R_R_R:
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if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_TRI))
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{
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(*info->fprintf_func)(info->stream, " R%x, R%x, R%x",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IDR))
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{
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if (raw_code & 0x01)
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x+)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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else if (raw_code & 0x02)
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, -R%x)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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else
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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}
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else
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{
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(*info->fprintf_func)(info->stream, " unhandled mode %s",
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decodePTR->opcodePTR->constraints);
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}
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break;
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case XG_R_R:
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if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_DYA))
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{
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operandOne = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
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operandTwo = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
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(*info->fprintf_func)(info->stream, " R%x, R%x", operandOne,
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operandTwo);
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}
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else
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{
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(*info->fprintf_func)(info->stream, " unhandled mode %s",
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opcodePTR->constraints);
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}
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break;
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case XG_R_R_I:
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(*info->fprintf_func)(info->stream, " R%x, (R%x, #0x%x)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7, raw_code & 0x1f);
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break;
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case XG_R:
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operandOne = ripBits (&operMaskReg, 3, decodePTR->opcodePTR,
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raw_code);
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(*info->fprintf_func)(info->stream, " R%x", operandOne);
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break;
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case XG_I | XG_PCREL:
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if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_REL9))
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still are unable to pinpoint the operands
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we analyze the opcodes constraint string. */
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if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON_R_C))
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{
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(*info->fprintf_func)(info->stream, " R%x, CCR",
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(raw_code >> 8) & 0x7);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON_C_R))
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{
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(*info->fprintf_func)(info->stream, " CCR, R%x",
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(raw_code >> 8) & 0x7);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON_R_P))
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{
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(*info->fprintf_func)(info->stream, " R%x, PC",
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(raw_code >> 8) & 0x7);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_TRI))
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{
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(*info->fprintf_func)(info->stream, " R%x, R%x, R%x",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IDR))
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{
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if (raw_code & 0x01)
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x+)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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else if (raw_code & 0x02)
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, -R%x)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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else
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, R%x)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7,
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(raw_code >> 2) & 0x7);
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}
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_DYA))
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{
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operandOne = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
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operandTwo = ripBits (&operMaskReg, 3, opcodePTR, raw_code);
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( *info->fprintf_func)(info->stream, " R%x, R%x", operandOne,
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operandTwo);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IDO5))
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{
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(*info->fprintf_func)(info->stream, " R%x, (R%x, #0x%x)",
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(raw_code >> 8) & 0x7, (raw_code >> 5) & 0x7, raw_code & 0x1f);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_MON))
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{
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operandOne = ripBits (&operMaskReg, 3, decodePTR->opcodePTR,
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raw_code);
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(*info->fprintf_func)(info->stream, " R%x", operandOne);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_REL9))
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{
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/* If address is negative handle it accordingly. */
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if (raw_code & XGATE_NINE_SIGNBIT)
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@@ -215,10 +201,10 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info)
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relAddr = raw_code & 0xff;
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relAddr = (relAddr << 1) + 2;
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}
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(*info->fprintf_func)(info->stream, " *%d", relAddr);
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(*info->fprintf_func)(info->stream, " Abs* 0x");
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(*info->print_address_func)(memaddr + relAddr, info);
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}
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(*info->fprintf_func)(info->stream, " *%d", relAddr);
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(*info->fprintf_func)(info->stream, " Abs* 0x");
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(*info->print_address_func)(memaddr + relAddr, info);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_REL10))
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{
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/* If address is negative handle it accordingly. */
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@@ -238,54 +224,44 @@ print_insn (bfd_vma memaddr, struct disassemble_info* info)
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(*info->fprintf_func)(info->stream, " Abs* 0x");
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(*info->print_address_func)(memaddr + relAddr, info);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM4))
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{
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(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
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(raw_code >> 8) & 0x7, (raw_code >> 4) & 0xF);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM8))
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{
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if (macro_search (decodePTR->opcodePTR->name, previousOpName) &&
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previousOpName[0])
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{
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absAddress = (0xFF & raw_code) << 8;
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absAddress |= perviousBin & 0xFF;
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(*info->fprintf_func)(info->stream, " R%x, #0x%02x Abs* 0x",
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(raw_code >> 8) & 0x7, raw_code & 0xff);
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(*info->print_address_func)(absAddress, info);
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previousOpName[0] = 0;
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}
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else
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{
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strcpy (previousOpName, decodePTR->opcodePTR->name);
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(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
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(raw_code >> 8) & 0x7, raw_code & 0xff);
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}
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM3))
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{
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(*info->fprintf_func)(info->stream, " #0x%x",
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(raw_code >> 8) & 0x7);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_INH))
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{
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//
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}
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else
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{
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(*info->fprintf_func)(info->stream,
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" Can't disassemble for mode) %s",
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decodePTR->opcodePTR->constraints);
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(*info->fprintf_func)(info->stream, " unhandled mode %s",
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opcodePTR->constraints);
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}
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break;
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case XG_R_I:
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if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM4))
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{
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(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
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(raw_code >> 8) & 0x7, (raw_code >> 4) & 0xF);
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}
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else if (!strcmp (decodePTR->opcodePTR->constraints, XGATE_OP_IMM8))
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{
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if (macro_search (decodePTR->opcodePTR->name, previousOpName) &&
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previousOpName[0])
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{
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absAddress = (0xFF & raw_code) << 8;
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absAddress |= perviousBin & 0xFF;
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(*info->fprintf_func)(info->stream, " R%x, #0x%02x Abs* 0x",
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(raw_code >> 8) & 0x7, raw_code & 0xff);
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(*info->print_address_func)(absAddress, info);
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previousOpName[0] = 0;
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}
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else
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{
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strcpy (previousOpName, decodePTR->opcodePTR->name);
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(*info->fprintf_func)(info->stream, " R%x, #0x%02x",
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(raw_code >> 8) & 0x7, raw_code & 0xff);
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}
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}
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else
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{
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(*info->fprintf_func)(info->stream,
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" Can't disassemble for mode %s",
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decodePTR->opcodePTR->constraints);
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}
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break;
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case XG_I:
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(*info->fprintf_func)(info->stream, " #0x%x",
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(raw_code >> 8) & 0x7);
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break;
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default:
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(*info->fprintf_func)(info->stream, "address mode not found\t %x",
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opcodePTR->bin_opcode);
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break;
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}
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perviousBin = raw_code;
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}
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else
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@@ -86,7 +86,7 @@
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#define OP_IDO5 XGATE_OP_IDO5
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#define OP_REL9 XGATE_OP_REL9
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#define OP_REL10 XGATE_OP_REL10
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#define OP_DM XGATE_OP_DYA_MON
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#define OP_DM XGATE_OP_DYA_MON
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/* macro operand modes */
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#define OP_mADD XGATE_OP_IMM16mADD
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#define OP_mAND XGATE_OP_IMM16mAND
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@@ -95,110 +95,109 @@
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#define OP_mSUB XGATE_OP_IMM16mSUB
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#define ALL XGATE_V1|XGATE_V2|XGATE_V3
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#define XG_IP XG_I|XG_PCREL
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const struct xgate_opcode xgate_opcodes[] = {
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/* Name -+ +-- CPU
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Constraints --+ +------------ CCR changes
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Format ----------------+ +---------------- Max # cycles
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Short Hand Format-------------------------+ +------------------- Min # cycles
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Size -----------------------------------------------+ +-------------------------- Opcode */
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{ "adc", OP_TRI, "00011rrrrrrrrr11", XG_R_R_R, 2, 0x1803, 1, 1, CHG_NZVC, ALL},
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{ "add", OP_TRI, "00011rrrrrrrrr10", XG_R_R_R, 2, 0x1802, 1, 1, CHG_NZVC, ALL},
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{ "addh", OP_IMM8, "11101rrriiiiiiii", XG_R_I, 2, 0xE800, 1, 1, CHG_NZVC, ALL},
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{ "addl", OP_IMM8, "11100rrriiiiiiii", XG_R_I, 2, 0xE000, 1, 1, CHG_NZVC, ALL},
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{ "and", OP_TRI, "00010rrrrrrrrr00", XG_R_R_R, 2, 0x1000, 1, 1, CHG_NZV, ALL},
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{ "andh", OP_IMM8, "10001rrriiiiiiii", XG_R_I, 2, 0x8800, 1, 1, CHG_NZV, ALL},
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{ "andl", OP_IMM8, "10000rrriiiiiiii", XG_R_I, 2, 0x8000, 1, 1, CHG_NZV, ALL},
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{ "asr", OP_IMM4, "00001rrriiii1001", XG_R_I, 2, 0x0809, 1, 1, CHG_NZVC, ALL},
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{ "asr", OP_DYA, "00001rrrrrr10001", XG_R_R, 2, 0x0811, 1, 1, CHG_NZVC, ALL},
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{ "bcc", OP_REL9, "0010000iiiiiiiii", XG_IP, 2, 0x2000, 1, 2, CHG_NONE, ALL},
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{ "bcs", OP_REL9, "0010001iiiiiiiii", XG_IP, 2, 0x2200, 1, 2, CHG_NONE, ALL},
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{ "beq", OP_REL9, "0010011iiiiiiiii", XG_IP, 2, 0x2600, 1, 2, CHG_NONE, ALL},
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{ "bfext", OP_TRI, "01100rrrrrrrrr11", XG_R_R_R, 2, 0x6003, 1, 1, CHG_NZV, ALL},
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{ "bffo", OP_DYA, "00001rrrrrr10000", XG_R_R, 2, 0x0810, 1, 1, CHG_NZVC, ALL},
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{ "bfins", OP_TRI, "01101rrrrrrrrr11", XG_R_R_R, 2, 0x6803, 1, 1, CHG_NZV, ALL},
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{"bfinsi", OP_TRI, "01110rrrrrrrrr11", XG_R_R_R, 2, 0x7003, 1, 1, CHG_NZV, ALL},
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{"bfinsx", OP_TRI, "01111rrrrrrrrr11", XG_R_R_R, 2, 0x7803, 1, 1, CHG_NZV, ALL},
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{ "bge", OP_REL9, "0011010iiiiiiiii", XG_IP, 2, 0x3400, 1, 2, CHG_NONE, ALL},
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{ "bgt", OP_REL9, "0011100iiiiiiiii", XG_IP, 2, 0x3800, 1, 2, CHG_NONE, ALL},
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{ "bhi", OP_REL9, "0011000iiiiiiiii", XG_IP, 2, 0x3000, 1, 2, CHG_NONE, ALL},
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{ "bith", OP_IMM8, "10011rrriiiiiiii", XG_R_I, 2, 0x9800, 1, 1, CHG_NZV, ALL},
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{ "bitl", OP_IMM8, "10010rrriiiiiiii", XG_R_I, 2, 0x9000, 1, 1, CHG_NZV, ALL},
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{ "ble", OP_REL9, "0011101iiiiiiiii", XG_IP, 2, 0x3A00, 1, 2, CHG_NONE, ALL},
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{ "bls", OP_REL9, "0011001iiiiiiiii", XG_IP, 2, 0x3200, 1, 2, CHG_NONE, ALL},
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{ "blt", OP_REL9, "0011011iiiiiiiii", XG_IP, 2, 0x3600, 1, 2, CHG_NONE, ALL},
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{ "bmi", OP_REL9, "0010101iiiiiiiii", XG_IP, 2, 0x2A00, 1, 2, CHG_NONE, ALL},
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{ "bne", OP_REL9, "0010010iiiiiiiii", XG_IP, 2, 0x2400, 1, 2, CHG_NONE, ALL},
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{ "bpl", OP_REL9, "0010100iiiiiiiii", XG_IP, 2, 0x2800, 1, 2, CHG_NONE, ALL},
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{ "bra", OP_REL10, "001111iiiiiiiiii", XG_IP, 2, 0x3C00, 2, 2, CHG_NONE, ALL},
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{ "brk", OP_INH, "0000000000000000", XG_INH, 2, 0x0000, 1, 1, CHG_NONE, ALL},
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{ "bvc", OP_REL9, "0010110iiiiiiiii", XG_IP, 2, 0x2C00, 1, 2, CHG_NONE, ALL},
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{ "bvs", OP_REL9, "0010111iiiiiiiii", XG_IP, 2, 0x2E00, 1, 2, CHG_NONE, ALL},
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{ "cmpl", OP_IMM8, "11010rrriiiiiiii", XG_R_I, 2, 0xD000, 1, 1, CHG_NZVC, ALL},
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{ "cpch", OP_IMM8, "11011rrriiiiiiii", XG_R_I, 2, 0xD800, 1, 1, CHG_NZVC, ALL},
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{ "csem", OP_IMM3, "00000iii11110000", XG_I , 2, 0x00F0, 1, 1, CHG_NONE, ALL},
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{ "csem", OP_MON, "00000rrr11110001", XG_R, 2, 0x00F1, 1, 1, CHG_NONE, ALL},
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{ "csl", OP_IMM4, "00001rrriiii1010", XG_R_I, 2, 0x080A, 1, 1, CHG_NZVC, ALL},
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{ "csl", OP_DYA, "00001rrrrrr10010", XG_R_R, 2, 0x0812, 1, 1, CHG_NZVC, ALL},
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{ "csr", OP_IMM4, "00001rrriiii1011", XG_R_I, 2, 0x080B, 1, 1, CHG_NZVC, ALL},
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{ "csr", OP_DYA, "00001rrrrrr10011", XG_R_R, 2, 0x0813, 1, 1, CHG_NZVC, ALL},
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{ "jal", OP_MON, "00000rrr11110110", XG_R, 2, 0x00F6, 2, 2, CHG_NONE, ALL},
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{ "ldb", OP_IDO5, "01000rrrrrriiiii", XG_R_R_I, 2, 0x4000, 2, 2, CHG_NONE, ALL},
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{ "ldb", OP_IDR, "01100rrrrrrrrrrr", XG_R_R_R, 2, 0x6000, 2, 2, CHG_NONE, ALL},
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{ "ldh", OP_IMM8, "11111rrriiiiiiii", XG_R_I, 2, 0xF800, 1, 1, CHG_NONE, ALL},
|
||||
{ "ldl", OP_IMM8, "11110rrriiiiiiii", XG_R_I, 2, 0xF000, 1, 1, CHG_NONE, ALL},
|
||||
{ "ldw", OP_IDO5, "01001rrrrrriiiii", XG_R_R_I, 2, 0x4800, 2, 2, CHG_NONE, ALL},
|
||||
{ "ldw", OP_IDR, "01101rrrrrrrrrrr", XG_R_R_R, 2, 0x6800, 2, 2, CHG_NONE, ALL},
|
||||
{ "lsl", OP_IMM4, "00001rrriiii1100", XG_R_I, 2, 0x080C, 1, 1, CHG_NZVC, ALL},
|
||||
{ "lsl", OP_DYA, "00001rrrrrr10100", XG_R_R, 2, 0x0814, 1, 1, CHG_NZVC, ALL},
|
||||
{ "lsr", OP_IMM4, "00001rrriiii1101", XG_R_I, 2, 0x080D, 1, 1, CHG_NZVC, ALL},
|
||||
{ "lsr", OP_DYA, "00001rrrrrr10101", XG_R_R, 2, 0x0815, 1, 1, CHG_NZVC, ALL},
|
||||
{ "nop", OP_INH, "0000000100000000", XG_INH, 2, 0x0100, 1, 1, CHG_NONE, ALL},
|
||||
{ "or", OP_TRI, "00010rrrrrrrrr10", XG_R_R_R, 2, 0x1002, 1, 1, CHG_NZV, ALL},
|
||||
{ "orh", OP_IMM8, "10101rrriiiiiiii", XG_R_I, 2, 0xA800, 1, 1, CHG_NZV, ALL},
|
||||
{ "orl", OP_IMM8, "10100rrriiiiiiii", XG_R_I, 2, 0xA000, 1, 1, CHG_NZV, ALL},
|
||||
{ "par", OP_MON, "00000rrr11110101", XG_R, 2, 0x00F5, 1, 1, CHG_NZV, ALL},
|
||||
{ "rol", OP_IMM4, "00001rrriiii1110", XG_R_I, 2, 0x080E, 1, 1, CHG_NZV, ALL},
|
||||
{ "rol", OP_DYA, "00001rrrrrr10110", XG_R_R, 2, 0x0816, 1, 1, CHG_NZV, ALL},
|
||||
{ "ror", OP_IMM4, "00001rrriiii1111", XG_R_I, 2, 0x080F, 1, 1, CHG_NZV, ALL},
|
||||
{ "ror", OP_DYA, "00001rrrrrr10111", XG_R_R, 2, 0x0817, 1, 1, CHG_NZV, ALL},
|
||||
{ "rts", OP_INH, "0000001000000000", XG_INH, 2, 0x0200, 2, 2, CHG_NONE, ALL},
|
||||
{ "sbc", OP_TRI, "00011rrrrrrrrr01", XG_R_R_R, 2, 0x1801, 1, 1, CHG_NZV, ALL},
|
||||
{ "ssem", OP_IMM3, "00000iii11110010", XG_I , 2, 0x00F2, 2, 2, CHG_C, ALL},
|
||||
{ "ssem", OP_MON, "00000rrr11110011", XG_R, 2, 0x00F3, 2, 2, CHG_C, ALL},
|
||||
{ "sex", OP_MON, "00000rrr11110100", XG_R, 2, 0x00F4, 1, 1, CHG_NZV, ALL},
|
||||
{ "sif", OP_INH, "0000001100000000", XG_INH, 2, 0x0300, 2, 2, CHG_NONE, ALL},
|
||||
{ "sif", OP_MON, "00000rrr11110111", XG_R, 2, 0x00F7, 2, 2, CHG_NONE, ALL},
|
||||
{ "stb", OP_IDO5, "01010rrrrrriiiii", XG_R_R_I, 2, 0x5000, 2, 2, CHG_NONE, ALL},
|
||||
{ "stb", OP_IDR, "01110rrrrrrrrrrr", XG_R_R_R, 2, 0x7000, 2, 2, CHG_NONE, ALL},
|
||||
{ "stw", OP_IDO5, "01011rrrrrriiiii", XG_R_R_I, 2, 0x5800, 2, 2, CHG_NONE, ALL},
|
||||
{ "stw", OP_IDR, "01111rrrrrrrrrrr", XG_R_R_R, 2, 0x7800, 2, 2, CHG_NONE, ALL},
|
||||
{ "sub", OP_TRI, "00011rrrrrrrrr00", XG_R_R_R, 2, 0x1800, 1, 1, CHG_NZVC, ALL},
|
||||
{ "subh", OP_IMM8, "11001rrriiiiiiii", XG_R_I, 2, 0xC800, 1, 1, CHG_NZVC, ALL},
|
||||
{ "subl", OP_IMM8, "11000rrriiiiiiii", XG_R_I, 2, 0xC000, 1, 1, CHG_NZVC, ALL},
|
||||
{ "tfr", OP_MON_R_C, "00000rrr11111000",XG_R_C, 2, 0x00F8, 1, 1, CHG_NONE, ALL},
|
||||
{ "tfr", OP_MON_C_R, "00000rrr11111001",XG_C_R, 2, 0x00F9, 1, 1, CHG_NONE, ALL},
|
||||
{ "tfr", OP_MON_R_P, "00000rrr11111010",XG_R_P, 2, 0x00FA, 1, 1, CHG_NONE, ALL},
|
||||
{ "xnor", OP_TRI, "00010rrrrrrrrr11", XG_R_R_R, 2, 0x1003, 1, 1, CHG_NZV, ALL},
|
||||
{ "xnorh", OP_IMM8, "10111rrriiiiiiii", XG_R_I, 2, 0xB800, 1, 1, CHG_NZV, ALL},
|
||||
{ "xnorl", OP_IMM8, "10110rrriiiiiiii", XG_R_I, 2, 0xB000, 1, 1, CHG_NZV, ALL},
|
||||
/* Name -+ +--- CPU
|
||||
Constraints --+ +----------- CCR changes
|
||||
Format -------+ +---------------- Max # cycles
|
||||
+------------------- Min # cycles
|
||||
Size -------------------------------------+ +-------------------------- Opcode */
|
||||
{ "adc", OP_TRI, "00011rrrrrrrrr11", 2, 0x1803, 1, 1, CHG_NZVC, ALL},
|
||||
{ "add", OP_TRI, "00011rrrrrrrrr10", 2, 0x1802, 1, 1, CHG_NZVC, ALL},
|
||||
{ "addh", OP_IMM8, "11101rrriiiiiiii", 2, 0xE800, 1, 1, CHG_NZVC, ALL},
|
||||
{ "addl", OP_IMM8, "11100rrriiiiiiii", 2, 0xE000, 1, 1, CHG_NZVC, ALL},
|
||||
{ "and", OP_TRI, "00010rrrrrrrrr00", 2, 0x1000, 1, 1, CHG_NZV, ALL},
|
||||
{ "andh", OP_IMM8, "10001rrriiiiiiii", 2, 0x8800, 1, 1, CHG_NZV, ALL},
|
||||
{ "andl", OP_IMM8, "10000rrriiiiiiii", 2, 0x8000, 1, 1, CHG_NZV, ALL},
|
||||
{ "asr", OP_IMM4, "00001rrriiii1001", 2, 0x0809, 1, 1, CHG_NZVC, ALL},
|
||||
{ "asr", OP_DYA, "00001rrrrrr10001", 2, 0x0811, 1, 1, CHG_NZVC, ALL},
|
||||
{ "bcc", OP_REL9, "0010000iiiiiiiii", 2, 0x2000, 1, 2, CHG_NONE, ALL},
|
||||
{ "bcs", OP_REL9, "0010001iiiiiiiii", 2, 0x2200, 1, 2, CHG_NONE, ALL},
|
||||
{ "beq", OP_REL9, "0010011iiiiiiiii", 2, 0x2600, 1, 2, CHG_NONE, ALL},
|
||||
{ "bfext", OP_TRI, "01100rrrrrrrrr11", 2, 0x6003, 1, 1, CHG_NZV, ALL},
|
||||
{ "bffo", OP_DYA, "00001rrrrrr10000", 2, 0x0810, 1, 1, CHG_NZVC, ALL},
|
||||
{ "bfins", OP_TRI, "01101rrrrrrrrr11", 2, 0x6803, 1, 1, CHG_NZV, ALL},
|
||||
{"bfinsi", OP_TRI, "01110rrrrrrrrr11", 2, 0x7003, 1, 1, CHG_NZV, ALL},
|
||||
{"bfinsx", OP_TRI, "01111rrrrrrrrr11", 2, 0x7803, 1, 1, CHG_NZV, ALL},
|
||||
{ "bge", OP_REL9, "0011010iiiiiiiii", 2, 0x3400, 1, 2, CHG_NONE, ALL},
|
||||
{ "bgt", OP_REL9, "0011100iiiiiiiii", 2, 0x3800, 1, 2, CHG_NONE, ALL},
|
||||
{ "bhi", OP_REL9, "0011000iiiiiiiii", 2, 0x3000, 1, 2, CHG_NONE, ALL},
|
||||
{ "bith", OP_IMM8, "10011rrriiiiiiii", 2, 0x9800, 1, 1, CHG_NZV, ALL},
|
||||
{ "bitl", OP_IMM8, "10010rrriiiiiiii", 2, 0x9000, 1, 1, CHG_NZV, ALL},
|
||||
{ "ble", OP_REL9, "0011101iiiiiiiii", 2, 0x3A00, 1, 2, CHG_NONE, ALL},
|
||||
{ "bls", OP_REL9, "0011001iiiiiiiii", 2, 0x3200, 1, 2, CHG_NONE, ALL},
|
||||
{ "blt", OP_REL9, "0011011iiiiiiiii", 2, 0x3600, 1, 2, CHG_NONE, ALL},
|
||||
{ "bmi", OP_REL9, "0010101iiiiiiiii", 2, 0x2A00, 1, 2, CHG_NONE, ALL},
|
||||
{ "bne", OP_REL9, "0010010iiiiiiiii", 2, 0x2400, 1, 2, CHG_NONE, ALL},
|
||||
{ "bpl", OP_REL9, "0010100iiiiiiiii", 2, 0x2800, 1, 2, CHG_NONE, ALL},
|
||||
{ "bra", OP_REL10, "001111iiiiiiiiii", 2, 0x3C00, 2, 2, CHG_NONE, ALL},
|
||||
{ "brk", OP_INH, "0000000000000000", 2, 0x0000, 1, 1, CHG_NONE, ALL},
|
||||
{ "bvc", OP_REL9, "0010110iiiiiiiii", 2, 0x2C00, 1, 2, CHG_NONE, ALL},
|
||||
{ "bvs", OP_REL9, "0010111iiiiiiiii", 2, 0x2E00, 1, 2, CHG_NONE, ALL},
|
||||
{ "cmpl", OP_IMM8, "11010rrriiiiiiii", 2, 0xD000, 1, 1, CHG_NZVC, ALL},
|
||||
{ "cpch", OP_IMM8, "11011rrriiiiiiii", 2, 0xD800, 1, 1, CHG_NZVC, ALL},
|
||||
{ "csem", OP_IMM3, "00000iii11110000", 2, 0x00F0, 1, 1, CHG_NONE, ALL},
|
||||
{ "csem", OP_MON, "00000rrr11110001", 2, 0x00F1, 1, 1, CHG_NONE, ALL},
|
||||
{ "csl", OP_IMM4, "00001rrriiii1010", 2, 0x080A, 1, 1, CHG_NZVC, ALL},
|
||||
{ "csl", OP_DYA, "00001rrrrrr10010", 2, 0x0812, 1, 1, CHG_NZVC, ALL},
|
||||
{ "csr", OP_IMM4, "00001rrriiii1011", 2, 0x080B, 1, 1, CHG_NZVC, ALL},
|
||||
{ "csr", OP_DYA, "00001rrrrrr10011", 2, 0x0813, 1, 1, CHG_NZVC, ALL},
|
||||
{ "jal", OP_MON, "00000rrr11110110", 2, 0x00F6, 2, 2, CHG_NONE, ALL},
|
||||
{ "ldb", OP_IDO5, "01000rrrrrriiiii", 2, 0x4000, 2, 2, CHG_NONE, ALL},
|
||||
{ "ldb", OP_IDR, "01100rrrrrrrrrrr", 2, 0x6000, 2, 2, CHG_NONE, ALL},
|
||||
{ "ldh", OP_IMM8, "11111rrriiiiiiii", 2, 0xF800, 1, 1, CHG_NONE, ALL},
|
||||
{ "ldl", OP_IMM8, "11110rrriiiiiiii", 2, 0xF000, 1, 1, CHG_NONE, ALL},
|
||||
{ "ldw", OP_IDO5, "01001rrrrrriiiii", 2, 0x4800, 2, 2, CHG_NONE, ALL},
|
||||
{ "ldw", OP_IDR, "01101rrrrrrrrrrr", 2, 0x6800, 2, 2, CHG_NONE, ALL},
|
||||
{ "lsl", OP_IMM4, "00001rrriiii1100", 2, 0x080C, 1, 1, CHG_NZVC, ALL},
|
||||
{ "lsl", OP_DYA, "00001rrrrrr10100", 2, 0x0814, 1, 1, CHG_NZVC, ALL},
|
||||
{ "lsr", OP_IMM4, "00001rrriiii1101", 2, 0x080D, 1, 1, CHG_NZVC, ALL},
|
||||
{ "lsr", OP_DYA, "00001rrrrrr10101", 2, 0x0815, 1, 1, CHG_NZVC, ALL},
|
||||
{ "nop", OP_INH, "0000000100000000", 2, 0x0100, 1, 1, CHG_NONE, ALL},
|
||||
{ "or", OP_TRI, "00010rrrrrrrrr10", 2, 0x1002, 1, 1, CHG_NZV, ALL},
|
||||
{ "orh", OP_IMM8, "10101rrriiiiiiii", 2, 0xA800, 1, 1, CHG_NZV, ALL},
|
||||
{ "orl", OP_IMM8, "10100rrriiiiiiii", 2, 0xA000, 1, 1, CHG_NZV, ALL},
|
||||
{ "par", OP_MON, "00000rrr11110101", 2, 0x00F5, 1, 1, CHG_NZV, ALL},
|
||||
{ "rol", OP_IMM4, "00001rrriiii1110", 2, 0x080E, 1, 1, CHG_NZV, ALL},
|
||||
{ "rol", OP_DYA, "00001rrrrrr10110", 2, 0x0816, 1, 1, CHG_NZV, ALL},
|
||||
{ "ror", OP_IMM4, "00001rrriiii1111", 2, 0x080F, 1, 1, CHG_NZV, ALL},
|
||||
{ "ror", OP_DYA, "00001rrrrrr10111", 2, 0x0817, 1, 1, CHG_NZV, ALL},
|
||||
{ "rts", OP_INH, "0000001000000000", 2, 0x0200, 2, 2, CHG_NONE, ALL},
|
||||
{ "sbc", OP_TRI, "00011rrrrrrrrr01", 2, 0x1801, 1, 1, CHG_NZV, ALL},
|
||||
{ "ssem", OP_IMM3, "00000iii11110010", 2, 0x00F2, 2, 2, CHG_C, ALL},
|
||||
{ "ssem", OP_MON, "00000rrr11110011", 2, 0x00F3, 2, 2, CHG_C, ALL},
|
||||
{ "sex", OP_MON, "00000rrr11110100", 2, 0x00F4, 1, 1, CHG_NZV, ALL},
|
||||
{ "sif", OP_INH, "0000001100000000", 2, 0x0300, 2, 2, CHG_NONE, ALL},
|
||||
{ "sif", OP_MON, "00000rrr11110111", 2, 0x00F7, 2, 2, CHG_NONE, ALL},
|
||||
{ "stb", OP_IDO5, "01010rrrrrriiiii", 2, 0x5000, 2, 2, CHG_NONE, ALL},
|
||||
{ "stb", OP_IDR, "01110rrrrrrrrrrr", 2, 0x7000, 2, 2, CHG_NONE, ALL},
|
||||
{ "stw", OP_IDO5, "01011rrrrrriiiii", 2, 0x5800, 2, 2, CHG_NONE, ALL},
|
||||
{ "stw", OP_IDR, "01111rrrrrrrrrrr", 2, 0x7800, 2, 2, CHG_NONE, ALL},
|
||||
{ "sub", OP_TRI, "00011rrrrrrrrr00", 2, 0x1800, 1, 1, CHG_NZVC, ALL},
|
||||
{ "subh", OP_IMM8, "11001rrriiiiiiii", 2, 0xC800, 1, 1, CHG_NZVC, ALL},
|
||||
{ "subl", OP_IMM8, "11000rrriiiiiiii", 2, 0xC000, 1, 1, CHG_NZVC, ALL},
|
||||
{ "tfr", OP_MON_R_C, "00000rrr11111000", 2, 0x00F8, 1, 1, CHG_NONE, ALL},
|
||||
{ "tfr", OP_MON_C_R, "00000rrr11111001", 2, 0x00F9, 1, 1, CHG_NONE, ALL},
|
||||
{ "tfr", OP_MON_R_P, "00000rrr11111010", 2, 0x00FA, 1, 1, CHG_NONE, ALL},
|
||||
{ "xnor", OP_TRI, "00010rrrrrrrrr11", 2, 0x1003, 1, 1, CHG_NZV, ALL},
|
||||
{ "xnorh", OP_IMM8, "10111rrriiiiiiii", 2, 0xB800, 1, 1, CHG_NZV, ALL},
|
||||
{ "xnorl", OP_IMM8, "10110rrriiiiiiii", 2, 0xB000, 1, 1, CHG_NZV, ALL},
|
||||
/* macro and alias codes */
|
||||
{ "add", OP_mADD, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "and", OP_mAND, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "bhs", OP_REL9, "0010000iiiiiiiii", XG_IP, 2, 0x2000, 0, 0, CHG_NONE, ALL},
|
||||
{ "blo", OP_REL9, "0010001iiiiiiiii", XG_IP, 2, 0x2200, 0, 0, CHG_NONE, ALL},
|
||||
{ "cmp", OP_mCPC, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "cmp", OP_DYA, "00011sssrrrrrr00", XG_R_R, 2, 0x1800, 0, 0, CHG_NZVC, ALL},
|
||||
{ "com", OP_DM, "00010rrrsssrrr11", XG_R, 2, 0x1003, 0, 0, CHG_NZVC, ALL},
|
||||
{ "com", OP_DYA, "00010rrrsssrrr11", XG_R_R, 2, 0x1003, 0, 0, CHG_NZV, ALL},
|
||||
{ "cpc", OP_DYA, "00011sssrrrrrr01", XG_R_R, 2, 0x1801, 0, 0, CHG_NZVC, ALL},
|
||||
{ "ldd", OP_mLDW, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "ldw", OP_mLDW, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "mov", OP_DYA, "00010rrrsssrrr10", XG_R_R, 2, 0x1002, 0, 0, CHG_NZVC, ALL},
|
||||
{ "neg", OP_DYA, "00011rrrsssrrr00", XG_R_R, 2, 0x1800, 0, 0, CHG_NZVC, ALL},
|
||||
{ "sub", OP_mSUB, "----------------", XG_R_I, 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "tst", OP_MON, "00011sssrrrsss00", XG_R, 2, 0x1800, 0, 0, CHG_NZV, ALL}
|
||||
{ "add", OP_mADD, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "and", OP_mAND, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "bhs", OP_REL9, "0010000iiiiiiiii", 2, 0x2000, 0, 0, CHG_NONE, ALL},
|
||||
{ "blo", OP_REL9, "0010001iiiiiiiii", 2, 0x2200, 0, 0, CHG_NONE, ALL},
|
||||
{ "cmp", OP_mCPC, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "cmp", OP_DYA, "00011sssrrrrrr00", 2, 0x1800, 0, 0, CHG_NZVC, ALL},
|
||||
{ "com", OP_DM, "00010rrrsssrrr11", 2, 0x1003, 0, 0, CHG_NZVC, ALL},
|
||||
{ "com", OP_DYA, "00010rrrsssrrr11", 2, 0x1003, 0, 0, CHG_NZV, ALL},
|
||||
{ "cpc", OP_DYA, "00011sssrrrrrr01", 2, 0x1801, 0, 0, CHG_NZVC, ALL},
|
||||
{ "ldd", OP_mLDW, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "ldw", OP_mLDW, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "mov", OP_DYA, "00010rrrsssrrr10", 2, 0x1002, 0, 0, CHG_NZVC, ALL},
|
||||
{ "neg", OP_DYA, "00011rrrsssrrr00", 2, 0x1800, 0, 0, CHG_NZVC, ALL},
|
||||
{ "sub", OP_mSUB, "----------------", 4, 0, 0, 0, CHG_NONE, ALL},
|
||||
{ "tst", OP_MON, "00011sssrrrsss00", 2, 0x1800, 0, 0, CHG_NZV, ALL}
|
||||
};
|
||||
|
||||
const int xgate_num_opcodes = TABLE_SIZE (xgate_opcodes);
|
||||
|
||||
Reference in New Issue
Block a user