forked from Imagelibrary/binutils-gdb
sim: mips: Add simulator support for mips32r6/mips64r6
2022-02-01 Ali Lown <ali.lown@imgtec.com> Andrew Bennett <andrew.bennett@imgtec.com> Dragan Mladjenovic <dragan.mladjenovic@rt-rk.com> Faraz Shahbazker <fshahbazker@wavecomp.com> sim/common/ChangeLog: * sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21, EXTEND26): New macros. sim/mips/ChangeLog: * Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen. * configure: Regenerate. * configure.ac: Support mipsisa32r6 and mipsisa64r6. (sim_engine_run): Pick simulator model from processor specified in e_flags. * cp1.c (value_fpr): Handle fmt_dc32. (fp_unary, fp_binary): Zero initialize locals. (update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac, fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New functions. (sim_fpu_class_mips_mapping): New. * cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define. * interp.c (MIPSR6_P): New. (load_word): Allow unaligned memory access for MIPSR6. * micromips.igen (sc, scd): Adapt to new do_sc* helper signature. * mips.igen: Add *r6 models. (signal_if_cti, forbiddenslot32): New helpers. (delayslot32): Use signal_if_cti. (do_sc, do_scd); Add store_ll_bit parameter. (sc, scd): Adapt to previous change. (nal, beq, bal): New definitions for *r6. (sll): Split nop and ssnop cases into ... (nop, ssnop): New definitions. (loadstore_ea): Use the 32-bit compatibility adressing. (cache): Split logic into ... (do_cache): New helper. (check_fpu): Select IEEE 754-2008 mode for R6. (not_word_value, unpredictable, check_mt_hilo, check_mf_hilo, check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add, li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd, daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra, dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr, jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror, rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt, tltu, tne, xor, xori, check_fmt_p, do_load_double, do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT, cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1, dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT, mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT, sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f, bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp, tlbr, tlbwi, tlbwr): Enable on *r6 models. * mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu, dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr, wsbh): Likewise. * mips3264r6.igen: New file. * sim-main.h (FP_formats): Add fmt_dc32. (FORBIDDEN_SLOT): New macros. (simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines. (fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub): New declarations. (R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA, MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping previous declarations. sim/testsuite/mips/ChangeLog: * basic.exp: Add r6-*.s tests. (run_r6_removed_test): New function. (run_endian_tests): New function. * hilo-hazard-3.s: Skip for mips*r6. * r2-fpu.s: New test. * r6-64.s: New test. * r6-branch.s: New test. * r6-forbidden.s: New test. * r6-fpu.s: New test. * r6-llsc-dp.s: New test. * r6-llsc-wp.s: New test. * r6-removed.csv: New test. * r6-removed.s: New test. * r6.s: New test. * utils-r6.inc: New inc.
This commit is contained in:
Faraz Shahbazker
committed by
Mike Frysinger
Mike Frysinger
parent
fc3c199fac
commit
06c441ccef
@@ -26,6 +26,8 @@ mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ER
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#include "sim-basics.h"
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#include "sim-base.h"
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#include "bfd.h"
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#include "elf-bfd.h"
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#include "elf/mips.h"
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/* Deprecated macros and types for manipulating 64bit values. Use
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../common/sim-bits.h and ../common/sim-endian.h macros instead. */
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@@ -72,6 +74,9 @@ typedef enum {
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fmt_word = 4,
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fmt_long = 5,
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fmt_ps = 6,
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/* The following is a special case for FP conditions where only
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the lower 32bits are considered. This is a HACK. */
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fmt_dc32 = 7,
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/* The following are well outside the normal acceptable format
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range, and are used in the register status vector. */
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fmt_unknown = 0x10000000,
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@@ -261,6 +266,7 @@ struct _sim_cpu {
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#define DSPC ((CPU)->dspc)
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#define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
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#define FORBIDDEN_SLOT() { NIA = forbiddenslot32 (SD_); }
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#define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
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@@ -271,15 +277,16 @@ struct _sim_cpu {
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#define DSSTATE ((CPU)->dsstate)
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/* Flags in the "state" variable: */
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#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
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#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
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#define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
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#define simPCOC0 (1 << 17) /* COC[1] from current */
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#define simPCOC1 (1 << 18) /* COC[1] from previous */
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#define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
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#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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#define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
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#define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
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#define simTRACE (1 << 8) /* 1 = trace address activity */
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#define simPCOC0 (1 << 17) /* COC[1] from current */
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#define simPCOC1 (1 << 18) /* COC[1] from previous */
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#define simDELAYSLOT (1 << 24) /* 1 = delay slot entry exists */
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#define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
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#define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
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#define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
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#define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */
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#ifndef ENGINE_ISSUE_PREFIX_HOOK
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#define ENGINE_ISSUE_PREFIX_HOOK() \
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@@ -532,6 +539,10 @@ struct mips_sim_state {
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/* Bits reserved for implementations: */
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#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
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/* From R6 onwards, some instructions (e.g. ADDIUPC) change behaviour based
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* on the Status.UX bits to either sign extend, or act as full 64 bit. */
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#define status_optional_EXTEND32(x) ((SR & status_UX) ? x : EXTEND32(x))
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#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
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#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
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#define cause_CE_mask 0x30000000 /* Coprocessor exception */
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@@ -719,8 +730,55 @@ void test_fcsr (SIM_STATE);
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/* FPU operations. */
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void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, int abs, int cond, int cc);
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#define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
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/* Non-signalling */
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#define FP_R6CMP_AF 0x0
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#define FP_R6CMP_EQ 0x2
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#define FP_R6CMP_LE 0x6
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#define FP_R6CMP_LT 0x4
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#define FP_R6CMP_NE 0x13
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#define FP_R6CMP_OR 0x11
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#define FP_R6CMP_UEQ 0x3
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#define FP_R6CMP_ULE 0x7
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#define FP_R6CMP_ULT 0x5
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#define FP_R6CMP_UN 0x1
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#define FP_R6CMP_UNE 0x12
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/* Signalling */
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#define FP_R6CMP_SAF 0x8
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#define FP_R6CMP_SEQ 0xa
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#define FP_R6CMP_SLE 0xe
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#define FP_R6CMP_SLT 0xc
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#define FP_R6CMP_SNE 0x1b
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#define FP_R6CMP_SOR 0x19
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#define FP_R6CMP_SUEQ 0xb
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#define FP_R6CMP_SULE 0xf
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#define FP_R6CMP_SULT 0xd
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#define FP_R6CMP_SUN 0x9
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#define FP_R6CMP_SUNE 0x1a
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/* FPU Class */
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#define FP_R6CLASS_SNAN (1<<0)
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#define FP_R6CLASS_QNAN (1<<1)
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#define FP_R6CLASS_NEGINF (1<<2)
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#define FP_R6CLASS_NEGNORM (1<<3)
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#define FP_R6CLASS_NEGSUB (1<<4)
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#define FP_R6CLASS_NEGZERO (1<<5)
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#define FP_R6CLASS_POSINF (1<<6)
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#define FP_R6CLASS_POSNORM (1<<7)
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#define FP_R6CLASS_POSSUB (1<<8)
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#define FP_R6CLASS_POSZERO (1<<9)
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void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt,
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int abs, int cond, int cc);
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#define Compare(op1,op2,fmt,cond,cc) \
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fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
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uint64_t fp_r6_cmp (SIM_STATE, uint64_t op1, uint64_t op2,
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FP_formats fmt, int cond);
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#define R6Compare(op1,op2,fmt,cond) fp_r6_cmp(SIM_ARGS, op1, op2, fmt, cond)
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uint64_t fp_classify(SIM_STATE, uint64_t op, FP_formats fmt);
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#define Classify(op, fmt) fp_classify(SIM_ARGS, op, fmt)
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int fp_rint(SIM_STATE, uint64_t op, uint64_t *ans, FP_formats fmt);
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#define RoundToIntegralExact(op, ans, fmt) fp_rint(SIM_ARGS, op, ans, fmt)
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uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt);
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#define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
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uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt);
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@@ -733,6 +791,14 @@ uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
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#define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
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uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
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#define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
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uint64_t fp_min (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
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#define Min(op1,op2,fmt) fp_min(SIM_ARGS, op1, op2, fmt)
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uint64_t fp_max (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
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#define Max(op1,op2,fmt) fp_max(SIM_ARGS, op1, op2, fmt)
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uint64_t fp_mina (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
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#define MinA(op1,op2,fmt) fp_mina(SIM_ARGS, op1, op2, fmt)
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uint64_t fp_maxa (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt);
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#define MaxA(op1,op2,fmt) fp_maxa(SIM_ARGS, op1, op2, fmt)
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uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt);
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#define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
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uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt);
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@@ -741,6 +807,12 @@ uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt);
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#define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
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uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2,
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uint64_t op3, FP_formats fmt);
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#define FusedMultiplyAdd(op1,op2,op3,fmt) fp_fmadd(SIM_ARGS, op1, op2, op3, fmt)
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uint64_t fp_fmadd (SIM_STATE, uint64_t op1, uint64_t op2,
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uint64_t op3, FP_formats fmt);
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#define FusedMultiplySub(op1,op2,op3,fmt) fp_fmsub(SIM_ARGS, op1, op2, op3, fmt)
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uint64_t fp_fmsub (SIM_STATE, uint64_t op1, uint64_t op2,
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uint64_t op3, FP_formats fmt);
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#define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
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uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2,
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uint64_t op3, FP_formats fmt);
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