gdb: riscv: enable sim integration

Now the simulator can be loaded via gdb using "target sim".

gdb/ChangeLog

@@ -1,3 +1,7 @@
+2021-02-04  Mike Frysinger  <vapier@gentoo.org>
+
+	* configure.tgt (riscv*-*-*): Set gdb_sim.
+
 2021-02-04  Simon Marchi  <simon.marchi@polymtl.ca>
 
 	* target.c (target_is_non_stop_p): Return bool.

gdb/configure.tgt

@@ -554,6 +554,7 @@ riscv*-*-linux*)
 riscv*-*-*)
 	# Target: RISC-V architecture
 	gdb_target_obs=""
+	gdb_sim=../sim/riscv/libsim.a
 	;;
 
 rl78-*-elf)