forked from Imagelibrary/binutils-gdb
arc: Update opcode related include files for ARCv3.
Add new ARCv3 CPUs and required bits to decode/encode ARCv3 ISA opcodes. Fix 32 bit relocations which were set as signed but should be bitfield: ARC_32_ME, ARC_GLOB_DAT, ARC_JMP_SLOT, ARC_RELATIVE. Remove non-ABI relocation ARC_32_ME_S. include/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> Cupertino Miranda <cupertinomiranda@gmail.com> Bruno Mauricio <brunoasmauricio@gmail.com> * include/elf/arc-cpu.def: Add new HS5x and HS6x CPUs. * include/elf/arc-reloc.def: Add new ARC64 relocations. * include/elf/arc.h (EF_ARC_CPU_ARC64): New define. * include/opcode/arc-attrs.h (FEATURE_LIST_NAME): Update predicate. * include/opcode/arc-func.h: Update formating. (replace_disp8ls): New function. (replace_disp9s): Likewise. (replace_disp6s): Likewise. (replace_disp7s): Likewise. (replace_disp12s): Likewise. * include/opcode/arc.h (ARC_OPCODE_ARC64): New define. (ARC_OPCODE_ARC32): Likewise. (ARC_OPERAND_FP): Likewise. (HARD_FIELDF): Likewise. (ARC_OPCODE_ARCVx): New macro. (arc_flag_class): Update structure to hold new extract/insert functions for flags. (INSN3OP): Update macro. (FP_SIZE, TPOF, DPOF, SOPF, COPF, CONVOPS): New enums. Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
This commit is contained in:
Claudiu Zissulescu
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Claudiu Zissulescu
Claudiu Zissulescu
parent
4deb1ee57f
commit
04414221df
@@ -199,13 +199,19 @@ extern int arc_opcode_len (const struct arc_opcode *opcode);
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#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
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#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
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#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
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#define ARC_OPCODE_ARC64 0x0010 /* ARC64 specific insns. */
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#define ARC_OPCODE_ARC32 0x0020 /* ARC32 specific insns. */
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/* CPU combi. */
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#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
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| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS \
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| ARC_OPCODE_ARC64 | ARC_OPCODE_ARC32)
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#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
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#define ARC_OPCODE_ARCV1 (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
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#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
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#define ARC_OPCODE_ARCVx \
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(ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS | ARC_OPCODE_ARC64 \
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| ARC_OPCODE_ARC32)
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#define ARC_OPCODE_ARCMPY6E (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
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/* The operands table is an array of struct arc_operand. */
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@@ -325,6 +331,9 @@ extern const unsigned arc_NToperand;
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/* Mark the colon position. */
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#define ARC_OPERAND_COLON 0x4000
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/* Mark a floating point register. */
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#define ARC_OPERAND_FP 0x8000
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/* Mask for selecting the type for typecheck purposes. */
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#define ARC_OPERAND_TYPECHECK_MASK \
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(ARC_OPERAND_IR \
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@@ -369,6 +378,16 @@ struct arc_flag_class
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/* List of valid flags (codes). */
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unsigned flags[256];
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/* Some special cases needs to use insert/extract functions for
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flags as well. The function prototypes are identically like the
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one used for insertion/extraction of an operand. The reason
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beeing the ability of reusing these functions. */
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unsigned long long (*insert) (unsigned long long instruction,
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long long int op,
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const char **errmsg);
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long long int (*extract) (unsigned long long instruction,
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bool *invalid);
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};
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extern const struct arc_flag_class arc_flag_classes[];
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@@ -441,6 +460,8 @@ struct arc_pseudo_insn
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extern const struct arc_pseudo_insn arc_pseudo_insns[];
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extern const unsigned arc_num_pseudo_insn;
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extern const struct arc_pseudo_insn arc64_pseudo_insns[];
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extern const unsigned arc64_num_pseudo_insn;
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/* Structure for AUXILIARY registers. */
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struct arc_aux_reg
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@@ -478,8 +499,10 @@ extern const unsigned arc_num_relax_opcodes;
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#define FIELDC(word) ((word & 0x3F) << 6)
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#define FIELDF (0x01 << 15)
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#define FIELDQ (0x1F)
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#define HARD_FIELDF (0x00)
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#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
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#define INSN3OP(MOP,SOP) \
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(((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16) | HARD_FIELDF)
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#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
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#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
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@@ -667,6 +690,100 @@ typedef enum
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#define ARC_NUM_ADDRTYPES 16
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/*ARC64 floating point enums. */
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#define P_HALF 0
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#define P_SINGLE 1
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#define P_DOUBLE 2
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#define TOPF_FMADD 0
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#define TOPF_FMSUB 1
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#define TOPF_FNMADD 2
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#define TOPF_FNMSUB 3
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#define TOPF_VFMADD 4
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#define TOPF_VFMSUB 5
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#define TOPF_VFNMADD 6
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#define TOPF_VFNMSUB 7
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#define TOPF_VFMADDS 0xC
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#define TOPF_VFMSUBS 0xD
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#define TOPF_VFNMADDS 0xE
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#define TOPF_VFNMSUBS 0xF
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#define DOPF_FADD 0
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#define DOPF_FSUB 1
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#define DOPF_FMUL 2
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#define DOPF_FDIV 3
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#define DOPF_FCMP 4
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#define DOPF_FCMPF 5
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#define DOPF_FMIN 6
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#define DOPF_FMAX 7
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#define DOPF_FSGNJ 8
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#define DOPF_FSGNJN 10
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#define DOPF_FSGNJX 11
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#define DOPF_VFADD 0x10
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#define DOPF_VFSUB 0x11
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#define DOPF_VFMUL 0x12
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#define DOPF_VFDIV 0x13
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#define DOPF_VFADDS 0x14
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#define DOPF_VFSUBS 0x15
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#define DOPF_VFMULS 0x16
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#define DOPF_VFDIVS 0x17
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#define DOPF_VFUNPKL 0x18
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#define DOPF_VFUNPKM 0x19
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#define DOPF_VFPACKL 0x1a
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#define DOPF_VFPACKM 0x1b
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#define DOPF_VFBFLYL 0x1c
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#define DOPF_VFBFLYM 0x1d
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#define DOPF_VFADDSUB 0x1e
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#define DOPF_VFSUBADD 0x1f
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#define SOPF_FSQRT 0
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#define SOPF_VFSQRT 1
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#define SOPF_VFEXCH 2
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#define COPF_FMOV 0
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#define COPF_VFMOV 1
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#define FUINT2S 0
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#define FS2UINT 0
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#define FINT2S 0
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#define FS2INT 0
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#define FSRND 0
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#define F2UINT_RZ 0
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#define FSINT_RZ 0
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#define FSRND_RZ 0
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#define FMVI2S 0
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#define FMVS2I 0
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#define FS2H 0
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#define FH2S 0
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#define FS2H_RZ 0
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#define FUINT2D 1
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#define FS2UL 1
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#define FINT2D 1
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#define FS2L 1
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#define FS2D 1
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#define FS2UL_RZ 1
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#define FS2L_RZ 1
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#define FUL2S 2
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#define FD2UINT 2
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#define FL2S 2
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#define FD2INT 2
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#define FD2S 2
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#define FD2UINT_RZ 2
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#define FD2INT_RZ 2
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#define FUL2D 3
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#define FD2UL 3
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#define FL2D 3
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#define FD2L 3
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#define FDRND 3
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#define FD2UL_RZ 3
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#define FD2L_RZ 3
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#define FDRND_RZ 3
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#define FMVL2D 3
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#define FMVD2L 3
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#ifdef __cplusplus
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}
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#endif
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