forked from Imagelibrary/binutils-gdb
sim/erc32: Use fenv.h for host FPU access
This commit is contained in:
Jiri Gaisler
committed by
Mike Frysinger
Mike Frysinger
parent
20a0ffe33a
commit
0172ee3adc
@@ -1,3 +1,8 @@
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2015-02-21 Jiri Gaisler <jiri@gaisler.se>
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* float.c (get_accex, clear_accex, set_fsr): Use functions from fenv.h
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instead of custom assembly.
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2015-02-21 Jiri Gaisler <jiri@gaisler.se>
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* erc32.c (mec_read): Allow simulator memory size to be read
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@@ -28,53 +28,38 @@
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* 4. Clear host exception bits
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*
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*
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* This can also be done using ieee_flags() library routine on sun.
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*/
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#include "config.h"
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#include "sis.h"
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#include <fenv.h>
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/* Forward declarations */
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extern uint32 _get_sw (void);
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extern uint32 _get_cw (void);
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static void __setfpucw (unsigned short fpu_control);
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/* This host dependent routine should return the accrued exceptions */
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/* This routine should return the accrued exceptions */
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int
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get_accex()
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{
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#ifdef sparc
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return ((_get_fsr_raw() >> 5) & 0x1F);
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#elif i386
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uint32 accx;
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int fexc, accx;
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accx = _get_sw() & 0x3f;
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accx = ((accx & 1) << 4) | ((accx & 2) >> 1) | ((accx & 4) >> 1) |
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(accx & 8) | ((accx & 16) >> 2) | ((accx & 32) >> 5);
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fexc = fetestexcept (FE_ALL_EXCEPT);
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accx = 0;
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if (fexc & FE_INEXACT)
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accx |= 1;
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if (fexc & FE_DIVBYZERO)
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accx |= 2;
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if (fexc & FE_UNDERFLOW)
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accx |= 4;
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if (fexc & FE_OVERFLOW)
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accx |= 8;
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if (fexc & FE_INVALID)
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accx |= 0x10;
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return(accx);
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#else
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return(0);
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#warning no fpu trap support for this target
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#endif
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}
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/* How to clear the accrued exceptions */
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void
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clear_accex()
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{
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#ifdef sparc
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set_fsr((_get_fsr_raw() & ~0x3e0));
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#elif i386
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asm("\n"
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".text\n"
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" fnclex\n"
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"\n"
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" ");
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#else
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#warning no fpu trap support for this target
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#endif
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feclearexcept (FE_ALL_EXCEPT);
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}
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/* How to map SPARC FSR onto the host */
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@@ -82,138 +67,22 @@ void
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set_fsr(fsr)
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uint32 fsr;
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{
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#ifdef sparc
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_set_fsr_raw(fsr & ~0x0f800000);
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#elif i386
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void __setfpucw(unsigned short fpu_control);
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uint32 rawfsr;
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int fround;
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fsr >>= 30;
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switch (fsr) {
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fsr >>= 30;
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switch (fsr) {
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case 0:
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case 2:
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break;
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fround = FE_TONEAREST;
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break;
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case 1:
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fsr = 3;
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break;
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fround = FE_TOWARDZERO;
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break;
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case 2:
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fround = FE_UPWARD;
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break;
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case 3:
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fsr = 1;
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break;
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fround = FE_DOWNWARD;
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break;
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}
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rawfsr = _get_cw();
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rawfsr |= (fsr << 10) | 0x3ff;
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__setfpucw(rawfsr);
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#else
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#warning no fpu trap support for this target
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#endif
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fesetround (fround);
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}
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/* Host dependent support functions */
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#ifdef sparc
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asm("\n"
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"\n"
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".text\n"
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" .align 4\n"
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" .global __set_fsr_raw,_set_fsr_raw\n"
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"__set_fsr_raw:\n"
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"_set_fsr_raw:\n"
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" save %sp,-104,%sp\n"
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" st %i0,[%fp+68]\n"
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" ld [%fp+68], %fsr\n"
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" mov 0,%i0\n"
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" ret\n"
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" restore\n"
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"\n"
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" .align 4\n"
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" .global __get_fsr_raw\n"
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" .global _get_fsr_raw\n"
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"__get_fsr_raw:\n"
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"_get_fsr_raw:\n"
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" save %sp,-104,%sp\n"
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" st %fsr,[%fp+68]\n"
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" ld [%fp+68], %i0\n"
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" ret\n"
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" restore\n"
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"\n"
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" ");
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#elif i386
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asm("\n"
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"\n"
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".text\n"
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" .align 8\n"
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".globl _get_sw,__get_sw\n"
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"__get_sw:\n"
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"_get_sw:\n"
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" pushl %ebp\n"
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" movl %esp,%ebp\n"
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" movl $0,%eax\n"
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" fnstsw %ax\n"
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" movl %ebp,%esp\n"
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" popl %ebp\n"
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" ret\n"
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"\n"
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" .align 8\n"
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".globl _get_cw,__get_cw\n"
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"__get_cw:\n"
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"_get_cw:\n"
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" pushl %ebp\n"
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" movl %esp,%ebp\n"
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" subw $2,%esp\n"
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" fnstcw -2(%ebp)\n"
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" movw -2(%ebp),%eax\n"
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" movl %ebp,%esp\n"
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" popl %ebp\n"
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" ret\n"
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"\n"
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"\n"
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" ");
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#else
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#warning no fpu trap support for this target
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#endif
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#if i386
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/* #if defined _WIN32 || defined __GO32__ */
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/* This is so floating exception handling works on NT
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These definitions are from the linux fpu_control.h, which
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doesn't exist on NT.
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default to:
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- extended precision
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- rounding to nearest
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- exceptions on overflow, zero divide and NaN
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*/
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#define _FPU_DEFAULT 0x1372
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#define _FPU_RESERVED 0xF0C0 /* Reserved bits in cw */
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static void
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__setfpucw(unsigned short fpu_control)
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{
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volatile unsigned short cw;
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/* If user supplied _fpu_control, use it ! */
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if (!fpu_control)
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{
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/* use defaults */
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fpu_control = _FPU_DEFAULT;
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}
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/* Get Control Word */
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__asm__ volatile ("fnstcw %0" : "=m" (cw) : );
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/* mask in */
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cw &= _FPU_RESERVED;
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cw = cw | (fpu_control & ~_FPU_RESERVED);
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/* set cw */
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__asm__ volatile ("fldcw %0" :: "m" (cw));
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}
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/* #endif */
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#endif
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