388 lines
16 KiB
C
388 lines
16 KiB
C
/* miiLib.h - Media Independent Interface library header */
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/* Copyright 1990-2004 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01k,22apr04,kp added the macro MII_SR_SPEED_SEL_MASK
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01j,06aug03,slk added phyFlags option MII_PHY_ISO_UNAVAIL SPR# 90115
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01i,13may02,rcs added pPhyOptRegsRtn field to PHY_INFO. SPR# 76711
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01h,14jun01,rcs moved new registers used by GMII to new struc MII_G_REGS
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and placed it at end of PHY_INFO. (SPR# 68502)
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01g,23feb01,jln add basic GMII support for 1000-T auto-negotiation (SPR# 68502)
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01f,23nov99,cn added miiLibInit () to make miiLib a component (SPR #29542).
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01e,08nov99,cn added fields phyLinkDownRtn, pMiiPhyNode, miiPhyPresent
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to PHY_INFO structure. New flags MII_ALL_BUS_SCAN,
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MII_PHY_MONITOR, and macro MII_MONITOR_DELAY. Also
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added miiPhyUnInit (), miiLibUnInit ().
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01d,27sep99,cn added definition of MII_CR_DEF_0_MASK.
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01c,13sep99,cn added definition of MII_MAX_REG_NUM, moved global APIs
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from miiLib.c (SPR# 28305).
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01b,15jun99,cn changes after the code review.
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01a,16mar99,cn written from motFccEnd.h, 01b.
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*/
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/*
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DESCRIPTION
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This module implements a Media Independent Interface (MII) library.
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INCLUDE FILES:
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*/
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#ifndef __INCmiiLibh
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#define __INCmiiLibh
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/* includes */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define S_miiLib_PHY_LINK_DOWN (M_miiLib | 1)
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#define S_miiLib_PHY_NULL (M_miiLib | 2)
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#define S_miiLib_PHY_NO_ABLE (M_miiLib | 3)
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#define S_miiLib_PHY_AN_FAIL (M_miiLib | 4)
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/* defines */
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#define MII_SYS_DELAY(delay) \
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if (pPhyInfo->phyDelayRtn != NULL) \
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((* (pPhyInfo->phyDelayRtn)) (delay))
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#define MII_READ(addr, reg, val1, val2) \
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val2 = ((* (pPhyInfo->phyReadRtn)) ((pPhyInfo->pDrvCtrl), \
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(addr), (reg), (val1)));
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#define MII_WRITE(addr, reg, val1, val2) \
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val2 = ((* (pPhyInfo->phyWriteRtn)) ((pPhyInfo->pDrvCtrl), \
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(addr), (reg), (val1)));
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/* library flags */
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#define MII_PHY_FLAGS_SET(setBits) \
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(pPhyInfo->phyFlags |= (setBits))
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#define MII_PHY_FLAGS_ARE_SET(setBits) \
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(pPhyInfo->phyFlags & (setBits))
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#define MII_PHY_FLAGS_GET(setBits) \
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(pPhyInfo->phyFlags)
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#define MII_PHY_FLAGS_CLEAR(clearBits) \
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(pPhyInfo->phyFlags &= ~(clearBits))
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/* MII definitions */
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#define MII_CRC_LEN 0x4 /* CRC length in bytes */
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#define MII_ETH_MAX_PCK_SZ (ETHERMTU + SIZEOF_ETHERHEADER \
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+ MII_CRC_LEN)
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#define MII_MAX_PHY_NUM 0x20 /* max number of attached PHYs */
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#define MII_MAX_REG_NUM 0x20 /* max number of registers */
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#define MII_CTRL_REG 0x0 /* Control Register */
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#define MII_STAT_REG 0x1 /* Status Register */
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#define MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */
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#define MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */
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#define MII_AN_ADS_REG 0x4 /* Auto-Negotiation */
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/* Advertisement Register */
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#define MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */
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/* partner ability Register */
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#define MII_AN_EXP_REG 0x6 /* Auto-Negotiation */
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/* Expansion Register */
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#define MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */
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/* next-page transmit Register */
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#define MII_AN_PRTN_NEXT_REG 0x8 /* Link partner received next page */
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#define MII_MASSLA_CTRL_REG 0x9 /* MATER-SLAVE control register */
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#define MII_MASSLA_STAT_REG 0xa /* MATER-SLAVE status register */
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#define MII_EXT_STAT_REG 0xf /* Extented status register */
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/* MII control register bit */
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#define MII_CR_COLL_TEST 0x0080 /* collision test */
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#define MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */
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#define MII_CR_RESTART 0x0200 /* restart auto negotiation */
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#define MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */
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#define MII_CR_POWER_DOWN 0x0800 /* power down */
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#define MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */
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#define MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */
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#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
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#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
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#define MII_CR_NORM_EN 0x0000 /* just enable the PHY */
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#define MII_CR_DEF_0_MASK 0xca7f /* they must return zero */
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#define MII_CR_RES_MASK 0x003f /* reserved bits,return zero */
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/* MII Status register bit definitions */
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#define MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */
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#define MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */
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#define MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */
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#define MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */
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#define MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */
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#define MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */
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#define MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */
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#define MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */
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#define MII_SR_T4 0x8000 /* T4 capable */
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#define MII_SR_ABIL_MASK 0xff80 /* abilities mask */
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#define MII_SR_EXT_CAP 0x0001 /* extended capabilities */
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#define MII_SR_SPEED_SEL_MASK 0xf800 /* Mask to extract just speed
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* capabilities from status
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* register.
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*/
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/* MII ID2 register bit mask */
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#define MII_ID2_REVISON_MASK 0x000f
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#define MII_ID2_MODE_MASK 0x03f0
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/* MII AN advertisement Register bit definition */
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#define MII_ANAR_10TX_HD 0x0020
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#define MII_ANAR_10TX_FD 0x0040
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#define MII_ANAR_100TX_HD 0x0080
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#define MII_ANAR_100TX_FD 0x0100
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#define MII_ANAR_100T_4 0x0200
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#define MII_ANAR_PAUSE 0x0400
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#define MII_ANAR_ASM_PAUSE 0x0800
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#define MII_ANAR_REMORT_FAULT 0x2000
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#define MII_ANAR_NEXT_PAGE 0x8000
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#define MII_ANAR_PAUSE_MASK 0x0c00
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/* MII Link Code word bit definitions */
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#define MII_BP_FAULT 0x2000 /* remote fault */
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#define MII_BP_ACK 0x4000 /* acknowledge */
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#define MII_BP_NP 0x8000 /* nexp page is supported */
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/* MII Next Page bit definitions */
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#define MII_NP_TOGGLE 0x0800 /* toggle bit */
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#define MII_NP_ACK2 0x1000 /* acknowledge two */
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#define MII_NP_MSG 0x2000 /* message page */
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#define MII_NP_ACK1 0x4000 /* acknowledge one */
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#define MII_NP_NP 0x8000 /* nexp page will follow */
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/* MII Expansion Register bit definitions */
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#define MII_EXP_FAULT 0x0010 /* parallel detection fault */
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#define MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */
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#define MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */
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#define MII_EXP_PR 0x0002 /* full page received */
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#define MII_EXP_PRT_AN 0x0001 /* link partner auto negotiation able */
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/* MII Master-Slave Control register bit definition */
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#define MII_MASSLA_CTRL_1000T_HD 0x100
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#define MII_MASSLA_CTRL_1000T_FD 0x200
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#define MII_MASSLA_CTRL_PORT_TYPE 0x400
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#define MII_MASSLA_CTRL_CONFIG_VAL 0x800
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#define MII_MASSLA_CTRL_CONFIG_EN 0x1000
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/* MII Master-Slave Status register bit definition */
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#define MII_MASSLA_STAT_LP1000T_HD 0x400
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#define MII_MASSLA_STAT_LP1000T_FD 0x800
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#define MII_MASSLA_STAT_REMOTE_RCV 0x1000
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#define MII_MASSLA_STAT_LOCAL_RCV 0x2000
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#define MII_MASSLA_STAT_CONF_RES 0x4000
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#define MII_MASSLA_STAT_CONF_FAULT 0x8000
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/* MII Extented Status register bit definition */
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#define MII_EXT_STAT_1000T_HD 0x1000
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#define MII_EXT_STAT_1000T_FD 0x2000
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#define MII_EXT_STAT_1000X_HD 0x4000
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#define MII_EXT_STAT_1000X_FD 0x8000
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/* technology ability field bit definitions */
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#define MII_TECH_10BASE_T 0x0020 /* 10Base-T */
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#define MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */
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#define MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */
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#define MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */
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#define MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */
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#define MII_TECH_PAUSE 0x0400 /* PAUSE */
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#define MII_TECH_ASM_PAUSE 0x0800 /* Asym pause */
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#define MII_TECH_PAUSE_MASK 0x0c00
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#define MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */
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#define MII_TECH_MASK MII_ADS_TECH_MASK
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#define MII_ADS_SEL_MASK 0x001f /* selector field mask */
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#define MII_AN_FAIL 0x10 /* auto-negotiation fail */
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#define MII_STAT_FAIL 0x20 /* errors in the status register */
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#define MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */
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/* MII management frame structure */
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#define MII_MF_PREAMBLE 0xffffffff /* preamble pattern */
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#define MII_MF_ST 0x1 /* start of frame pattern */
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#define MII_MF_OP_RD 0x2 /* read operation pattern */
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#define MII_MF_OP_WR 0x1 /* write operation pattern */
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#define MII_MF_PREAMBLE_LEN 0x20 /* preamble lenght in bit */
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#define MII_MF_ST_LEN 0x2 /* start frame lenght in bit */
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#define MII_MF_OP_LEN 0x2 /* op code lenght in bit */
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#define MII_MF_ADDR_LEN 0x5 /* PHY addr lenght in bit */
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#define MII_MF_REG_LEN 0x5 /* PHY reg lenght in bit */
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#define MII_MF_TA_LEN 0x2 /* turnaround lenght in bit */
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#define MII_MF_DATA_LEN 0x10 /* data lenght in bit */
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/* defines related to the PHY device */
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#define MII_PHY_PRE_INIT 0x0001 /* PHY info pre-initialized */
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#define MII_PHY_AUTO 0x0010 /* auto-negotiation allowed */
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#define MII_PHY_TBL 0x0020 /* use negotiation table */
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#define MII_PHY_100 0x0040 /* PHY may use 100Mbit speed */
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#define MII_PHY_10 0x0080 /* PHY may use 10Mbit speed */
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#define MII_PHY_FD 0x0100 /* PHY may use full duplex */
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#define MII_PHY_HD 0x0200 /* PHY may use half duplex */
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#define MII_PHY_ISO 0x0400 /* isolate all PHYs */
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#define MII_PHY_PWR_DOWN 0x0800 /* power down mode */
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#define MII_PHY_DEF_SET 0x1000 /* set a default mode */
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#define MII_ALL_BUS_SCAN 0x2000 /* scan the all bus */
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#define MII_PHY_MONITOR 0x4000 /* monitor the PHY's status */
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#define MII_PHY_INIT 0x8000 /* PHY info initialized */
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#define MII_PHY_1000T_FD 0x10000 /* PHY may use 1000-T full duplex */
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#define MII_PHY_1000T_HD 0x20000 /* PHY mau use 1000-T half duplex */
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#define MII_PHY_TX_FLOW_CTRL 0x40000 /* Transmit flow control */
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#define MII_PHY_RX_FLOW_CTRL 0x80000 /* Receive flow control */
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#define MII_PHY_GMII_TYPE 0x100000 /* GMII = 1, MII = 0 */
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#define MII_PHY_ISO_UNAVAIL 0x200000 /* ctrl reg isolate func not available */
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/* miscellaneous defines */
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#define MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
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#define MII_PHY_NO_DELAY 0x0 /* do not delay */
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#define MII_PHY_NULL 0xff /* PHY is not present */
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#define MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
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#ifndef MII_MONITOR_DELAY
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# define MII_MONITOR_DELAY 0x5 /* in seconds */
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#endif
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#define MII_PHY_LINK_UNKNOWN 0x0 /* link method - Unknown */
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#define MII_PHY_LINK_AUTO 0x1 /* link method - Auto-Negotiation */
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#define MII_PHY_LINK_FORCE 0x2 /* link method - Force link */
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/*
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* these values may be used in the default phy mode field of the load
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* string, since that is used to force the operating mode of the PHY
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* in case any attempt to establish the link failed.
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*/
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#define PHY_10BASE_T 0x00 /* 10 Base-T */
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#define PHY_10BASE_T_FDX 0x01 /* 10 Base Tx, full duplex */
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#define PHY_100BASE_TX 0x02 /* 100 Base Tx */
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#define PHY_100BASE_TX_FDX 0x03 /* 100 Base TX, full duplex */
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#define PHY_100BASE_T4 0x04 /* 100 Base T4 */
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#define PHY_AN_ENABLE 0x05 /* re-enable auto-negotiation */
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#define MII_FDX_STR "full duplex" /* full duplex mode */
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#define MII_FDX_LEN sizeof (MII_FDX_STR) /* full duplex mode */
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#define MII_HDX_STR "half duplex" /* half duplex mode */
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#define MII_HDX_LEN sizeof (MII_HDX_STR) /* full duplex mode */
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#define MII_AN_TBL_MAX 20 /* max number of entries in the table */
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/* allowed PHY's speeds */
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#define MII_1000MBS 1000000000 /* bits per sec */
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#define MII_100MBS 100000000 /* bits per sec */
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#define MII_10MBS 10000000 /* bits per sec */
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/* typedefs */
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typedef INT16 MII_AN_ORDER_TBL [MII_AN_TBL_MAX];
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typedef BOOL MII_PHY_BUS [MII_MAX_PHY_NUM];
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typedef struct mii_phy_node
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{
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NODE node;
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struct phy_info * pPhyInfo;
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} MII_PHY_NODE;
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/*
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* the structure below only represents the status of the PHY's registers
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* when they were last read through the MII interface
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*/
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typedef struct mii_regs
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{
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UINT16 phyStatus; /* PHY's status register */
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UINT16 phyCtrl; /* PHY's control register */
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UINT16 phyId1; /* PHY's identifier field 1 */
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UINT16 phyId2; /* PHY's identifier field 2 */
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UINT16 phyAds; /* PHY's advertisement register */
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UINT16 phyPrtn; /* PHY's partner register */
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UINT16 phyExp; /* PHY's expansion register */
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UINT16 phyNext; /* PHY's next page transmit register */
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} MII_REGS;
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typedef struct mii_g_regs
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{
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UINT16 phyRcvNext; /* PHY'S partner received next page */
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UINT16 phyMSCtrl; /* PHY'S MASTER-SLAVE Control register */
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UINT16 phyMSStatus; /* PHY'S MASTER-SLAVE Status register */
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UINT16 phyExtStatus; /* PHY'S extented Status register */
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} MII_G_REGS;
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/*
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* the structure below is to be allocated and filled in by the
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* driver before it attempts to use the miiPhyInit () routine. Some
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* of its field may be overwritten by miiPhyInit (), since their initial
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* values may not be appropriate. In addition, some field do not have
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* to be initialized by the calling task, since miiPhyInit () may use a
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* default value, whereas some other are mandatory. To help understand this,
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* the comment for each field includes flags stating whether the relevent
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* field in the PHY_INFO structure is an input (I) parameter to miiPhyInit (),
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* an output (O) parameter, or an input-output (I/O) parameter first,
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* and then whether it is optional (O) or mandatory (M). For output
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* parameters, the second flag is a "don't care" (X).
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*/
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typedef struct phy_info
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{
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MII_REGS miiRegs; /* PHY registers - (O|X) */
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UINT8 phyAddr; /* address of a PHY - (I/O)|(O) */
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UINT32 phyFlags; /* some flags - (I/O)|(O) */
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UINT32 phySpeed; /* 10/100 Mbit/sec - (O|X) */
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char phyMode[20]; /* half/full duplex mode - (O|X) */
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UINT32 phyDefMode; /* default operating mode - (I|O) */
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MII_AN_ORDER_TBL * phyAnOrderTbl; /* auto-negotiation table - (I|O) */
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FUNCPTR phyReadRtn; /* phy read routine - (I|M) */
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FUNCPTR phyWriteRtn; /* phy write routine - (I|M) */
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FUNCPTR phyDelayRtn; /* phy delay routine - (I|O) */
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UINT32 phyDelayParm; /* parameter to delay routine - (I|O) */
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UINT32 phyMaxDelay; /* phy max delay - (I|O) */
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void * pDrvCtrl; /* driver control structure - (I|M) */
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FUNCPTR phyLinkDownRtn; /* phy status down routine - (I|O) */
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MII_PHY_NODE * pMiiPhyNode; /* phy node - O */
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MII_PHY_BUS * miiPhyPresent; /* which PHYs are there - O */
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UINT32 phyLinkMethod; /* phy link method (Auto/Force) - (O|X) */
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UINT32 phyAutoNegotiateFlags; /* flag for auto-negotiation - (O|X) */
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MII_G_REGS miiGRegs; /* Giga Bit PHY registers - (O|X) */
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FUNCPTR pPhyOptRegsRtn; /* device specific pPhyOptRegsRtn */
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} PHY_INFO;
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/* globals */
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void miiPhyOptFuncSet (FUNCPTR optRegsFunc);
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STATUS miiPhyInit (PHY_INFO * pPhyInfo);
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STATUS miiLibUnInit (void);
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STATUS miiLibInit (void);
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STATUS miiPhyUnInit (PHY_INFO * pPhyInfo);
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void miiShow (PHY_INFO * pPhyInfo);
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STATUS miiRegsGet (PHY_INFO * pPhyInfo, UINT regNum, UCHAR * buff);
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STATUS miiAnCheck (PHY_INFO * pPhyInfo, UINT8 phyAddr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCmiiLibh */
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