687 lines
29 KiB
C
687 lines
29 KiB
C
/* Copyright 1984-1998 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01g,07jan99,cn fixed properly SPR# 22503 and SPR# 24296.
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01f,22oct98,cn added missing parenthesis in some defines (SPR# 22503).
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01e,13apr98,map moved SCC device definitions to ../multi/ppc860Cpm.h
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renamed SCC_DEV to SCC_UART_DEV
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01d,26mar98,map added SMC, SCC, PIP defines.
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01c,24may96,tpr changed statusMode from VINT16 to VUINT16.
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01b,22apr96,cah change definitions to be offsets from a known #define
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constant, rather than from a run-time IMMR register value.
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Changes are required in sysSerial.c for this as well.
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01a,11apr96,cah created.
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*/
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/*
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* This file contains constants for the Motorola MPC860 PowerPC
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* microcontroller chip.
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*/
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#ifndef __INCppc860Sioh
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#define __INCppc860Sioh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include "sioLib.h"
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#include "drv/multi/ppc860Cpm.h"
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#include "drv/multi/ppc860Siu.h"
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/* device and channel structures */
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/*
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* The PPC860SMC_CHAN structure defines a serial I/O channel which
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* describes the (TBD) registers for a given channel.
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* Also the various SIO driver functions ( ioctl, txStarup, callbackInstall,
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* pollInput, polloutput ) that this channel could utilize are declared
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* here.
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*/
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/* roughly things copied in structure form from multi/m68360.h */
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/* MPC860 Dual Ported Ram addresses */
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#define PPC860_DPR_SCC1(dprbase) ((VINT32 *) ((dprbase) + 0x1c00))
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#define PPC860_DPR_I2C(dprbase) ((VINT32 *) ((dprbase) + 0x1c80))
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#define PPC860_DPR_MISC(dprbase) ((VINT32 *) ((dprbase) + 0x1cb0))
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#define PPC860_DPR_IDMA1(dprbase) ((VINT32 *) ((dprbase) + 0x1cc0))
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#define PPC860_DPR_SCC2(dprbase) ((VINT32 *) ((dprbase) + 0x1d00))
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#define PPC860_DPR_SPI(dprbase) ((VINT32 *) ((dprbase) + 0x1d80))
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#define PPC860_DPR_TMR(dprbase) ((VINT32 *) ((dprbase) + 0x1db0))
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#define PPC860_DPR_IDMA2(dprbase) ((VINT32 *) ((dprbase) + 0x1dc0))
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#define PPC860_DPR_SCC3(dprbase) ((VINT32 *) ((dprbase) + 0x1e00))
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#define PPC860_DPR_SMC1(dprbase) ((VINT32 *) ((dprbase) + 0x1e80))
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#define PPC860_DPR_DSP1(dprbase) ((VINT32 *) ((dprbase) + 0x1ec0))
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#define PPC860_DPR_SCC4(dprbase) ((VINT32 *) ((dprbase) + 0x1f00))
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#define PPC860_DPR_SMC2(dprbase) ((VINT32 *) ((dprbase) + 0x1f80))
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#define PPC860_DPR_DSP2(dprbase) ((VINT32 *) ((dprbase) + 0x1fc0))
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/*
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* dual-ported parameter RAM SMC offsets
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* access these with SMC_RBASE(base_dpram_addr_of_this_SMC1)
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* base_dpram_addr_of_this_SMC1 == PPC860_DPR_SMC1(dprbase)
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* or == PPC860_DPR_SMC2(dprbase)
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*/
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#define SMC_RBASE(base) ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
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#define SMC_TBASE(base) ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
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#define SMC_RFCR(base) ((VINT8 *) ((base) + 0x04)) /* Rx Function Code */
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#define SMC_TFCR(base) ((VINT8 *) ((base) + 0x05)) /* Tx Function Code */
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#define SMC_MRBLR(base) ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
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#define SMC_RSTATE(base) ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
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#define SMC_RBPTR(base) ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
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#define SMC_TSTATE(base) ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
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#define SMC_TBPTR(base) ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
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#define SMC_MAX_IDL(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
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#define SMC_IDLC(base) ((VINT16 *) ((base) + 0x2A)) /* Temp Idle counter */
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#define SMC_BRKLN(base) ((VINT16 *) ((base) + 0x2C)) /* Last Rx Break length*/
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#define SMC_BRKEC(base) ((VINT16 *) ((base) + 0x2E)) /* Rx Brk Cond counter */
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#define SMC_BRKCR(base) ((VINT16 *) ((base) + 0x30)) /* Break Count reg (Tx)*/
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#define SMC_RMASK(base) ((VINT16 *) ((base) + 0x32)) /* Temp bit mask */
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/* dual ported parameter RAM PIP offsets */
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#define PIP_RBASE(base) ((VINT16 *)((base) + 0x00)) /* Rx Buff Descr Base */
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#define PIP_TBASE(base) ((VINT16 *)((base) + 0x01)) /* Tx Buff Descr Base */
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#define PIP_CFCR(base) ((VINT8 *)((base) + 0x04)) /* Cent. Function Code */
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#define PIP_SMASK(base) ((VINT8 *)((base) + 0x05)) /* Status mask */
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/*
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* dual-ported parameter RAM SCC offsets
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* access these with SCC_RBASE(base_dpram_addr_of_this_SCC1)
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* base_dpram_addr_of_this_SCC1 == PPC860_DPR_SCC1(dprbase)
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* or == PPC860_DPR_SCC1(dprbase)
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*/
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#define SCC_RBASE(base) ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
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#define SCC_TBASE(base) ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
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#define SCC_RFCR(base) ((VINT8 *) ((base) + 0x04)) /* Rx Function Code */
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#define SCC_TFCR(base) ((VINT8 *) ((base) + 0x05)) /* Tx Function Code */
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#define SCC_MRBLR(base) ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
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#define SCC_RSTATE(base) ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
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#define SCC_RBPTR(base) ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
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#define SCC_TSTATE(base) ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
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#define SCC_TBPTR(base) ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
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#define SCC_RCRC(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
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#define SCC_TCRC(base) ((VINT16 *) ((base) + 0x2C)) /* Max Idle characters */
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#define SCC_MAX_IDL(base) ((VINT16 *) ((base) + 0x38)) /* Max Idle characters */
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#define SCC_IDLC(base) ((VINT16 *) ((base) + 0x3A)) /* Temp Idle counter */
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#define SCC_BRKCR(base) ((VINT16 *) ((base) + 0x3C)) /* Break Count Reg (Tx)*/
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#define SCC_PAREC(base) ((VINT16 *) ((base) + 0x3E)) /* Rx Parity Err Cnt */
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#define SCC_FRMEC(base) ((VINT16 *) ((base) + 0x40)) /* Rx Frame Err Cnt */
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#define SCC_NOSEC(base) ((VINT16 *) ((base) + 0x42)) /* Receive Noise Cnt */
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/*
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* dual-ported parameter RAM I2C offsets
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* access these with I2C_RPBASE(base_dpram_addr_of_I2C)
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*/
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#define I2C_RPBASE(base) ((VINT16 *) ((char *)base + 0x2C))
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typedef struct /* SMC_BUF */
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{
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VUINT16 statusMode; /* status and control */
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VINT16 dataLength; /* length of data buffer in bytes */
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u_char * dataPointer; /* points to data buffer */
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} SMC_BUF;
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typedef struct /* SMC_PARAM */
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{ /* offset description*/
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VINT16 rbase; /* 00 Rx buffer descriptor base address */
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VINT16 tbase; /* 02 Tx buffer descriptor base address */
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VINT8 rfcr; /* 04 Rx function code */
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VINT8 tfcr; /* 05 Tx function code */
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VINT16 mrblr; /* 06 maximum receive buffer length */
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VINT32 rstate; /* 08 Rx internal state */
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VINT32 res1; /* 0C Rx internal data pointer */
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VINT16 rbptr; /* 10 Rx buffer descriptor pointer */
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VINT16 res2; /* 12 reserved/internal */
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VINT32 res3; /* 14 reserved/internal */
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VINT32 tstate; /* 18 Tx internal state */
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VINT32 res4; /* 1C reserved/internal */
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VINT16 tbptr; /* 20 Tx buffer descriptor pointer */
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VINT16 res5; /* 22 reserved/internal */
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VINT32 res6; /* 24 reserved/internal */
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VINT16 maxidl; /* 28 Maximum idle characters */
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VINT16 idlc; /* 2A temporary idle counter */
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VINT16 brkln; /* 2C last recv break length */
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VINT16 brkec; /* 2E recv break condition counter */
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VINT16 brkcr; /* 30 xmit break count register */
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VINT16 r_mask; /* 32 temporary bit mask */
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} SMC_PARAM;
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typedef struct /* SMC */
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{
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SMC_PARAM param; /* SMC parameters */
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} SMC;
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typedef struct /* SMC_REG */
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{
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VINT16 smcmr; /* SMC Mode register */
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VINT8 res1[2]; /* reserved */
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VINT8 smce; /* SMC Event register */
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VINT8 res2[3]; /* reserved */
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VINT8 smcm; /* SMC Mask register */
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} SMC_REG;
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/* SMC device descriptor */
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typedef struct /* SMC_DEV */
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{
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int smcNum; /* number of SMC device (1 or 2)*/
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int txBdNum; /* number of transmit buf descriptors */
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int rxBdNum; /* number of receive buf descriptors */
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SMC_BUF * txBdBase; /* transmit BD base address */
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SMC_BUF * rxBdBase; /* receive BD base address */
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u_char * txBufBase; /* transmit buffer base address */
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u_char * rxBufBase; /* receive buffer base address */
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VINT32 txBufSize; /* transmit buffer size */
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VINT32 rxBufSize; /* receive buffer size */
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int txBdNext; /* next transmit BD to fill */
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int rxBdNext; /* next receive BD to read */
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volatile SMC * pSmc; /* SMC parameter RAM. Must point */
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/* at DPRAM area for SMC1 or SMC2 */
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volatile SMC_REG * pSmcReg; /* SMC registers must point at */
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/* SMCMR1 or SMCMR2 */
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VINT32 intMask; /* interrupt acknowledge mask */
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} SMC_DEV;
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/* SCC device descriptor */
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typedef struct /* SCC_UART_DEV */
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{
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int sccNum; /* number of SCC device */
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int txBdNum; /* number of transmit buf descriptors */
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int rxBdNum; /* number of receive buf descriptors */
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SCC_BUF * txBdBase; /* transmit BD base address */
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SCC_BUF * rxBdBase; /* receive BD base address */
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u_char * txBufBase; /* transmit buffer base address */
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u_char * rxBufBase; /* receive buffer base address */
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VINT32 txBufSize; /* transmit buffer size */
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VINT32 rxBufSize; /* receive buffer size */
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int txBdNext; /* next transmit BD to fill */
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int rxBdNext; /* next receive BD to read */
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volatile SCC * pScc; /* SCC parameter RAM */
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volatile SCC_REG * pSccReg; /* SCC registers */
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VINT32 intMask; /* interrupt acknowledge mask */
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} SCC_UART_DEV;
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typedef struct /* I2C_PARAM */
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{ /* offset description */
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VINT16 rbase; /* 00 Rx buffer descriptors base address */
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VINT16 tbase; /* 02 Tx buffer descriptors base address */
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VINT8 rfcr; /* 04 Rx function code */
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VINT8 tfcr; /* 05 Tx function code */
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VINT16 mrblr; /* 06 maximum receive buffer length */
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VINT32 ris; /* 08 Rx internal state */
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VINT32 ridp; /* 0c Rx internal data pointer */
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VINT16 rbptr; /* 10 Rx buffer descriptor pointer */
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VINT16 ribc; /* 12 Rx internal byte count */
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VINT32 rt; /* 14 Rx temp */
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VINT32 tis; /* 18 Tx internal state */
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VINT32 tidp; /* 1c Tx internal data pointer */
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VINT16 tbptr; /* 20 Tx buffer descriptor pointer */
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VINT16 tibc; /* 22 Tx internal byte count */
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VINT32 tt; /* 24 Tx temp */
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VINT32 notused; /* 28 not used */
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VINT16 rpbase; /* 2c relocatable parameter RAM base */
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VINT16 reserved; /* 2e reserved */
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} I2C_PARAM;
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/* standard dual-mode serial driver header structure follows */
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typedef struct ppc860_chan /* PPC860SMC_CHAN */
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{
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/* always goes first */
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SIO_DRV_FUNCS *pDrvFuncs; /* driver functions */
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/* callbacks */
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STATUS (*getTxChar)(); /* pointer to a xmitr function */
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STATUS (*putRcvChar)();/* pointer to a recvr function */
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void * getTxArg;
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void * putRcvArg;
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VINT16 int_vec; /* interrupt vector number */
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VINT16 channelMode; /* SIO_MODE */
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int baudRate;
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int clockRate; /* CPU clock frequency (Hz) */
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int bgrNum; /* number of BRG being used */
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VINT32 * pBaud; /* BRG registers */
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VINT32 regBase; /* register/DPR base address */
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SMC_DEV uart; /* UART SCC device */
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} PPC860SMC_CHAN;
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/* serial procedures */
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IMPORT void ppc860DevInit (PPC860SMC_CHAN *);
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IMPORT void ppc860Int (PPC860SMC_CHAN *);
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IMPORT void ppc800DevInit (PPC860SMC_CHAN *);
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IMPORT void ppc800Int (PPC860SMC_CHAN *);
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/* standard dual-mode serial driver header structure follows - SCC */
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typedef struct ppc860Scc_chan /* PPC860SCC_CHAN */
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{
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/* always goes first */
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SIO_DRV_FUNCS *pDrvFuncs; /* driver functions */
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/* callbacks */
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STATUS (*getTxChar)(); /* pointer to a xmitr function */
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STATUS (*putRcvChar)();/* pointer to a recvr function */
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void * getTxArg;
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void * putRcvArg;
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VINT16 int_vec; /* interrupt vector number */
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VINT16 channelMode; /* SIO_MODE */
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int baudRate;
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int clockRate; /* CPU clock frequency (Hz) */
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int bgrNum; /* number of BRG being used */
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VINT32 * pBaud; /* BRG registers */
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VINT32 regBase; /* register/DPR base address */
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SCC_UART_DEV uart; /* UART SCC device */
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} PPC860SCC_CHAN;
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/* function declarations */
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IMPORT void ppc860SccInt (PPC860SCC_CHAN *);
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IMPORT void ppc860SccDevInit (PPC860SCC_CHAN *);
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/* channels */
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#define PPC860_CHANNEL_A 0
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#define PPC860_CHANNEL_B 1
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#define PPC860SMC_N_CHANS 2 /* number of serial channels on chip */
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/* SIO -- mpc860 serial channel chip -- register definitions */
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/* Buffer Descriptor Pointer Definitions */
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/* Receive BD status bits 16-bit value */
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#define BD_RX_EMPTY_BIT 0x8000 /* buffer is empty */
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#define BD_RX_WRAP_BIT 0x2000 /* last BD in chain */
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#define BD_RX_INTERRUPT_BIT 0x1000 /* set interrupt when filled */
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#define BD_RX_CON_MODE_BIT 0x0200 /* Continuous Mode bit */
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#define BD_RX_IDLE_CLOSE_BIT 0x0100 /* Close on IDLE recv bit */
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#define BD_RX_BREAK_CLOSE_BIT 0x0020 /* Close on break recv bit */
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#define BD_RX_FRAME_CLOSE_BIT 0x0010 /* Close on frame error bit */
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#define BD_RX_PARITY_ERROR_BIT 0x0008 /* Parity error in last byte */
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#define BD_RX_OVERRUN_ERROR_BIT 0x0002 /* Overrun occurred */
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/* Transmit BD status bits 16-bit value */
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#define BD_TX_READY_BIT 0x8000 /* Transmit ready/busy bit */
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#define BD_TX_WRAP_BIT 0x2000 /* last BD in chain */
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#define BD_TX_INTERRUPT_BIT 0x1000 /* set interrupt when emptied */
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#define BD_TX_CON_MODE_BIT 0x0200 /* Continuous Mode bit */
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#define BD_TX_PREAMBLE_BIT 0x0100 /* send preamble sequence */
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#define BD_STATUS_OFFSET 0x00 /* two bytes */
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#define BD_DATA_LENGTH_OFFSET 0x02 /* two bytes */
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#define BD_BUF_POINTER_OFFSET 0x04 /* four bytes */
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/*
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* MPC860 internal register/memory map (section 17 of prelim. spec)
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* note that these are offsets from the value stored in the IMMR
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* register, which is in the PowerPC special register address space
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* at register number 638
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*/
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/**** SIU module configuration ***/
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#define MPC860_SIUMCR(base) ((VINT32 *) ((base) + 0x00))
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/**** System Protection Control ***/
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#define MPC860_SYPCR(base) ((VINT32 *) ((base) + 0x04))
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/**** SW watch dog timer value ***/
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#define MPC860_SWT(base) ((VINT32 *) ((base) + 0x08))
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/*** Software service reg ***/
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#define MPC860_SWSR(base) ((VINT16 *) ((base) + 0x0E))
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/*** Interrupt pending reg ***/
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#define MPC860_SIPEND(base) ((VINT32 *) ((base) + 0x10))
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/*** Interrupt Mask reg ***/
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#define MPC860_SIMASK(base) ((VINT32 *) ((base) + 0x14))
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/*** Interrupt Edge level mask ***/
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#define MPC860_SIEL(base) ((VINT32 *) ((base) + 0x18))
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/*** Interrupt Vector reg ***/
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#define MPC860_SIVEC(base) ((VINT32 *) ((base) + 0x1C))
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/*** Transfer error status ***/
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#define MPC860_TESR(base) ((VINT32 *) ((base) + 0x20))
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/*** SDMA Config reg ***/
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#define MPC860_SDCR(base) ((VINT32 *) ((base) + 0x30))
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/*** CP Interrupt vector reg ***/
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#define MPC860_CIVR(base) ((VINT16 *) ((base) + 0x930))
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/*** CP Interrupt config reg ***/
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#define MPC860_CICR(base) ((VINT32 *) ((base) + 0x940))
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/*** CP Interrupt pending reg ***/
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#define MPC860_CIPR(base) ((VINT32 *) ((base) + 0x944))
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/*** CP Interrupt mask reg ***/
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#define MPC860_CIMR(base) ((VINT32 *) ((base) + 0x948))
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/*** CP Interrupt in-service reg ***/
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#define MPC860_CISR(base) ((VINT32 *) ((base) + 0x94C))
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/*** Port A data direction reg ***/
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#define MPC860_PADIR(base) ((VINT16 *) ((base) + 0x950))
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/*** Port A pin assign reg ***/
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#define MPC860_PAPAR(base) ((VINT16 *) ((base) + 0x952))
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/*** Port A open drain reg ***/
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#define MPC860_PAODR(base) ((VINT16 *) ((base) + 0x954))
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/*** Port A data reg ***/
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#define MPC860_PADAT(base) ((VINT16 *) ((base) + 0x956))
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/*** Port C data direction reg ***/
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#define MPC860_PCDIR(base) ((VINT16 *) ((base) + 0x960))
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/*** Port C pin assign reg ***/
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#define MPC860_PCPAR(base) ((VINT16 *) ((base) + 0x962))
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/*** Port C special options reg ***/
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#define MPC860_PCSO(base) ((VINT16 *) ((base) + 0x964))
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/*** Port C data reg ***/
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#define MPC860_PCDAT(base) ((VINT16 *) ((base) + 0x966))
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/*** Port C interrupt control reg ***/
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#define MPC860_PCINT(base) ((VINT16 *) ((base) + 0x968))
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/*** Port D data direction reg ***/
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#define MPC860_PDDIR(base) ((VINT16 *) ((base) + 0x970))
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/*** Port D pin assign reg ***/
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#define MPC860_PDPAR(base) ((VINT16 *) ((base) + 0x972))
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/*** Port D data reg ***/
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#define MPC860_PDDAT(base) ((VINT16 *) ((base) + 0x976))
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|
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/*** Comm processor cmd reg ***/
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#define MPC860_CPCR(base) ((VINT16 *) ((base) + 0x9C0))
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/*** RISC config reg ***/
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|
#define MPC860_RCCR(base) ((VINT16 *) ((base) + 0x9C4))
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/*** RISC dev support status reg ***/
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|
#define MPC860_RMDS(base) ((VINT8 *) ((base) + 0x9C7))
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/*** RISC ucode dev spt control reg ***/
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|
#define MPC860_RMDR(base) ((VINT32 *) ((base) + 0x9C8))
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/*** RISC controller trap reg 1 ***/
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#define MPC860_RCTR1(base) ((VINT16 *) ((base) + 0x9CC))
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/*** RISC controller trap reg 2 ***/
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#define MPC860_RCTR2(base) ((VINT16 *) ((base) + 0x9CE))
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/*** RISC controller trap reg 3 ***/
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#define MPC860_RCTR3(base) ((VINT16 *) ((base) + 0x9D0))
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/*** RISC controller trap reg 4 ***/
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#define MPC860_RCTR4(base) ((VINT16 *) ((base) + 0x9D2))
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/*** RISC Timers event reg ***/
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#define MPC860_RTER(base) ((VINT16 *) ((base) + 0x9D6))
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/*** RISC Timers mask reg ***/
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#define MPC860_RTMR(base) ((VINT16 *) ((base) + 0x9DA))
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/*** baud rate generation register set ***/
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/*** BRG1 configuration reg ***/
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#define MPC860_BRGC1(base) ((VINT32 *) ((base) + 0x9F0))
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/*** BRG2 configuration reg ***/
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#define MPC860_BRGC2(base) ((VINT32 *) ((base) + 0x9F4))
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/*** BRG3 configuration reg ***/
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#define MPC860_BRGC3(base) ((VINT32 *) ((base) + 0x9F8))
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/*** BRG4 configuration reg ***/
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#define MPC860_BRGC4(base) ((VINT32 *) ((base) + 0x9FC))
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/*** SCC1 Mode reg low ***/
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#define MPC860_GSMR_L1(base) ((VINT32 *) ((base) + 0xA00))
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/*** SCC1 Mode reg High ***/
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#define MPC860_GSMR_H1(base) ((VINT32 *) ((base) + 0xA04))
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/*** SCC1 Protocol Specific Mode reg ***/
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#define MPC860_PSMR1(base) ((VINT16 *) ((base) + 0xA08))
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/*** SCC1 Transmit-On-Demand reg ***/
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#define MPC860_TODR1(base) ((VINT16 *) ((base) + 0xA0C))
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/*** SCC1 Data Synchronization reg ***/
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#define MPC860_DSR1(base) ((VINT16 *) ((base) + 0xA0E))
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/*** SCC1 Event reg ***/
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#define MPC860_SCCE1(base) ((VINT16 *) ((base) + 0xA10))
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/*** SCC1 Mask reg ***/
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#define MPC860_SCCM1(base) ((VINT16 *) ((base) + 0xA14))
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/*** SCC1 Status reg ***/
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#define MPC860_SCCS1(base) ((VINT8 *) ((base) + 0xA17))
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/*** SCC2 Mode reg low ***/
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#define MPC860_GSMR_L2(base) ((VINT32 *) ((base) + 0xA20))
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/*** SCC2 Mode reg High ***/
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#define MPC860_GSMR_H2(base) ((VINT32 *) ((base) + 0xA24))
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/*** SCC2 Protocol Specific Mode reg ***/
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#define MPC860_PSMR2(base) ((VINT16 *) ((base) + 0xA28))
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/*** SCC2 Transmit-On-Demand reg ***/
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#define MPC860_TODR2(base) ((VINT16 *) ((base) + 0xA2C))
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/*** SCC2 Data Synchronization reg ***/
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#define MPC860_DSR2(base) ((VINT16 *) ((base) + 0xA2E))
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/*** SCC2 Event reg ***/
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#define MPC860_SCCE2(base) ((VINT16 *) ((base) + 0xA30))
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/*** SCC2 Mask reg ***/
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#define MPC860_SCCM2(base) ((VINT16 *) ((base) + 0xA34))
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/*** SCC2 Status reg ***/
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#define MPC860_SCCS2(base) ((VINT8 *) ((base) + 0xA37))
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/*** SCC3 Mode reg low ***/
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#define MPC860_GSMR_L3(base) ((VINT32 *) ((base) + 0xA40))
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/*** SCC3 Mode reg High ***/
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#define MPC860_GSMR_H3(base) ((VINT32 *) ((base) + 0xA44))
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/*** SCC3 Protocol Specific Mode reg ***/
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|
#define MPC860_PSMR3(base) ((VINT16 *) ((base) + 0xA48))
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/*** SCC3 Transmit-On-Demand reg ***/
|
|
#define MPC860_TODR3(base) ((VINT16 *) ((base) + 0xA4C))
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/*** SCC3 Data Synchronization reg ***/
|
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#define MPC860_DSR3(base) ((VINT16 *) ((base) + 0xA4E))
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/*** SCC3 Event reg ***/
|
|
#define MPC860_SCCE3(base) ((VINT16 *) ((base) + 0xA50))
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/*** SCC3 Mask reg ***/
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|
#define MPC860_SCCM3(base) ((VINT16 *) ((base) + 0xA54))
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/*** SCC3 Status reg ***/
|
|
#define MPC860_SCCS3(base) ((VINT8 *) ((base) + 0xA57))
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|
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/*** SCC4 Mode reg low ***/
|
|
#define MPC860_GSMR_L4(base) ((VINT32 *) ((base) + 0xA60))
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|
/*** SCC4 Mode reg High ***/
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|
#define MPC860_GSMR_H4(base) ((VINT32 *) ((base) + 0xA64))
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/*** SCC4 Protocol Specific Mode reg ***/
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#define MPC860_PSMR4(base) ((VINT16 *) ((base) + 0xA68))
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/*** SCC4 Transmit-On-Demand reg ***/
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#define MPC860_TODR4(base) ((VINT16 *) ((base) + 0xA6C))
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/*** SCC4 Data Synchronization reg ***/
|
|
#define MPC860_DSR4(base) ((VINT16 *) ((base) + 0xA6E))
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/*** SCC4 Event reg ***/
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|
#define MPC860_SCCE4(base) ((VINT16 *) ((base) + 0xA70))
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/*** SCC4 Mask reg ***/
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#define MPC860_SCCM4(base) ((VINT16 *) ((base) + 0xA74))
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/*** SCC4 Status reg ***/
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|
#define MPC860_SCCS4(base) ((VINT8 *) ((base) + 0xA77))
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/*** SMC1 Mode reg ***/
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|
#define MPC860_SMCMR1(base) ((VINT16 *) ((base) + 0xA82))
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/*** SMC1 Event reg ***/
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#define MPC860_SMCE1(base) ((VINT8 *) ((base) + 0xA86))
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/*** SMC1 Mask reg ***/
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#define MPC860_SMCM1(base) ((VINT8 *) ((base) + 0xA8A))
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/*** SMC2 Mode reg ***/
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#define MPC860_SMCMR2(base) ((VINT16 *) ((base) + 0xA92))
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/*** SMC2 or PIP Event reg ***/
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#define MPC860_SMCE2(base) ((VINT8 *) ((base) + 0xA96))
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/*** SMC2 Mask reg ***/
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#define MPC860_SMCM2(base) ((VINT8 *) ((base) + 0xA9A))
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/*** SPI Mode reg ***/
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#define MPC860_SPMODE(base) ((VINT16 *) ((base) + 0xAA0))
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/*** SPI Event reg ***/
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|
#define MPC860_SPIE(base) ((VINT8 *) ((base) + 0xAA6))
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/*** SPI Mask reg ***/
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#define MPC860_SPIM(base) ((VINT8 *) ((base) + 0xAAA))
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/*** SPI Command reg ***/
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#define MPC860_SPCOM(base) ((VINT8 *) ((base) + 0xAAD))
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/*** PIP Configuration reg ***/
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#define MPC860_PIPC(base) ((VINT16 *) ((base) + 0xAB2))
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/*** PIP Timing params reg ***/
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#define MPC860_PTPR(base) ((VINT16 *) ((base) + 0xAB6))
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/*** Port B data direction reg ***/
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#define MPC860_PBDIR(base) ((VINT32 *) ((base) + 0xAB8))
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/*** Port B pin assign reg ***/
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#define MPC860_PBPAR(base) ((VINT32 *) ((base) + 0xABC))
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/*** Port B open drain reg ***/
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#define MPC860_PBODR(base) ((VINT16 *) ((base) + 0xAC2))
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/*** Port B Data register ***/
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#define MPC860_PBDAT(base) ((VINT32 *) ((base) + 0xAC4))
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/*** SI Mode reg ***/
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#define MPC860_SIMODE(base) ((VINT32 *) ((base) + 0xAE0))
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/*** SI Global Mode reg ***/
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#define MPC860_SIGMR(base) ((VINT8 *) ((base) + 0xAE4))
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/*** SI Status reg ***/
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#define MPC860_SISTR(base) ((VINT8 *) ((base) + 0xAE6))
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/*** SI Command reg ***/
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#define MPC860_SICMR(base) ((VINT8 *) ((base) + 0xAE7))
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/*** SI Clock route reg ***/
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#define MPC860_SICR(base) ((VINT32 *) ((base) + 0xAEC))
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/*** SI RAM pointers reg ***/
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|
#define MPC860_SIRP(base) ((VINT32 *) ((base) + 0xAF0))
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/*** SI Routing RAM base addr ***/
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|
#define MPC860_SIRAM_BASE(base) ((base) + 0xC00)
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/*** Data Param RAM base addr ***/
|
|
#define MPC860_DPRAM_BASE(base) ((base) + 0x2000)
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/* Register Equates By Bit */
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/* Equates for Baud Rate Generation Registers */
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#define MPC860_BRGC_RST 0x20000 /* 1 = reset BRG */
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#define MPC860_BRGC_ENABLE_CNT 0x10000 /* 1 = enable clocks to BRG */
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#define MPC860_BRGC_BRGCLK_SRC 0x00000 /* Baud Rate Gen clock src */
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#define MPC860_BRGC_CLK2_SRC 0x04000 /* CLK2 pin = BRG source */
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#define MPC860_BRGC_CLK6_SRC 0x08000 /* CLK6 pin = BRG source */
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#define MPC860_BRGC_AUTOBAUD 0x02000 /* 1 = autobaud on Rx */
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/* 0 = normal operation */
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|
#define MPC860_BRGC_CLKDIV_MASK 0x01FFE /* 12 bit value */
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#define MPC860_BRGC_CLKDIV_SHIFT 0x1 /* shifted up one bit */
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#define MPC860_BRGC_PRESCALE_16 0x00001 /* 1 = divide-by-16 clock */
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/* Equates for SIMODE register */
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#define MPC860_SIMODE_SMC2_MUX 0x80000000 /* connected to mux SI */
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#define MPC860_SIMODE_SMC2_NMSI 0x00000000 /* connected to mux SI */
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#define MPC860_SIMODE_SMC2_BRG1 0x00000000 /* BRG1 is clock source */
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#define MPC860_SIMODE_SMC2_BRG2 0x10000000 /* BRG2 is clock source */
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#define MPC860_SIMODE_SMC2_BRG3 0x20000000 /* BRG3 is clock source */
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|
#define MPC860_SIMODE_SMC2_BRG4 0x30000000 /* BRG4 is clock source */
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|
#define MPC860_SIMODE_SMC2_CLK5 0x40000000 /* CLK5 is clock source */
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|
#define MPC860_SIMODE_SMC2_CLK6 0x50000000 /* CLK6 is clock source */
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|
#define MPC860_SIMODE_SMC2_CLK7 0x60000000 /* CLK7 is clock source */
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|
#define MPC860_SIMODE_SMC2_CLK8 0x70000000 /* CLK8 is clock source */
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|
|
|
#define MPC860_SIMODE_SMC1_MUX 0x00008000 /* connected to mux SI */
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|
#define MPC860_SIMODE_SMC1_NMSI 0x00000000 /* connected to mux SI */
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|
#define MPC860_SIMODE_SMC1_BRG1 0x00000000 /* BRG1 is clock source */
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|
#define MPC860_SIMODE_SMC1_BRG2 0x00001000 /* BRG2 is clock source */
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|
#define MPC860_SIMODE_SMC1_BRG3 0x00002000 /* BRG3 is clock source */
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|
#define MPC860_SIMODE_SMC1_BRG4 0x00003000 /* BRG4 is clock source */
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|
#define MPC860_SIMODE_SMC1_CLK1 0x00004000 /* CLK1 is clock source */
|
|
#define MPC860_SIMODE_SMC1_CLK2 0x00005000 /* CLK2 is clock source */
|
|
#define MPC860_SIMODE_SMC1_CLK3 0x00006000 /* CLK3 is clock source */
|
|
#define MPC860_SIMODE_SMC1_CLK4 0x00007000 /* CLK4 is clock source */
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|
|
|
#define MPC860_SIMODE_TDMB_NORM 0x00000000 /* normal operation */
|
|
#define MPC860_SIMODE_TDMB_ECHO 0x04000000 /* auto echo */
|
|
#define MPC860_SIMODE_TDMB_LOOP 0x08000000 /* internal loopback */
|
|
#define MPC860_SIMODE_TDMB_LCTR 0x0C000000 /* loopback control */
|
|
|
|
/*
|
|
* Equates for SMCE SM UART-mode Event Register
|
|
* writing a one to these location clears an event/interrupt
|
|
*/
|
|
#define MPC860_SMCE_UART_BRK_EVENT 0x10 /* break char received */
|
|
#define MPC860_SMCE_UART_BSY_EVENT 0x04 /* char discarded no bufs */
|
|
#define MPC860_SMCE_UART_TX_EVENT 0x02 /* char transmitted */
|
|
#define MPC860_SMCE_UART_RX_EVENT 0x01 /* char received */
|
|
#define MPC860_SMCE_UART_ALL_EVENTS ( \
|
|
MPC860_SMCE_UART_BRK_EVENT | \
|
|
MPC860_SMCE_UART_BSY_EVENT | \
|
|
MPC860_SMCE_UART_TX_EVENT | \
|
|
MPC860_SMCE_UART_RX_EVENT )
|
|
|
|
|
|
/*
|
|
* Equates for SMCM SM UART-mode Mask Register
|
|
* writing a one to these locations masks an event/interrupt
|
|
*/
|
|
#define MPC860_SMCM_UART_BRK_MASK 0x10 /* break char received */
|
|
#define MPC860_SMCM_UART_BSY_MASK 0x04 /* char discarded no bufs */
|
|
#define MPC860_SMCM_UART_TX_MASK 0x02 /* char transmitted */
|
|
#define MPC860_SMCM_UART_RX_MASK 0x01 /* char received */
|
|
|
|
/* Equates for CICR register CP interrupt configuration register */
|
|
#define MPC860_CICR_IRL_LEVEL_0 0x00000000 /* highest interrupt level */
|
|
#define MPC860_CICR_IRL_LEVEL_1 0x00020000
|
|
#define MPC860_CICR_IRL_LEVEL_2 0x00040000
|
|
#define MPC860_CICR_IRL_LEVEL_3 0x00060000
|
|
#define MPC860_CICR_IRL_LEVEL_4 0x00080000 /* standard value */
|
|
#define MPC860_CICR_IRL_LEVEL_5 0x000A0000
|
|
#define MPC860_CICR_IRL_LEVEL_6 0x000C0000
|
|
#define MPC860_CICR_IRL_LEVEL_7 0x000E0000 /* lowest */
|
|
#define MPC860_CICR_HP_SRC_STD 0x0001F000 /* highest priority int */
|
|
#define MPC860_CICR_MASTER_IEN 0x00000080 /* master interrupt enable */
|
|
|
|
/* Equates for CIMR register CP interrupt mask register */
|
|
#define MPC860_CIMR_SCC1_MASK 0x40000000 /* mask SCC1 interrupt */
|
|
#define MPC860_CIMR_SCC2_MASK 0x20000000 /* mask SCC2 interrupt */
|
|
#define MPC860_CIMR_SMC1_MASK 0x00000010 /* mask SMC1 interrupt */
|
|
#define MPC860_CIMR_SMC2_MASK 0x00000008 /* mask SMC2 interrupt */
|
|
|
|
/* Equates for RFCR register receive function code register */
|
|
#define MPC860_RFCR_DEC_LE 0x00 /* DEC little endian mode */
|
|
#define MPC860_RFCR_PPC_LE 0x08 /* PPC little endian mode */
|
|
/* reverse transmission order of */
|
|
/* bytes compared to DEC/Intel mode */
|
|
#define MPC860_RFCR_MOT_BE 0x18 /* big endian mode */
|
|
|
|
/* Equates for TFCR register transmission function code register */
|
|
#define MPC860_TFCR_DEC_LE 0x00 /* DEC little endian mode */
|
|
#define MPC860_TFCR_PPC_LE 0x08 /* PPC little endian mode */
|
|
/* reverse transmission order of */
|
|
/* bytes compared to DEC/Intel mode */
|
|
#define MPC860_TFCR_MOT_BE 0x18 /* big endian mode */
|
|
|
|
/* Equates for SMC Mode Register SMCMR */
|
|
#define MPC860_SMCMR_CLEN_MASK 0x7800 /* # bits in char minus one */
|
|
/* set to # data bits + # parity */
|
|
/* bits + # stop bits */
|
|
#define MPC860_SMCMR_CLEN_STD 0x4800 /* for 8-N-1 std serial I/O */
|
|
#define MPC860_SMCMR_STOPLEN_1 0x0000 /* stop length = 1 */
|
|
#define MPC860_SMCMR_STOPLEN_2 0x0400 /* stop length = 2 */
|
|
#define MPC860_SMCMR_NO_PARITY 0x0000 /* parity disabled */
|
|
#define MPC860_SMCMR_PARITY 0x0200 /* parity enabled */
|
|
#define MPC860_SMCMR_PARITY_ODD 0x0000 /* odd parity if enabled */
|
|
#define MPC860_SMCMR_PARITY_EVEN 0x0100 /* even parity if enabled */
|
|
#define MPC860_SMCMR_GCI_MODE 0x0000 /* GCI or SCIT mode */
|
|
#define MPC860_SMCMR_UART_MODE 0x0020 /* UART mode */
|
|
#define MPC860_SMCMR_TRANS_MODE 0x0030 /* totally transparent mode */
|
|
#define MPC860_SMCMR_NORM_MODE 0x0000 /* normal operation mode */
|
|
#define MPC860_SMCMR_LOOP_MODE 0x0004 /* local loopback mode */
|
|
#define MPC860_SMCMR_ECHO_MODE 0x0008 /* echo mode */
|
|
#define MPC860_SMCMR_TX_ENABLE 0x0002 /* enable transmitter */
|
|
#define MPC860_SMCMR_TX_DISABLE 0x0000 /* disable transmitter */
|
|
#define MPC860_SMCMR_RX_ENABLE 0x0001 /* enable receiver */
|
|
#define MPC860_SMCMR_RX_DISABLE 0x0000 /* disable receiver */
|
|
|
|
#define MPC860_SMCMR_STD_MODE ( \
|
|
MPC860_SMCMR_CLEN_STD | \
|
|
MPC860_SMCMR_STOPLEN_1 | \
|
|
MPC860_SMCMR_NO_PARITY | \
|
|
MPC860_SMCMR_UART_MODE | \
|
|
MPC860_SMCMR_NORM_MODE )
|
|
#define MPC860_SCMCR_STD_MODE_ENABLED ( \
|
|
MPC860_SMCMR_STD_MODE | \
|
|
MPC860_SMCMR_TX_ENABLE | \
|
|
MPC860_SMCMR_RX_ENABLE )
|
|
|
|
#endif /* _ASMLANGUAGE */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __INCppc860Sioh */
|