155 lines
6.3 KiB
C
155 lines
6.3 KiB
C
/* m8260Cp.h - Motorola MPC8260 Communications Processor header file */
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/* Copyright 1984-1999 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,12sep99,ms_ created from m8260Cpm.h, 01d.
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*/
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/*
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* This file contains constants for the Communication Processor in
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* the Motorola MPC8260 PowerQUICC II integrated Communications Processor
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*/
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#ifndef __INCm8260Cph
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#define __INCm8260Cph
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef M8260ABBREVIATIONS
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#define M8260ABBREVIATIONS
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
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typedef volatile INT32 VINT32; /* volatile unsigned word */
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typedef volatile INT16 VINT16; /* volatile unsigned halfword */
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typedef volatile INT8 VINT8; /* volatile unsigned byte */
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
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typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#endif /* M8260ABBREVIATIONS */
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/*
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* MPC8260 internal register/memory map (section 17 of prelim. spec)
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* note that these are offsets from the value stored in the IMMR
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* register. Also note that in the MPC8260, the IMMR is not a special
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* purpose register, but it is memory mapped.
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*/
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/* Command Register definitions (CPCR - 0x119C0) */
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#define M8260_CPCR(base) (CAST(VUINT32 *)((base) + 0x119C0)) /* CPCR */
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#define M8260_CPCR_LATENCY (65536 * 400) /* worst case exec latency */
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#define M8260_CPCR_RESET 0x80000000 /* software reset command */
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#define M8260_CPCR_PAGE_MSK 0x7c000000 /* RAM page number */
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#define M8260_CPCR_SBC_MSK 0x03e00000 /* sub-block code */
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#define M8260_CPCR_RES1 0x001e0000 /* reserved */
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#define M8260_CPCR_FLG 0x00010000 /* flag - command executing */
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#define M8260_CPCR_RES2 0x0000c000 /* reserved */
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#define M8260_CPCR_MCN_MSK 0x00003fc0 /* MCC channel number */
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#define M8260_CPCR_RES3 0x00000030 /* reserved */
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#define M8260_CPCR_OP_MSK 0x0000000f /* command opcode */
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#define M8260_CPCR_PAGE_SHIFT 0x1a /* get to the page field */
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#define M8260_CPCR_SBC_SHIFT 0x15 /* get to the SBC field */
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#define M8260_CPCR_MCN_SHIFT 0x6 /* get to the MCC field */
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#define M8260_CPCR_OP_SHIFT 0x0 /* get to the opcode field */
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#define M8260_CPCR_MCN_HDLC 0x0 /* protocol code: HDLC */
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#define M8260_CPCR_MCN_ATM 0xa /* protocol code: ATM */
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#define M8260_CPCR_MCN_ETH 0xc /* protocol code: ETH */
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#define M8260_CPCR_MCN_TRANS 0xf /* protocol code: TRANS */
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#define M8260_CPCR_OP(x) \
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(((x) << M8260_CPCR_OP_SHIFT) & M8260_CPCR_OP_MSK)
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#define M8260_CPCR_SBC(x) \
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(((x) << M8260_CPCR_SBC_SHIFT) & M8260_CPCR_SBC_MSK)
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#define M8260_CPCR_PAGE(x) \
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(((x) << M8260_CPCR_PAGE_SHIFT) & M8260_CPCR_PAGE_MSK)
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#define M8260_CPCR_MCN(x) \
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(((x) << M8260_CPCR_MCN_SHIFT) & M8260_CPCR_MCN_MSK)
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/* CPCR - Sub-block code */
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#define M8260_CPCR_SBC_FCC1 0x10 /* FCC1 channel */
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#define M8260_CPCR_SBC_ATM_FCC1 0x0e /* ATM on FCC1 */
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#define M8260_CPCR_SBC_FCC2 0x11 /* FCC2 channel */
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#define M8260_CPCR_SBC_ATM_FCC2 0x0e /* ATM on FCC2 */
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#define M8260_CPCR_SBC_FCC3 0x12 /* FCC3 channel */
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#define M8260_CPCR_SBC_SCC1 0x04 /* SCC1 channel */
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#define M8260_CPCR_SBC_SCC2 0x05 /* SCC2 channel */
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#define M8260_CPCR_SBC_SCC3 0x06 /* SCC3 channel */
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#define M8260_CPCR_SBC_SCC4 0x07 /* SCC4 channel */
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#define M8260_CPCR_SBC_SMC1 0x08 /* SMC1 channel */
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#define M8260_CPCR_SBC_SMC2 0x09 /* SMC2 channel */
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#define M8260_CPCR_SBC_RAND 0x0e /* RAND channel */
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#define M8260_CPCR_SBC_SPI 0x0a /* SPI */
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#define M8260_CPCR_SBC_I2C 0x0b /* I2C */
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#define M8260_CPCR_SBC_TIMER 0x0f /* TIMER */
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#define M8260_CPCR_SBC_MCC1 0x1c /* MCC1 channel */
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#define M8260_CPCR_SBC_MCC2 0x1d /* MCC2 channel */
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#define M8260_CPCR_SBC_IDMA1 0x14 /* IDMA1 channel */
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#define M8260_CPCR_SBC_IDMA2 0x15 /* IDMA2 channel */
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#define M8260_CPCR_SBC_IDMA3 0x16 /* IDMA3 channel */
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#define M8260_CPCR_SBC_IDMA4 0x17 /* IDMA4 channel */
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/* CPCR - Page code */
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#define M8260_CPCR_PAGE_FCC1 0x04 /* FCC1 channel */
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#define M8260_CPCR_PAGE_FCC2 0x05 /* FCC2 channel */
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#define M8260_CPCR_PAGE_FCC3 0x06 /* FCC3 channel */
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#define M8260_CPCR_PAGE_SCC1 0x00 /* SCC1 channel */
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#define M8260_CPCR_PAGE_SCC2 0x01 /* SCC2 channel */
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#define M8260_CPCR_PAGE_SCC3 0x02 /* SCC3 channel */
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#define M8260_CPCR_PAGE_SCC4 0x03 /* SCC4 channel */
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#define M8260_CPCR_PAGE_SMC1 0x07 /* SMC1 channel */
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#define M8260_CPCR_PAGE_SMC2 0x08 /* SMC2 channel */
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#define M8260_CPCR_PAGE_RAND 0x0a /* RAND channel */
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#define M8260_CPCR_PAGE_SPI 0x09 /* SPI */
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#define M8260_CPCR_PAGE_I2C 0x0a /* I2C */
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#define M8260_CPCR_PAGE_TIMER 0x0a /* TIMER */
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#define M8260_CPCR_PAGE_MCC1 0x07 /* MCC1 channel */
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#define M8260_CPCR_PAGE_MCC2 0x08 /* MCC2 channel */
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#define M8260_CPCR_PAGE_IDMA1 0x07 /* IDMA1 channel */
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#define M8260_CPCR_PAGE_IDMA2 0x08 /* IDMA2 channel */
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#define M8260_CPCR_PAGE_IDMA3 0x09 /* IDMA3 channel */
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#define M8260_CPCR_PAGE_IDMA4 0x0a /* IDMA4 channel */
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/* CPCR - opcodes */
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#define M8260_CPCR_RT_INIT 0x0 /* Init rx and tx */
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#define M8260_CPCR_RX_INIT 0x1 /* init rx only */
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#define M8260_CPCR_TX_INIT 0x2 /* init tx only */
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#define M8260_CPCR_HUNT 0x3 /* rx frame hunt mode */
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#define M8260_CPCR_TX_STOP 0x4 /* stop tx */
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#define M8260_CPCR_TX_GRSTOP 0x5 /* gracefully stop tx */
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#define M8260_CPCR_TX_RESTART 0x6 /* restart tx */
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#define M8260_CPCR_RX_CLOSE 0x7 /* close rx buffer */
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#define M8260_CPCR_SET_GROUP 0x8 /* set group address */
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#define M8260_CPCR_SET_TMR 0x8 /* set timer */
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#define M8260_CPCR_GCI_TMO 0x9 /* gci timeout */
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#define M8260_CPCR_IDMA_START 0x9 /* start idma */
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#define M8260_CPCR_MCC_RX_STOP 0x9 /* stop rx on MCC */
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#define M8260_CPCR_ATM_TX 0xa /* ATM transmit */
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#define M8260_CPCR_BCS_RESET 0xa /* blk chk seq reset */
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#define M8260_CPCR_GCI_ABRT 0xa /* gci abort request */
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#define M8260_CPCR_IDMA_STOP 0xb /* stop idma */
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#define M8260_CPCR_RANDOM 0xc /* random number */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCm8260Cph */
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