135 lines
4.3 KiB
C
135 lines
4.3 KiB
C
/* m8260Brg.h - Motorola MPC8260 Baud Rate Generators header file */
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/* Copyright 1984-1999 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01a,12sep99,ms_ created from m8260Cpm.h, 01d.
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*/
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/*
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* This file contains constants for the Baud Rate Generators (BRGs)
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* in the Motorola MPC8260 PowerQUICC II integrated Communications
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* Processor
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*/
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#ifndef __INCm8260Brgh
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#define __INCm8260Brgh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef M8260ABBREVIATIONS
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#define M8260ABBREVIATIONS
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#ifdef _ASMLANGUAGE
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#define CAST(x)
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#else /* _ASMLANGUAGE */
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typedef volatile UCHAR VCHAR; /* shorthand for volatile UCHAR */
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typedef volatile INT32 VINT32; /* volatile unsigned word */
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typedef volatile INT16 VINT16; /* volatile unsigned halfword */
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typedef volatile INT8 VINT8; /* volatile unsigned byte */
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typedef volatile UINT32 VUINT32; /* volatile unsigned word */
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typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
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typedef volatile UINT8 VUINT8; /* volatile unsigned byte */
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#define CAST(x) (x)
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#endif /* _ASMLANGUAGE */
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#endif /* M8260ABBREVIATIONS */
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#ifndef M8260_32_WR
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#define M8260_32_WR(addr, value) (* ((UINT32 *)(addr)) = ((UINT32) (value)))
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#endif
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#ifndef M8260_16_WR
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#define M8260_16_WR(addr, value) (* ((UINT16 *)(addr)) = ((UINT16) (value)))
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#endif
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#ifndef M8260_8_WR
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#define M8260_8_WR(addr, value) (* ((UINT8 *)(addr)) = ((UINT8) (value)))
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#endif
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#ifndef M8260_32_RD
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#define M8260_32_RD(addr, value) ((value) = (* (UINT32 *) ((UINT32 *)(addr))))
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#endif
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#ifndef M8260_16_RD
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#define M8260_16_RD(addr, value) ((value) = (* (UINT16 *) ((UINT16 *)(addr))))
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#endif
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#ifndef M8260_8_RD
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#define M8260_8_RD(addr, value) ((value) = (* (UINT8 *) ((UINT8 *)(addr))))
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#endif
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#ifndef M8260_NTH_REG_WR_32
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#define M8260_NTH_REG_WR_32(regVal, regBase, offsetNext, n) \
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{ \
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VINT32 *pReg = (VINT32 *) \
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(immrVal + \
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regBase + \
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((n-1) * offsetNext)); \
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M8260_32_WR(pReg, regVal); \
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}
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#endif
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#define M8260_BRGC_WR(value, brgc) \
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M8260_NTH_REG_WR_32(value, \
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M8260_BRGC_BASE, \
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M8260_BRGC_OFFSET_NEXT_BRGC, \
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brgc)
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/*
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* MPC8260 internal register/memory map (section 17 of prelim. spec)
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* note that these are offsets from the value stored in the IMMR
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* register. Also note that in the MPC8260, the IMMR is not a special
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* purpose register, but it is memory mapped.
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*/
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/* Baud Rate Generators */
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#define M8260_BRGC_BASE 0x000119F0
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#define M8260_BRGC_OFFSET_NEXT_BRGC 0x00000004
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#define M8260_BRGC_RD(regVal, brg) \
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{ \
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VINT32 *pReg = (VINT32 *) \
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(immrVal + \
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M8260_BRGC_BASE + \
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((brg - 1) * M8260_BRGC_OFFSET_NEXT_BRGC)); \
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M8260_32_RD(pReg, regVal); \
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}
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#define M8260_BRGC_SET_BITS(bitmap) \
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{ \
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UINT32 regVal; \
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VINT32 *pReg = (VINT32 *) \
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(immrVal + \
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M8260_BRGC_BASE + \
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(scc * M8260_BRGC_OFFSET_NEXT_BRGC)); \
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M8260_32_RD(pReg, regVal); \
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M8260_32_WR(pReg, (regVal | bitmap)); \
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}
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/* macros used in the configuration registers */
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#define M8260_BRGC_CD_MASK 0x00001FFE /* clock divider mask */
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#define M8260_BRGC_CD_SHIFT 0x1 /* to shift CD into position */
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#define M8260_BRGC_RST 0x00020000 /* Reset BRG */
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#define M8260_BRGC_EN 0x00010000 /* Enable BRG count */
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#define M8260_BRGC_EXTC_BRGCLK 0x0 /* clock comes from BRGCKL */
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#define M8260_BRGC_EXTC_CLK3_9 0x1 /* clock comes from pin 3 or 9 */
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#define M8260_BRGC_EXTC_CLK5_15 0x2 /* clock comes from pin 5 or 15 */
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#define M8260_BRGC_EXTC_MASK 0x0000C000 /* External Clock Source Mask */
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#define M8260_BRGC_EXTC_SHIFT 0xE /* shift EXTC 14 bits to position */
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#define M8260_BRGC_ATB 0x00002000 /* 1 = Autobaud on Rx */
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/* 0 = normal operation */
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#define M8260_BRGC_DIV16 0x00000001 /* BRG Clock divide by 16 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCm8260Brgh */
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