218 lines
7.5 KiB
C
218 lines
7.5 KiB
C
/* coldfireSio.h - Motorola ColdFire internal UART header file */
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/* Copyright 1984-1998 Wind River Systems, Inc. */
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/*
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modification history
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--------------------
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01b,09jul98,gls Adapted to WRS coding conventions
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01a,01may98,mem created, based on m5204Sio.h.
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*/
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/*
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This file contains constants and defines for the UART contained in several
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of the Motorola ColdFire ports.
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*/
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#ifndef __INCcoldfireSioh
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#define __INCcoldfireSioh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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#include "sioLib.h"
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typedef struct
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{
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SIO_DRV_FUNCS * pDrvFuncs; /* Driver functions */
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/* CallBacks */
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STATUS (*getTxChar)();
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STATUS (*putRcvChar)();
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void * getTxArg;
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void * putRcvArg;
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UINT clkRate; /* system clock rate */
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UINT16 mode; /* SIO_MODE */
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unsigned char intVec;
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int options;
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int intEnable;
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UINT baudRate;
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UCHAR oprCopy;
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UCHAR acrCopy;
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UCHAR imrCopy;
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volatile UCHAR *mr; /* UART mode register */
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volatile UCHAR *sr; /* UART status register */
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volatile UCHAR *csr; /* UART clock select register */
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volatile UCHAR *cr; /* UART command register */
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volatile UCHAR *rb; /* UART receive buffer register */
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volatile UCHAR *tb; /* UART transmit buffer register */
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volatile UCHAR *ipcr; /* UART input port change register */
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volatile UCHAR *acr; /* UART auxiliary control register */
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volatile UCHAR *isr; /* UART interrupt status register */
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volatile UCHAR *imr; /* UART interrupt mask register */
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volatile UCHAR *bg1; /* UART baud generator prescale register 1 */
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volatile UCHAR *bg2; /* UART baud generator prescale register 2 */
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volatile UCHAR *ivr; /* UART interrupt vector register */
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volatile UCHAR *ip; /* UART input port register */
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volatile UCHAR *op1; /* UART output port set cmd */
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volatile UCHAR *op2; /* UART output port reset cmd */
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} COLDFIRE_CHAN;
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#endif /* _ASMLANGUAGE */
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/* register bit definitions */
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/* MR1 - mode register 1 */
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#define COLDFIRE_UART_MR1_BC0 (1 << 0) /* bits per char 0 */
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#define COLDFIRE_UART_MR1_BC1 (1 << 1) /* bits per char 1 */
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#define COLDFIRE_UART_MR1_PT (1 << 2) /* parity type */
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#define COLDFIRE_UART_MR1_PM0 (1 << 3) /* parity mode 0 */
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#define COLDFIRE_UART_MR1_PM1 (1 << 4) /* parity mode 1 */
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#define COLDFIRE_UART_MR1_ERR (1 << 5) /* error mode */
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#define COLDFIRE_UART_MR1_RX_IRQ (1 << 6) /* receiver interrupt select */
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#define COLDFIRE_UART_MR1_RX_RTS (1 << 7) /* Rx RTS control */
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/* Some common modes */
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#define COLDFIRE_UART_MR1_BITS_CHAR_5 0
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#define COLDFIRE_UART_MR1_BITS_CHAR_6 COLDFIRE_UART_MR1_BC0
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#define COLDFIRE_UART_MR1_BITS_CHAR_7 COLDFIRE_UART_MR1_BC1
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#define COLDFIRE_UART_MR1_BITS_CHAR_8 (COLDFIRE_UART_MR1_BC0 \
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| COLDFIRE_UART_MR1_BC1)
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#define COLDFIRE_UART_MR1_NO_PARITY (COLDFIRE_UART_MR1_PM1)
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#define COLDFIRE_UART_MR1_PAR_MODE_MULTI (COLDFIRE_UART_MR1_PM0 \
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| COLDFIRE_UART_MR1_PM1)
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#define COLDFIRE_UART_MR1_EVEN_PARITY 0
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#define COLDFIRE_UART_MR1_ODD_PARITY COLDFIRE_UART_MR1_PT
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/* MR2 - mode register 2 */
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#define COLDFIRE_UART_MR2_SB0 (1 << 0) /* stop bit control 0 */
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#define COLDFIRE_UART_MR2_SB1 (1 << 1) /* stop bit control 1 */
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#define COLDFIRE_UART_MR2_SB2 (1 << 2) /* stop bit control 2 */
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#define COLDFIRE_UART_MR2_SB3 (1 << 3) /* stop bit control 3 */
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#define COLDFIRE_UART_MR2_TX_CTS (1 << 4) /* Tx CTS control */
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#define COLDFIRE_UART_MR2_TX_RTS (1 << 5) /* Tx RTS control */
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#define COLDFIRE_UART_MR2_CM0 (1 << 6) /* channel mode 0 */
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#define COLDFIRE_UART_MR2_CM1 (1 << 7) /* channel mode 1 */
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/* Some common bit lengths */
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#define COLDFIRE_UART_MR2_STOP_BITS_1 (COLDFIRE_UART_MR2_SB0 \
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| COLDFIRE_UART_MR2_SB1 \
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| COLDFIRE_UART_MR2_SB2)
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#define COLDFIRE_UART_MR2_STOP_BITS_2 (COLDFIRE_UART_MR2_SB0 \
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| COLDFIRE_UART_MR2_SB1 \
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| COLDFIRE_UART_MR2_SB2 \
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| COLDFIRE_UART_MR2_SB3)
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/* SR - status register */
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#define COLDFIRE_UART_SR_RXRDY (1 << 0) /* Rx ready */
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#define COLDFIRE_UART_SR_FFULL (1 << 1) /* FIFO full */
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#define COLDFIRE_UART_SR_TXRDY (1 << 2) /* Tx ready */
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#define COLDFIRE_UART_SR_TXEMP (1 << 3) /* Tx empty */
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#define COLDFIRE_UART_SR_OE (1 << 4) /* overrun error */
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#define COLDFIRE_UART_SR_PE (1 << 5) /* parity error */
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#define COLDFIRE_UART_SR_FE (1 << 6) /* framing error */
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#define COLDFIRE_UART_SR_RB (1 << 7) /* received break */
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/* CSR - clock select register */
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#define COLDFIRE_UART_CSR_TCS0 (1 << 0) /* Tx clock select 0 */
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#define COLDFIRE_UART_CSR_TCS1 (1 << 1) /* Tx clock select 1 */
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#define COLDFIRE_UART_CSR_TCS2 (1 << 2) /* Tx clock select 2 */
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#define COLDFIRE_UART_CSR_TCS3 (1 << 3) /* Tx clock select 3 */
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#define COLDFIRE_UART_CSR_RCS0 (1 << 4) /* Rx clock select 0 */
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#define COLDFIRE_UART_CSR_RCS1 (1 << 5) /* Rx clock select 1 */
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#define COLDFIRE_UART_CSR_RCS2 (1 << 6) /* Rx clock select 2 */
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#define COLDFIRE_UART_CSR_RCS3 (1 << 7) /* Rx clock select 3 */
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#define COLDFIRE_UART_CSR_TIMER_TX (COLDFIRE_UART_CSR_TCS0 \
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| COLDFIRE_UART_CSR_TCS2 \
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| COLDFIRE_UART_CSR_TCS3)
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#define COLDFIRE_UART_CSR_TIMER_RX (COLDFIRE_UART_CSR_RCS0 \
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| COLDFIRE_UART_CSR_RCS2 \
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| COLDFIRE_UART_CSR_RCS3)
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/* CR - command register */
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#define COLDFIRE_UART_CR_RC0 (1 << 0) /* receiver control bit 0 */
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#define COLDFIRE_UART_CR_RC1 (1 << 1) /* receiver control bit 1 */
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#define COLDFIRE_UART_CR_TC0 (1 << 2) /* transmitter control bit 0 */
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#define COLDFIRE_UART_CR_TC1 (1 << 3) /* transmitter control bit 1 */
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#define COLDFIRE_UART_CR_MISC0 (1 << 4) /* misc control bit 0 */
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#define COLDFIRE_UART_CR_MISC1 (1 << 5) /* misc control bit 1 */
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#define COLDFIRE_UART_CR_MISC2 (1 << 6) /* misc control bit 2 */
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/* Some common commands */
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#define COLDFIRE_UART_CR_TX_ENABLE (COLDFIRE_UART_CR_TC0)
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#define COLDFIRE_UART_CR_TX_DISABLE (COLDFIRE_UART_CR_TC1)
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#define COLDFIRE_UART_CR_RX_ENABLE (COLDFIRE_UART_CR_RC0)
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#define COLDFIRE_UART_CR_RX_DISABLE (COLDFIRE_UART_CR_RC1)
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#define COLDFIRE_UART_CR_RESET_MODE_PTR (COLDFIRE_UART_CR_MISC0)
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#define COLDFIRE_UART_CR_RESET_RX (COLDFIRE_UART_CR_MISC1)
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#define COLDFIRE_UART_CR_RESET_TX (COLDFIRE_UART_CR_MISC1 \
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| COLDFIRE_UART_CR_MISC0)
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#define COLDFIRE_UART_CR_RESET_ERR (COLDFIRE_UART_CR_MISC2)
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#define COLDFIRE_UART_CR_RESET_BRK (COLDFIRE_UART_CR_MISC2 \
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| COLDFIRE_UART_CR_MISC0)
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/* ACR - auxiliary control register */
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#define COLDFIRE_UART_ACR_IEC (1 << 0) /* input enable control */
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/* IMR - interrupt mask register */
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#define COLDFIRE_UART_IMR_TXRDY (1 << 0) /* transmitter ready */
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#define COLDFIRE_UART_IMR_RXRDY (1 << 1) /* receiver ready */
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#define COLDFIRE_UART_IMR_DB (1 << 2) /* delta break */
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#define COLDFIRE_UART_IMR_COS (1 << 7) /* change of CTS state */
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/* ISR - interrupt status register */
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#define COLDFIRE_UART_ISR_TXRDY (1 << 0) /* transmitter ready */
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#define COLDFIRE_UART_ISR_RXRDY (1 << 1) /* receiver ready */
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#define COLDFIRE_UART_ISR_DB (1 << 2) /* delta break */
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#define COLDFIRE_UART_ISR_COS (1 << 7) /* change of CTS state */
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/* IP - input port register */
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#define COLDFIRE_UART_IP_CTS (1 << 0) /* current CTS state */
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/* OP1 - output set register */
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#define COLDFIRE_UART_OP1_RTS (1 << 0) /* set RTS */
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/* OP2 - output reset register */
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#define COLDFIRE_UART_OP2_RTS (1 << 0) /* clear RTS */
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/* function declarations */
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#if defined(__STDC__) || defined(__cplusplus)
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IMPORT void coldfireDevInit (COLDFIRE_CHAN *pChan);
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IMPORT void coldfireDevInit2 (COLDFIRE_CHAN *pChan);
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IMPORT void coldfireInt (COLDFIRE_CHAN *pChan);
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#else /* __STDC__ */
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IMPORT void coldfireDevInit ();
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IMPORT void coldfireDevInit2 ();
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IMPORT void coldfireInt ();
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#endif /* __STDC__ */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCcoldfireSioh */
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