diff --git a/common/inc/tx_api.h b/common/inc/tx_api.h index bed139cd..c79c635c 100644 --- a/common/inc/tx_api.h +++ b/common/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE C */ -/* 6.1.5 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -66,6 +66,9 @@ /* add option to remove FileX */ /* pointer, */ /* resulting in version 6.1.5 */ +/* 04-02-2021 Scott Larson Modified comment(s), and */ +/* update patch number, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -98,7 +101,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 1 -#define THREADX_PATCH_VERSION 5 +#define THREADX_PATCH_VERSION 6 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/common/src/tx_mutex_priority_change.c b/common/src/tx_mutex_priority_change.c index c5f58869..809d0a21 100644 --- a/common/src/tx_mutex_priority_change.c +++ b/common/src/tx_mutex_priority_change.c @@ -35,7 +35,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_mutex_priority_change PORTABLE C */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -70,14 +70,18 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 05-19-2020 William E. Lamie Initial Version 6.0 */ -/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ /* change thread state from */ /* TX_SUSPENDED to */ /* TX_PRIORITY_CHANGE before */ /* calling */ /* _tx_thread_system_suspend, */ /* resulting in version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, fixed */ +/* mapping current thread's */ +/* priority rather than next, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ VOID _tx_mutex_priority_change(TX_THREAD *thread_ptr, UINT new_priority) @@ -308,15 +312,15 @@ UINT map_index; #if TX_MAX_PRIORITIES > 32 /* Calculate the index into the bit map array. */ - map_index = (next_execute_ptr -> tx_thread_priority)/ ((UINT) 32); + map_index = (thread_ptr -> tx_thread_priority)/ ((UINT) 32); /* Set the active bit to remember that the preempt map has something set. */ - TX_DIV32_BIT_SET(next_execute_ptr -> tx_thread_priority, priority_bit) + TX_DIV32_BIT_SET(thread_ptr -> tx_thread_priority, priority_bit) _tx_thread_preempted_map_active = _tx_thread_preempted_map_active | priority_bit; #endif /* Remember that this thread was preempted by a thread above the thread's threshold. */ - TX_MOD32_BIT_SET(next_execute_ptr -> tx_thread_priority, priority_bit) + TX_MOD32_BIT_SET(thread_ptr -> tx_thread_priority, priority_bit) _tx_thread_preempted_maps[MAP_INDEX] = _tx_thread_preempted_maps[MAP_INDEX] | priority_bit; } #endif diff --git a/common_modules/module_manager/inc/txm_module_manager_dispatch.h b/common_modules/module_manager/inc/txm_module_manager_dispatch.h index 42aa1bab..644cc1c9 100644 --- a/common_modules/module_manager/inc/txm_module_manager_dispatch.h +++ b/common_modules/module_manager/inc/txm_module_manager_dispatch.h @@ -68,6 +68,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], extra_parameters[2])) return(TXM_MODULE_INVALID_MEMORY); } @@ -131,6 +134,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -179,6 +185,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -218,6 +227,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -311,6 +323,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(VOID *))) return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); } return_value = (ALIGN_TYPE) _txe_byte_allocate( @@ -342,6 +357,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], extra_parameters[1])) return(TXM_MODULE_INVALID_MEMORY); } @@ -404,6 +422,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -455,6 +476,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[6]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -509,6 +533,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -668,6 +695,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); } return_value = (ALIGN_TYPE) _txe_event_flags_get( @@ -701,6 +731,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -745,6 +778,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -784,6 +820,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -886,6 +925,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); } return_value = (ALIGN_TYPE) _txe_mutex_create( @@ -967,6 +1009,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1017,6 +1062,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1066,6 +1114,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1151,6 +1202,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], extra_parameters[2])) return(TXM_MODULE_INVALID_MEMORY); } @@ -1264,6 +1318,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1314,6 +1371,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[5]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1363,6 +1423,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1551,6 +1614,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); } return_value = (ALIGN_TYPE) _txe_semaphore_create( @@ -1631,6 +1697,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1675,6 +1744,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1714,6 +1786,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -1840,6 +1915,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[9]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[2], extra_parameters[3])) return(TXM_MODULE_INVALID_MEMORY); @@ -1977,6 +2055,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[7]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(UINT))) return(TXM_MODULE_INVALID_MEMORY); @@ -2056,6 +2137,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[9]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -2126,6 +2210,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[9]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -2535,6 +2622,9 @@ VOID (*expiration_function)(ULONG); if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[6]))) + return(TXM_MODULE_INVALID_MEMORY); } /* Is it a disable request? */ @@ -2646,6 +2736,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(CHAR *))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(UINT))) return(TXM_MODULE_INVALID_MEMORY); @@ -2691,6 +2784,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[4]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -2735,6 +2831,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, param_1, sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[0], sizeof(ULONG))) return(TXM_MODULE_INVALID_MEMORY); @@ -2890,6 +2989,12 @@ static ALIGN_TYPE _txm_module_manager_tx_trace_user_event_insert_dispatch(TXM_MO ALIGN_TYPE return_value; + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[3]))) + return(TXM_MODULE_INVALID_MEMORY); + } + return_value = (ALIGN_TYPE) _tx_trace_user_event_insert( (ULONG) param_0, (ULONG) param_1, @@ -3015,6 +3120,9 @@ ALIGN_TYPE return_value; if (!TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, param_1)) return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, (ALIGN_TYPE)extra_parameters, sizeof(ALIGN_TYPE[2]))) + return(TXM_MODULE_INVALID_MEMORY); + if (!TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, extra_parameters[1], sizeof(VOID *))) return(TXM_MODULE_INVALID_MEMORY); } diff --git a/common_modules/module_manager/inc/txm_module_manager_util.h b/common_modules/module_manager/inc/txm_module_manager_util.h index 1eef6440..b07868a2 100644 --- a/common_modules/module_manager/inc/txm_module_manager_util.h +++ b/common_modules/module_manager/inc/txm_module_manager_util.h @@ -10,37 +10,40 @@ /**************************************************************************/ -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** Module Manager */ -/** */ -/**************************************************************************/ -/**************************************************************************/ +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ -/**************************************************************************/ -/* */ -/* COMPONENT DEFINITION RELEASE */ -/* */ -/* txm_module_manager_util.h PORTABLE C */ -/* 6.1 */ +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* txm_module_manager_util.h PORTABLE C */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ /* */ -/* DESCRIPTION */ -/* */ -/* This file declares prototypes of utility functions used by the */ -/* module manager. */ -/* */ -/* RELEASE HISTORY */ -/* */ +/* DESCRIPTION */ +/* */ +/* This file declares prototypes of utility functions used by the */ +/* module manager. */ +/* */ +/* RELEASE HISTORY */ +/* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s) and */ +/* optimized object checks, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -53,15 +56,18 @@ (!(TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size))) #define TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size) \ - (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_code_start) && \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ + ((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_code_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_code_end + 1))) #define TXM_MODULE_MANAGER_CHECK_OUTSIDE_CODE(module_instance, obj_ptr, obj_size) \ (!(TXM_MODULE_MANAGER_CHECK_INSIDE_CODE(module_instance, obj_ptr, obj_size))) +/* Add sizeof(TXM_MODULE_ALLOCATED_OBJECT) to pool start because the object can't exist before that. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) \ ((_txm_module_manager_object_pool_created == TX_TRUE) && \ - (((obj_ptr) >= (ALIGN_TYPE) _txm_module_manager_object_pool.tx_byte_pool_start) && \ + ((obj_ptr) < ((obj_ptr) + (obj_size))) && \ + (((obj_ptr) >= ((ALIGN_TYPE) _txm_module_manager_object_pool.tx_byte_pool_start + sizeof(TXM_MODULE_ALLOCATED_OBJECT))) && \ (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (_txm_module_manager_object_pool.tx_byte_pool_start + _txm_module_manager_object_pool.tx_byte_pool_size)))) /* Define macros for module. */ @@ -84,29 +90,29 @@ /* Buffers we read from can be in RW/RO/Shared areas. */ #define TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_READ(module_instance, buffer_ptr, buffer_size) \ - (((void *) (buffer_ptr) == TX_NULL) || \ - (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, buffer_ptr, buffer_size))) + ((TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, buffer_ptr, buffer_size)) || \ + ((void *) (buffer_ptr) == TX_NULL)) /* Buffers we write to can only be in RW/Shared areas. */ #define TXM_MODULE_MANAGER_PARAM_CHECK_BUFFER_WRITE(module_instance, buffer_ptr, buffer_size) \ - (((void *) (buffer_ptr) == TX_NULL) || \ - (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, buffer_ptr, buffer_size))) + ((TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE_DATA(module_instance, buffer_ptr, buffer_size)) || \ + ((void *) (buffer_ptr) == TX_NULL)) /* Kernel objects should be outside the module at the very least. */ #define TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, obj_ptr, obj_size) \ - (((void *) (obj_ptr) == TX_NULL) || \ - (TXM_MODULE_MANAGER_ENSURE_OUTSIDE_MODULE(module_instance, obj_ptr, obj_size))) + ((TXM_MODULE_MANAGER_ENSURE_OUTSIDE_MODULE(module_instance, obj_ptr, obj_size)) || \ + ((void *) (obj_ptr) == TX_NULL)) /* When creating an object, the object must be inside the object pool. */ #define TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_CREATION(module_instance, obj_ptr, obj_size) \ - (((void *) (obj_ptr) == TX_NULL) || \ - (TXM_MODULE_MANAGER_ENSURE_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) && \ - (_txm_module_manager_object_size_check(obj_ptr, obj_size) == TX_SUCCESS))) + ((TXM_MODULE_MANAGER_ENSURE_INSIDE_OBJ_POOL(module_instance, obj_ptr, obj_size) && \ + (_txm_module_manager_object_size_check(obj_ptr, obj_size) == TX_SUCCESS)) || \ + ((void *) (obj_ptr) == TX_NULL)) /* Strings we dereference can be in RW/RO/Shared areas. */ #define TXM_MODULE_MANAGER_PARAM_CHECK_DEREFERENCE_STRING(module_instance, string_ptr) \ - (((void *) (string_ptr) == TX_NULL) || \ - (TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, string_ptr, 1))) + ((TXM_MODULE_MANAGER_ENSURE_INSIDE_MODULE(module_instance, string_ptr, 1)) || \ + ((void *) (string_ptr) == TX_NULL)) #define TXM_MODULE_MANAGER_UTIL_MAX_VALUE_OF_TYPE_UNSIGNED(type) ((1ULL << (sizeof(type) * 8)) - 1) diff --git a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c index 355de996..a0929621 100644 --- a/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c +++ b/common_modules/module_manager/src/txm_module_manager_kernel_dispatch.c @@ -41,7 +41,7 @@ /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_kernel_dispatch PORTABLE C */ -/* 6.1.3 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -50,6 +50,8 @@ /* */ /* This function dispatches the module's kernel request based upon the */ /* ID and parameters specified in the request. */ +/* To disallow modules to use specific ThreadX services, define */ +/* TXM_***_CALL_NOT_USED (see #ifndefs surrounding each case). */ /* */ /* INPUT */ /* */ @@ -83,6 +85,10 @@ /* 12-31-2020 Scott Larson Modified comment(s), added */ /* port-specific dispatch, */ /* resulting in version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comment(s), */ +/* added optional defines to */ +/* remove unneeded functions, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ ALIGN_TYPE _txm_module_manager_kernel_dispatch(ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) @@ -104,581 +110,773 @@ TXM_MODULE_INSTANCE *module_instance; switch (kernel_request) { + #ifndef TXM_BLOCK_ALLOCATE_CALL_NOT_USED case TXM_BLOCK_ALLOCATE_CALL: { return_value = _txm_module_manager_tx_block_allocate_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_BLOCK_POOL_CREATE_CALL_NOT_USED case TXM_BLOCK_POOL_CREATE_CALL: { return_value = _txm_module_manager_tx_block_pool_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BLOCK_POOL_DELETE_CALL_NOT_USED case TXM_BLOCK_POOL_DELETE_CALL: { return_value = _txm_module_manager_tx_block_pool_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_BLOCK_POOL_INFO_GET_CALL_NOT_USED case TXM_BLOCK_POOL_INFO_GET_CALL: { return_value = _txm_module_manager_tx_block_pool_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BLOCK_POOL_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_BLOCK_POOL_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_block_pool_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_BLOCK_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_block_pool_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BLOCK_POOL_PRIORITIZE_CALL_NOT_USED case TXM_BLOCK_POOL_PRIORITIZE_CALL: { return_value = _txm_module_manager_tx_block_pool_prioritize_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_BLOCK_RELEASE_CALL_NOT_USED case TXM_BLOCK_RELEASE_CALL: { return_value = _txm_module_manager_tx_block_release_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_BYTE_ALLOCATE_CALL_NOT_USED case TXM_BYTE_ALLOCATE_CALL: { return_value = _txm_module_manager_tx_byte_allocate_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BYTE_POOL_CREATE_CALL_NOT_USED case TXM_BYTE_POOL_CREATE_CALL: { return_value = _txm_module_manager_tx_byte_pool_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BYTE_POOL_DELETE_CALL_NOT_USED case TXM_BYTE_POOL_DELETE_CALL: { return_value = _txm_module_manager_tx_byte_pool_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_BYTE_POOL_INFO_GET_CALL_NOT_USED case TXM_BYTE_POOL_INFO_GET_CALL: { return_value = _txm_module_manager_tx_byte_pool_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BYTE_POOL_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_BYTE_POOL_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_byte_pool_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_BYTE_POOL_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_byte_pool_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_BYTE_POOL_PRIORITIZE_CALL_NOT_USED case TXM_BYTE_POOL_PRIORITIZE_CALL: { return_value = _txm_module_manager_tx_byte_pool_prioritize_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_BYTE_RELEASE_CALL_NOT_USED case TXM_BYTE_RELEASE_CALL: { return_value = _txm_module_manager_tx_byte_release_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_EVENT_FLAGS_CREATE_CALL_NOT_USED case TXM_EVENT_FLAGS_CREATE_CALL: { return_value = _txm_module_manager_tx_event_flags_create_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_EVENT_FLAGS_DELETE_CALL_NOT_USED case TXM_EVENT_FLAGS_DELETE_CALL: { return_value = _txm_module_manager_tx_event_flags_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_EVENT_FLAGS_GET_CALL_NOT_USED case TXM_EVENT_FLAGS_GET_CALL: { return_value = _txm_module_manager_tx_event_flags_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_EVENT_FLAGS_INFO_GET_CALL_NOT_USED case TXM_EVENT_FLAGS_INFO_GET_CALL: { return_value = _txm_module_manager_tx_event_flags_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_EVENT_FLAGS_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_EVENT_FLAGS_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_event_flags_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_EVENT_FLAGS_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_event_flags_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_EVENT_FLAGS_SET_CALL_NOT_USED case TXM_EVENT_FLAGS_SET_CALL: { return_value = _txm_module_manager_tx_event_flags_set_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_EVENT_FLAGS_SET_NOTIFY_CALL_NOT_USED case TXM_EVENT_FLAGS_SET_NOTIFY_CALL: { return_value = _txm_module_manager_tx_event_flags_set_notify_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_MUTEX_CREATE_CALL_NOT_USED case TXM_MUTEX_CREATE_CALL: { return_value = _txm_module_manager_tx_mutex_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_MUTEX_DELETE_CALL_NOT_USED case TXM_MUTEX_DELETE_CALL: { return_value = _txm_module_manager_tx_mutex_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_MUTEX_GET_CALL_NOT_USED case TXM_MUTEX_GET_CALL: { return_value = _txm_module_manager_tx_mutex_get_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_MUTEX_INFO_GET_CALL_NOT_USED case TXM_MUTEX_INFO_GET_CALL: { return_value = _txm_module_manager_tx_mutex_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_MUTEX_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_MUTEX_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_mutex_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_MUTEX_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_mutex_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_MUTEX_PRIORITIZE_CALL_NOT_USED case TXM_MUTEX_PRIORITIZE_CALL: { return_value = _txm_module_manager_tx_mutex_prioritize_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_MUTEX_PUT_CALL_NOT_USED case TXM_MUTEX_PUT_CALL: { return_value = _txm_module_manager_tx_mutex_put_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_QUEUE_CREATE_CALL_NOT_USED case TXM_QUEUE_CREATE_CALL: { return_value = _txm_module_manager_tx_queue_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_QUEUE_DELETE_CALL_NOT_USED case TXM_QUEUE_DELETE_CALL: { return_value = _txm_module_manager_tx_queue_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_QUEUE_FLUSH_CALL_NOT_USED case TXM_QUEUE_FLUSH_CALL: { return_value = _txm_module_manager_tx_queue_flush_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_QUEUE_FRONT_SEND_CALL_NOT_USED case TXM_QUEUE_FRONT_SEND_CALL: { return_value = _txm_module_manager_tx_queue_front_send_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_QUEUE_INFO_GET_CALL_NOT_USED case TXM_QUEUE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_queue_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_QUEUE_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_QUEUE_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_queue_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_QUEUE_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_queue_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_QUEUE_PRIORITIZE_CALL_NOT_USED case TXM_QUEUE_PRIORITIZE_CALL: { return_value = _txm_module_manager_tx_queue_prioritize_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_QUEUE_RECEIVE_CALL_NOT_USED case TXM_QUEUE_RECEIVE_CALL: { return_value = _txm_module_manager_tx_queue_receive_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_QUEUE_SEND_CALL_NOT_USED case TXM_QUEUE_SEND_CALL: { return_value = _txm_module_manager_tx_queue_send_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_QUEUE_SEND_NOTIFY_CALL_NOT_USED case TXM_QUEUE_SEND_NOTIFY_CALL: { return_value = _txm_module_manager_tx_queue_send_notify_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_SEMAPHORE_CEILING_PUT_CALL_NOT_USED case TXM_SEMAPHORE_CEILING_PUT_CALL: { return_value = _txm_module_manager_tx_semaphore_ceiling_put_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_SEMAPHORE_CREATE_CALL_NOT_USED case TXM_SEMAPHORE_CREATE_CALL: { return_value = _txm_module_manager_tx_semaphore_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_SEMAPHORE_DELETE_CALL_NOT_USED case TXM_SEMAPHORE_DELETE_CALL: { return_value = _txm_module_manager_tx_semaphore_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_SEMAPHORE_GET_CALL_NOT_USED case TXM_SEMAPHORE_GET_CALL: { return_value = _txm_module_manager_tx_semaphore_get_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_SEMAPHORE_INFO_GET_CALL_NOT_USED case TXM_SEMAPHORE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_semaphore_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_SEMAPHORE_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_SEMAPHORE_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_semaphore_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_SEMAPHORE_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_semaphore_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_SEMAPHORE_PRIORITIZE_CALL_NOT_USED case TXM_SEMAPHORE_PRIORITIZE_CALL: { return_value = _txm_module_manager_tx_semaphore_prioritize_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_SEMAPHORE_PUT_CALL_NOT_USED case TXM_SEMAPHORE_PUT_CALL: { return_value = _txm_module_manager_tx_semaphore_put_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_SEMAPHORE_PUT_NOTIFY_CALL_NOT_USED case TXM_SEMAPHORE_PUT_NOTIFY_CALL: { return_value = _txm_module_manager_tx_semaphore_put_notify_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_THREAD_CREATE_CALL_NOT_USED case TXM_THREAD_CREATE_CALL: { return_value = _txm_module_manager_tx_thread_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_THREAD_DELETE_CALL_NOT_USED case TXM_THREAD_DELETE_CALL: { return_value = _txm_module_manager_tx_thread_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_ENTRY_EXIT_NOTIFY_CALL_NOT_USED case TXM_THREAD_ENTRY_EXIT_NOTIFY_CALL: { return_value = _txm_module_manager_tx_thread_entry_exit_notify_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_THREAD_IDENTIFY_CALL_NOT_USED case TXM_THREAD_IDENTIFY_CALL: { return_value = _txm_module_manager_tx_thread_identify_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_THREAD_INFO_GET_CALL_NOT_USED case TXM_THREAD_INFO_GET_CALL: { return_value = _txm_module_manager_tx_thread_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_THREAD_INTERRUPT_CONTROL_CALL_NOT_USED case TXM_THREAD_INTERRUPT_CONTROL_CALL: { return_value = _txm_module_manager_tx_thread_interrupt_control_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_THREAD_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_thread_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_THREAD_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_THREAD_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_thread_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_THREAD_PREEMPTION_CHANGE_CALL_NOT_USED case TXM_THREAD_PREEMPTION_CHANGE_CALL: { return_value = _txm_module_manager_tx_thread_preemption_change_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_THREAD_PRIORITY_CHANGE_CALL_NOT_USED case TXM_THREAD_PRIORITY_CHANGE_CALL: { return_value = _txm_module_manager_tx_thread_priority_change_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_THREAD_RELINQUISH_CALL_NOT_USED case TXM_THREAD_RELINQUISH_CALL: { return_value = _txm_module_manager_tx_thread_relinquish_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_THREAD_RESET_CALL_NOT_USED case TXM_THREAD_RESET_CALL: { return_value = _txm_module_manager_tx_thread_reset_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_RESUME_CALL_NOT_USED case TXM_THREAD_RESUME_CALL: { return_value = _txm_module_manager_tx_thread_resume_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_SLEEP_CALL_NOT_USED case TXM_THREAD_SLEEP_CALL: { return_value = _txm_module_manager_tx_thread_sleep_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_STACK_ERROR_NOTIFY_CALL_NOT_USED case TXM_THREAD_STACK_ERROR_NOTIFY_CALL: { return_value = _txm_module_manager_tx_thread_stack_error_notify_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_SUSPEND_CALL_NOT_USED case TXM_THREAD_SUSPEND_CALL: { return_value = _txm_module_manager_tx_thread_suspend_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_SYSTEM_SUSPEND_CALL_NOT_USED case TXM_THREAD_SYSTEM_SUSPEND_CALL: { return_value = _txm_module_manager_tx_thread_system_suspend_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_TERMINATE_CALL_NOT_USED case TXM_THREAD_TERMINATE_CALL: { return_value = _txm_module_manager_tx_thread_terminate_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_THREAD_TIME_SLICE_CHANGE_CALL_NOT_USED case TXM_THREAD_TIME_SLICE_CHANGE_CALL: { return_value = _txm_module_manager_tx_thread_time_slice_change_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_THREAD_WAIT_ABORT_CALL_NOT_USED case TXM_THREAD_WAIT_ABORT_CALL: { return_value = _txm_module_manager_tx_thread_wait_abort_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TIME_GET_CALL_NOT_USED case TXM_TIME_GET_CALL: { return_value = _txm_module_manager_tx_time_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_TIME_SET_CALL_NOT_USED case TXM_TIME_SET_CALL: { return_value = _txm_module_manager_tx_time_set_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TIMER_ACTIVATE_CALL_NOT_USED case TXM_TIMER_ACTIVATE_CALL: { return_value = _txm_module_manager_tx_timer_activate_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TIMER_CHANGE_CALL_NOT_USED case TXM_TIMER_CHANGE_CALL: { return_value = _txm_module_manager_tx_timer_change_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_TIMER_CREATE_CALL_NOT_USED case TXM_TIMER_CREATE_CALL: { return_value = _txm_module_manager_tx_timer_create_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_TIMER_DEACTIVATE_CALL_NOT_USED case TXM_TIMER_DEACTIVATE_CALL: { return_value = _txm_module_manager_tx_timer_deactivate_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TIMER_DELETE_CALL_NOT_USED case TXM_TIMER_DELETE_CALL: { return_value = _txm_module_manager_tx_timer_delete_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TIMER_INFO_GET_CALL_NOT_USED case TXM_TIMER_INFO_GET_CALL: { return_value = _txm_module_manager_tx_timer_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_TIMER_PERFORMANCE_INFO_GET_CALL_NOT_USED case TXM_TIMER_PERFORMANCE_INFO_GET_CALL: { return_value = _txm_module_manager_tx_timer_performance_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_TIMER_PERFORMANCE_SYSTEM_INFO_GET_CALL_NOT_USED case TXM_TIMER_PERFORMANCE_SYSTEM_INFO_GET_CALL: { return_value = _txm_module_manager_tx_timer_performance_system_info_get_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_TRACE_BUFFER_FULL_NOTIFY_CALL_NOT_USED case TXM_TRACE_BUFFER_FULL_NOTIFY_CALL: { return_value = _txm_module_manager_tx_trace_buffer_full_notify_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TRACE_DISABLE_CALL_NOT_USED case TXM_TRACE_DISABLE_CALL: { return_value = _txm_module_manager_tx_trace_disable_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_TRACE_ENABLE_CALL_NOT_USED case TXM_TRACE_ENABLE_CALL: { return_value = _txm_module_manager_tx_trace_enable_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_TRACE_EVENT_FILTER_CALL_NOT_USED case TXM_TRACE_EVENT_FILTER_CALL: { return_value = _txm_module_manager_tx_trace_event_filter_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TRACE_EVENT_UNFILTER_CALL_NOT_USED case TXM_TRACE_EVENT_UNFILTER_CALL: { return_value = _txm_module_manager_tx_trace_event_unfilter_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TRACE_INTERRUPT_CONTROL_CALL_NOT_USED case TXM_TRACE_INTERRUPT_CONTROL_CALL: { return_value = _txm_module_manager_tx_trace_interrupt_control_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TRACE_ISR_ENTER_INSERT_CALL_NOT_USED case TXM_TRACE_ISR_ENTER_INSERT_CALL: { return_value = _txm_module_manager_tx_trace_isr_enter_insert_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TRACE_ISR_EXIT_INSERT_CALL_NOT_USED case TXM_TRACE_ISR_EXIT_INSERT_CALL: { return_value = _txm_module_manager_tx_trace_isr_exit_insert_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_TRACE_USER_EVENT_INSERT_CALL_NOT_USED case TXM_TRACE_USER_EVENT_INSERT_CALL: { return_value = _txm_module_manager_tx_trace_user_event_insert_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif + #ifndef TXM_MODULE_OBJECT_ALLOCATE_CALL_NOT_USED case TXM_MODULE_OBJECT_ALLOCATE_CALL: { return_value = _txm_module_manager_txm_module_object_allocate_dispatch(module_instance, param_0, param_1); break; } + #endif + #ifndef TXM_MODULE_OBJECT_DEALLOCATE_CALL_NOT_USED case TXM_MODULE_OBJECT_DEALLOCATE_CALL: { return_value = _txm_module_manager_txm_module_object_deallocate_dispatch(module_instance, param_0); break; } + #endif + #ifndef TXM_MODULE_OBJECT_POINTER_GET_CALL_NOT_USED case TXM_MODULE_OBJECT_POINTER_GET_CALL: { return_value = _txm_module_manager_txm_module_object_pointer_get_dispatch(module_instance, param_0, param_1, param_2); break; } + #endif + #ifndef TXM_MODULE_OBJECT_POINTER_GET_EXTENDED_CALL_NOT_USED case TXM_MODULE_OBJECT_POINTER_GET_EXTENDED_CALL: { return_value = _txm_module_manager_txm_module_object_pointer_get_extended_dispatch(module_instance, param_0, param_1, (ALIGN_TYPE *) param_2); break; } + #endif default: { diff --git a/common_smp/inc/tx_api.h b/common_smp/inc/tx_api.h index 7758bd5c..ee343f15 100644 --- a/common_smp/inc/tx_api.h +++ b/common_smp/inc/tx_api.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* tx_api.h PORTABLE SMP */ -/* 6.1.5 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -55,6 +55,9 @@ /* add option to remove FileX */ /* pointer, fix whitespace, */ /* resulting in version 6.1.5 */ +/* 04-02-2021 Scott Larson Modified comment(s), and */ +/* update patch number, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -94,7 +97,7 @@ extern "C" { #define AZURE_RTOS_THREADX #define THREADX_MAJOR_VERSION 6 #define THREADX_MINOR_VERSION 1 -#define THREADX_PATCH_VERSION 5 +#define THREADX_PATCH_VERSION 6 /* Define the following symbol for backward compatibility */ #define EL_PRODUCT_THREADX diff --git a/ports/arc_em/metaware/inc/tx_port.h b/ports/arc_em/metaware/inc/tx_port.h index 2fee779d..64b14664 100644 --- a/ports/arc_em/metaware/inc/tx_port.h +++ b/ports/arc_em/metaware/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARCv2_EM/MetaWare */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -288,7 +291,7 @@ ULONG _tx_misra_time_stamp_get(VOID); macros. */ -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; #define TX_DISABLE interrupt_save = _clri(); #define TX_RESTORE _seti(interrupt_save); @@ -308,7 +311,7 @@ ULONG _tx_misra_time_stamp_get(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARCv2_EM/MetaWare Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_em/metaware/readme_threadx.txt b/ports/arc_em/metaware/readme_threadx.txt index d7791171..276c9867 100644 --- a/ports/arc_em/metaware/readme_threadx.txt +++ b/ports/arc_em/metaware/readme_threadx.txt @@ -209,6 +209,18 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_initialize_low_level.s Modified comments + tx_thread_context_restore.s r25/r30 are caller saved + tx_thread_context_save.s r25/r30 are caller saved + tx_thread_interrupt_control.s Modified comments + tx_thread_schedule.s fixed interrupt priority overwritting bug, + and fixed hardware stack checker disable and reenable logic + tx_thread_stack_build.s Modified comments + tx_thread_system_return.s Modified comments + tx_timer_interrupt.s remove unneeded load of _tx_thread_preempt_disable + 09-30-2020 Initial ThreadX 6.1 for ARCv2 EM using MetaWare tools. diff --git a/ports/arc_em/metaware/src/tx_initialize_low_level.s b/ports/arc_em/metaware/src/tx_initialize_low_level.s index bcd91dff..4be1e0c1 100644 --- a/ports/arc_em/metaware/src/tx_initialize_low_level.s +++ b/ports/arc_em/metaware/src/tx_initialize_low_level.s @@ -8,33 +8,32 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Initialize */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; + .equ IRQ_SELECT, 0x40B .equ KSTACK_TOP, 0x264 .equ KSTACK_BASE, 0x265 .equ STATUS32_SC, 0x4000 -; + ; ; /* Define section for placement after all linker allocated RAM memory. This -; is used to calculate the first free address that is passed to +; is used to calculate the first free address that is passed to ; tx_appication_define, soley for the ThreadX application's use. */ ; .section ".free_memory","aw" .align 4 .global _tx_first_free_address _tx_first_free_address: - .space 4 + .space 4 ; ; /* Define section for placement before the main stack area for setting ; up the STACK_TOP address for hardware stack checking. */ @@ -53,54 +52,55 @@ _tx_system_stack_top_address: .global _tx_system_stack_base_address _tx_system_stack_base_address: .space 4 -; -; + .text -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_initialize_low_level ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for any low-level processor */ -;/* initialization, including setting up interrupt vectors, setting */ -;/* up a periodic timer interrupt source, saving the system stack */ -;/* pointer for use in ISR processing later, and finding the first */ -;/* available RAM memory address for tx_application_define. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comments, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_initialize_low_level(VOID) ;{ .global _tx_initialize_low_level - .type _tx_initialize_low_level, @function + .type _tx_initialize_low_level, @function _tx_initialize_low_level: .ifdef TX_ENABLE_HW_STACK_CHECKING @@ -130,7 +130,7 @@ _tx_initialize_low_level: ; ; ; /* Setup Timer 0 for periodic interrupts at interrupt vector 16. */ -; +; mov r0, 0 ; Disable additional ISR reg saving/restoring sr r0, [AUX_IRQ_CTRL] ; @@ -171,7 +171,7 @@ _tx_initialize_low_level: ; ; /* Define default vector table entries. */ ; - .global _tx_memory_error + .global _tx_memory_error _tx_memory_error: flag 1 nop @@ -179,7 +179,7 @@ _tx_memory_error: nop b _tx_memory_error - .global _tx_instruction_error + .global _tx_instruction_error _tx_instruction_error: flag 1 nop @@ -187,7 +187,7 @@ _tx_instruction_error: nop b _tx_instruction_error - .global _tx_ev_machine_check + .global _tx_ev_machine_check _tx_ev_machine_check: flag 1 nop @@ -195,7 +195,7 @@ _tx_ev_machine_check: nop b _tx_ev_machine_check - .global _tx_ev_tblmiss_inst + .global _tx_ev_tblmiss_inst _tx_ev_tblmiss_inst: flag 1 nop @@ -203,7 +203,7 @@ _tx_ev_tblmiss_inst: nop b _tx_ev_tblmiss_inst - .global _tx_ev_tblmiss_data + .global _tx_ev_tblmiss_data _tx_ev_tblmiss_data: flag 1 nop @@ -211,7 +211,7 @@ _tx_ev_tblmiss_data: nop b _tx_ev_tblmiss_data - .global _tx_ev_protection_viol + .global _tx_ev_protection_viol _tx_ev_protection_viol: flag 1 nop @@ -219,7 +219,7 @@ _tx_ev_protection_viol: nop b _tx_ev_protection_viol - .global _tx_ev_privilege_viol + .global _tx_ev_privilege_viol _tx_ev_privilege_viol: flag 1 nop @@ -227,7 +227,7 @@ _tx_ev_privilege_viol: nop b _tx_ev_privilege_viol - .global _tx_ev_software_int + .global _tx_ev_software_int _tx_ev_software_int: flag 1 nop @@ -235,7 +235,7 @@ _tx_ev_software_int: nop b _tx_ev_software_int - .global _tx_ev_trap + .global _tx_ev_trap _tx_ev_trap: flag 1 nop @@ -243,7 +243,7 @@ _tx_ev_trap: nop b _tx_ev_trap - .global _tx_ev_extension + .global _tx_ev_extension _tx_ev_extension: flag 1 nop @@ -251,7 +251,7 @@ _tx_ev_extension: nop b _tx_ev_extension - .global _tx_ev_divide_by_zero + .global _tx_ev_divide_by_zero _tx_ev_divide_by_zero: flag 1 nop @@ -259,7 +259,7 @@ _tx_ev_divide_by_zero: nop b _tx_ev_divide_by_zero - .global _tx_ev_dc_error + .global _tx_ev_dc_error _tx_ev_dc_error: flag 1 nop @@ -267,7 +267,7 @@ _tx_ev_dc_error: nop b _tx_ev_dc_error - .global _tx_ev_maligned + .global _tx_ev_maligned _tx_ev_maligned: flag 1 nop @@ -275,7 +275,7 @@ _tx_ev_maligned: nop b _tx_ev_maligned - .global _tx_unsued_0 + .global _tx_unsued_0 _tx_unsued_0: flag 1 nop @@ -283,7 +283,7 @@ _tx_unsued_0: nop b _tx_unsued_0 - .global _tx_unused_1 + .global _tx_unused_1 _tx_unused_1: flag 1 nop @@ -291,7 +291,7 @@ _tx_unused_1: nop b _tx_unused_1 - .global _tx_timer_0 + .global _tx_timer_0 _tx_timer_0: ; ; /* By default, setup Timer 0 as the ThreadX timer interrupt. */ @@ -311,7 +311,7 @@ _tx_timer_0: ; nop ; b _tx_timer_0 - .global _tx_timer_1 + .global _tx_timer_1 _tx_timer_1: sub sp, sp, 160 ; Allocate an interrupt stack frame st blink, [sp, 16] ; Save blink @@ -333,7 +333,7 @@ _tx_timer_1: ; nop ; b _tx_timer_1 - .global _tx_undefined_0 + .global _tx_undefined_0 _tx_undefined_0: flag 1 nop @@ -341,7 +341,7 @@ _tx_undefined_0: nop b _tx_undefined_0 - .global _tx_undefined_1 + .global _tx_undefined_1 _tx_undefined_1: flag 1 nop @@ -349,7 +349,7 @@ _tx_undefined_1: nop b _tx_undefined_1 - .global _tx_undefined_2 + .global _tx_undefined_2 _tx_undefined_2: flag 1 nop diff --git a/ports/arc_em/metaware/src/tx_thread_context_restore.s b/ports/arc_em/metaware/src/tx_thread_context_restore.s index 882b306c..df072a7b 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_restore.s +++ b/ports/arc_em/metaware/src/tx_thread_context_restore.s @@ -8,77 +8,70 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; + .equ BTA, 0x412 .equ KSTACK_TOP, 0x264 .equ KSTACK_BASE, 0x265 .equ STATUS32_SC, 0x4000 -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_restore ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function restores the interrupt context if it is processing a */ -;/* nested interrupt. If not, it returns to the interrupt thread if no */ -;/* preemption is necessary. Otherwise, if preemption is necessary or */ -;/* if no thread was running, the function returns to the scheduler. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling routine */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs Interrupt Service Routines */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function restores the interrupt context if it is processing a */ +;/* nested interrupt. If not, it returns to the interrupt thread if no */ +;/* preemption is necessary. Otherwise, if preemption is necessary or */ +;/* if no thread was running, the function returns to the scheduler. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling routine */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs Interrupt Service Routines */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ +;/* r25/r30 are caller saved, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_restore(VOID) ;{ .global _tx_thread_context_restore - .type _tx_thread_context_restore, @function + .type _tx_thread_context_restore, @function _tx_thread_context_restore: ; ; /* Note: it is assumed that the stack pointer is in the same position now as @@ -109,7 +102,7 @@ _tx_thread_context_restore: ; ; /* Interrupts are nested. */ ; -; /* Just recover the saved registers and return to the point of +; /* Just recover the saved registers and return to the point of ; interrupt. */ ; @@ -119,7 +112,7 @@ __tx_thread_nested_restore: sr r0, [LP_START] ; Restore LP_START ld r1, [sp, 8] ; Recover LP_END sr r1, [LP_END] ; Restore LP_END - ld r2, [sp, 12] ; Recover LP_COUNT + ld r2, [sp, 12] ; Recover LP_COUNT mov LP_COUNT, r2 ld r2, [sp, 156] ; Pickup BTA sr r2, [BTA] ; Recover BTA @@ -128,6 +121,7 @@ __tx_thread_nested_restore: ld r59, [sp, 144] ; Recover r59 .endif ld blink, [sp, 16] ; Recover blink + ld r25, [sp, 32] ; Recover r25 ld r12, [sp, 84] ; Recover r12 ld r11, [sp, 88] ; Recover r11 ld r10, [sp, 92] ; Recover r10 @@ -140,8 +134,9 @@ __tx_thread_nested_restore: ld r3, [sp, 120] ; Recover r3 ld r2, [sp, 124] ; Recover r2 ld r1, [sp, 128] ; Recover r1 - ld r0, [sp, 132] ; Recover r0 - add sp, sp, 160 ; Recover interrupt stack frame + ld r0, [sp, 132] ; Recover r0 + ld r30, [sp, 136] ; Recover r30 + add sp, sp, 160 ; Recover interrupt stack frame rtie ; Return from interrupt ; ; @@ -149,7 +144,7 @@ __tx_thread_nested_restore: __tx_thread_not_nested_restore: ; ; /* Determine if a thread was interrupted and no preemption is required. */ -; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) +; else if (((_tx_thread_current_ptr) && (_tx_thread_current_ptr == _tx_thread_execute_ptr) ; || (_tx_thread_preempt_disable)) ; { ; @@ -207,6 +202,7 @@ __tx_thread_no_preempt_restore: ld r59, [sp, 144] ; Recover r59 .endif ld blink, [sp, 16] ; Recover blink + ld r25, [sp, 32] ; Recover r25 ld r12, [sp, 84] ; Recover r12 ld r11, [sp, 88] ; Recover r11 ld r10, [sp, 92] ; Recover r10 @@ -220,6 +216,7 @@ __tx_thread_no_preempt_restore: ld r2, [sp, 124] ; Recover r2 ld r1, [sp, 128] ; Recover r1 ld r0, [sp, 132] ; Recover r0 + ld r30, [sp, 136] ; Recover r30 add sp, sp, 160 ; Recover interrupt stack frame rtie ; Return from interrupt ; diff --git a/ports/arc_em/metaware/src/tx_thread_context_save.s b/ports/arc_em/metaware/src/tx_thread_context_save.s index e67cdd80..e252af97 100644 --- a/ports/arc_em/metaware/src/tx_thread_context_save.s +++ b/ports/arc_em/metaware/src/tx_thread_context_save.s @@ -8,76 +8,68 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; + .equ BTA, 0x412 .equ KSTACK_TOP, 0x264 .equ KSTACK_BASE, 0x265 .equ STATUS32_SC, 0x4000 -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_context_save ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function saves the context of an executing thread in the */ -;/* beginning of interrupt processing. The function also ensures that */ -;/* the system stack is used upon return to the calling ISR. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ISRs */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function saves the context of an executing thread in the */ +;/* beginning of interrupt processing. The function also ensures that */ +;/* the system stack is used upon return to the calling ISR. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ISRs */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ +;/* r25/r30 are caller saved, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_context_save(VOID) ;{ .global _tx_thread_context_save - .type _tx_thread_context_save, @function + .type _tx_thread_context_save, @function _tx_thread_context_save: ; ; /* Upon entry to this routine, it is assumed that an interrupt stack frame @@ -106,6 +98,8 @@ _tx_thread_context_save: ; calling ISR. */ ; __tx_thread_nested_save: ; Label is for special nested interrupt case from idle system save below + st r30, [sp, 136] ; Save r30 + st r25, [sp, 32] ; Save r25 st r12, [sp, 84] ; Save r12 st r11, [sp, 88] ; Save r11 st r10, [sp, 92] ; Save r10 @@ -114,7 +108,7 @@ __tx_thread_nested_save: ; Label is for special n st r7, [sp, 104] ; Save r7 st r6, [sp, 108] ; Save r6 st r5, [sp, 112] ; Save r5 - st r4, [sp, 116] ; Save r6 + st r4, [sp, 116] ; Save r4 lr r10, [LP_START] ; Pickup LP_START lr r9, [LP_END] ; Pickup LP_END st LP_COUNT, [sp, 12] ; Save LP_COUNT @@ -156,6 +150,8 @@ __tx_thread_not_nested_save: add r0, r0, 1 ; Increment the nested interrupt count st r0, [gp, _tx_thread_system_state@sda] ; Update system state ld r1, [gp, _tx_thread_current_ptr@sda] ; Pickup current thread pointer + st r30, [sp, 136] ; Save r30 + st r25, [sp, 32] ; Save r25 st r12, [sp, 84] ; Save r12 st r11, [sp, 88] ; Save r11 breq r1, 0, __tx_thread_idle_system_save ; If no thread is running, idle system was @@ -247,13 +243,15 @@ __tx_thread_idle_system_save: lr r0, [AUX_IRQ_ACT] ; Pickup the interrupt active register neg r1, r0 ; Negate and r1, r0, r1 ; See if there are any other interrupts present - brne r0, r1, __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic + breq r0, r1, __tx_thread_not_nested + j __tx_thread_nested_save ; If more interrupts, go into the nested interrupt save logic +__tx_thread_not_nested: ; -; /* Not much to do here, just adjust the stack pointer, and return to +; /* Not much to do here, just adjust the stack pointer, and return to ; ISR processing. */ ; j_s.d [blink] ; Return to ISR - add sp, sp, 160 ; Recover stack space + add sp, sp, 160 ; Recover stack space ; ; } ;} diff --git a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s index e032d6d8..59a078fa 100644 --- a/ports/arc_em/metaware/src/tx_thread_interrupt_control.s +++ b/ports/arc_em/metaware/src/tx_thread_interrupt_control.s @@ -8,69 +8,61 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_interrupt_control ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is responsible for changing the interrupt lockout */ -;/* posture of the system. */ -;/* */ -;/* INPUT */ -;/* */ -;/* new_posture New interrupt lockout posture */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* old_posture Old interrupt lockout posture */ -;/* */ -;/* CALLS */ -;/* */ -;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* Application Code */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comments, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;UINT _tx_thread_interrupt_control(UINT new_posture) ;{ .global _tx_thread_interrupt_control - .type _tx_thread_interrupt_control, @function + .type _tx_thread_interrupt_control, @function _tx_thread_interrupt_control: ; ; /* Pickup current interrupt lockout posture. */ diff --git a/ports/arc_em/metaware/src/tx_thread_schedule.s b/ports/arc_em/metaware/src/tx_thread_schedule.s index bb50e563..0cc74757 100644 --- a/ports/arc_em/metaware/src/tx_thread_schedule.s +++ b/ports/arc_em/metaware/src/tx_thread_schedule.s @@ -8,73 +8,67 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; + .equ BTA, 0x412 .equ KSTACK_TOP, 0x264 .equ KSTACK_BASE, 0x265 .equ STATUS32_SC, 0x4000 -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_schedule ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function waits for a thread control block pointer to appear in */ -;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ -;/* in the variable, the corresponding thread is resumed. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* This function waits for a thread control block pointer to appear in */ +;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +;/* in the variable, the corresponding thread is resumed. */ +;/* */ +;/* INPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* _tx_initialize_kernel_enter ThreadX entry function */ -;/* _tx_thread_system_return Return to system from thread */ -;/* _tx_thread_context_restore Restore thread's context */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* _tx_thread_system_return Return to system from thread */ +;/* _tx_thread_context_restore Restore thread's context */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comment(s), and */ +;/* fixed interrupt priority */ +;/* overwritting bug, and */ +;/* fixed hardware stack checker*/ +;/* disable and reenable logic, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -85,8 +79,13 @@ _tx_thread_schedule: ; ; /* Enable interrupts. */ ; - mov r0, 0x1F ; Build enable interrupt value - seti r0 ; Enable interrupts + seti 0 ; Enable interrupts without changing threshold level + + .ifdef TX_ENABLE_HW_STACK_CHECKING + lr r2, [status32] ; Pickup current STATUS32 + and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC) + kflag r2 ; Disable hardware stack checking + .endif ; ; /* Wait for a thread to execute. */ ; do @@ -99,7 +98,7 @@ __tx_thread_schedule_loop: ; ; } ; while(_tx_thread_execute_ptr == TX_NULL); -; +; ; /* Yes! We have a thread to execute. Lockout interrupts and ; transfer control to it. */ ; @@ -118,16 +117,6 @@ __tx_thread_schedule_loop: ld r4, [r0, 24] ; Pickup time-slice for this thread add r3, r3, 1 ; Increment run counter st r3, [r0, 4] ; Store the new run counter - - .ifdef TX_ENABLE_HW_STACK_CHECKING - lr r2, [status32] ; Pickup current STATUS32 - and r2, r2, ~STATUS32_SC ; Clear the hardware stack checking enable bit (SC) - kflag r2 ; Disable hardware stack checking - ld r3, [r0, 12] ; Pickup the top of the thread's stack (lowest address) - sr r3, [KSTACK_TOP] ; Setup KSTACK_TOP - ld r3, [r0, 16] ; Pickup the base of the thread's stack (highest address) - sr r3, [KSTACK_BASE] ; Setup KSTACK_BASE - .endif ; ; /* Setup time-slice, if present. */ ; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; @@ -135,6 +124,10 @@ __tx_thread_schedule_loop: ld sp, [r0, 8] ; Switch to thread's stack .ifdef TX_ENABLE_HW_STACK_CHECKING + ld r3, [r0, 12] ; Pickup the top of the thread's stack (lowest address) + sr r3, [KSTACK_TOP] ; Setup KSTACK_TOP + ld r3, [r0, 16] ; Pickup the base of the thread's stack (highest address) + sr r3, [KSTACK_BASE] ; Setup KSTACK_BASE or r2, r2, STATUS32_SC ; Or in hardware stack checking enable bit (SC) kflag r2 ; Enable hardware stack checking .endif @@ -176,8 +169,8 @@ __tx_thread_schedule_loop: ld r13, [sp, 64] ; Recover r13 ld r1, [sp, 68] ; Pickup status32 ld r30, [sp, 72] ; Recover r30 - add sp, sp, 76 ; Recover solicited stack frame - j_s.d [blink] ; Return to thread and restore flags + add sp, sp, 76 ; Recover solicited stack frame + j_s.d [blink] ; Return to thread and restore flags seti r1 ; Recover STATUS32 ; __tx_thread_schedule_int_ret: @@ -189,7 +182,7 @@ __tx_thread_schedule_int_ret: sr r0, [LP_START] ; Restore LP_START ld r1, [sp, 8] ; Recover LP_END sr r1, [LP_END] ; Restore LP_END - ld r2, [sp, 12] ; Recover LP_COUNT + ld r2, [sp, 12] ; Recover LP_COUNT mov LP_COUNT, r2 ld r0, [sp, 156] ; Pickup saved BTA sr r0, [BTA] ; Recover BTA @@ -230,7 +223,7 @@ __tx_thread_schedule_int_ret: .endif add sp, sp, 160 ; Recover interrupt stack frame rtie ; Return to point of interrupt - + ; ;} ; diff --git a/ports/arc_em/metaware/src/tx_thread_stack_build.s b/ports/arc_em/metaware/src/tx_thread_stack_build.s index b576b0ff..b6550712 100644 --- a/ports/arc_em/metaware/src/tx_thread_stack_build.s +++ b/ports/arc_em/metaware/src/tx_thread_stack_build.s @@ -8,70 +8,60 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -; -; - .equ LONG_ALIGN_MASK, 0xFFFFFFFC + + .equ LONG_ALIGN_MASK, 0xFFFFFFFC .equ INT_ENABLE_BITS, 0x8000001E -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_stack_build ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ +;/* */ ;/* This function builds a stack frame on the supplied thread's stack. */ ;/* The stack frame results in a fake interrupt return to the supplied */ -;/* function pointer. */ -;/* */ -;/* INPUT */ -;/* */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ ;/* thread_ptr Pointer to thread control blk */ ;/* function_ptr Pointer to return function */ -;/* */ -;/* OUTPUT */ -;/* */ +;/* */ +;/* OUTPUT */ +;/* */ ;/* None */ -;/* */ -;/* CALLS */ -;/* */ +;/* */ +;/* CALLS */ +;/* */ ;/* None */ -;/* */ -;/* CALLED BY */ -;/* */ +;/* */ +;/* CALLED BY */ +;/* */ ;/* _tx_thread_create Create thread service */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comments, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) @@ -80,11 +70,11 @@ .type _tx_thread_stack_build, @function _tx_thread_stack_build: ; -; +; ; /* Build a fake interrupt frame. The form of the fake interrupt stack ; on the ARCv2 EM should look like the following after it is built. ; Note that the extension registers are always assigned space here. -; +; ; Stack Top: 1 Interrupt stack frame type ; LP_START Initial loop start ; LP_END Initial loop end @@ -119,7 +109,7 @@ _tx_thread_stack_build: ; r2 Initial r2 ; r1 Initial r1 ; r0 Initial r0 -; r30 Initial r30 +; r30 Initial r30 ; r58 Initial r58 ; r59 Initial r59 ; 0 Reserved @@ -127,10 +117,10 @@ _tx_thread_stack_build: ; 0 Initial BTA ; 0 Point of Interrupt (thread entry point) ; 0 Initial STATUS32 -; 0 Backtrace -; 0 Backtrace -; 0 Backtrace -; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace +; 0 Backtrace ; ; *: these registers will only be saved and restored if flag -Xxmac_d16 is passed to hcac ; @@ -179,19 +169,19 @@ _tx_thread_stack_build: st r5, [r3, 128] ; Store initial r1 st r5, [r3, 132] ; Store initial r0 st r5, [r3, 136] ; Store initial r30 - st r5, [r3, 140] ; Store initial r58 + st r5, [r3, 140] ; Store initial r58 st r5, [r3, 144] ; Store initial r59 st r5, [r3, 148] ; Reserved st r5, [r3, 152] ; Reserved st r5, [r3, 156] ; Store initial BTA - st r1, [r3, 160] ; Store initial point of entry + st r1, [r3, 160] ; Store initial point of entry lr r6, [status32] ; Pickup STATUS32 or r6, r6, INT_ENABLE_BITS ; Make sure interrupts are enabled st r6, [r3, 164] ; Store initial STATUS32 - st r5, [r3, 168] ; Backtrace 0 - st r5, [r3, 172] ; Backtrace 0 - st r5, [r3, 176] ; Backtrace 0 - st r5, [r3, 180] ; Backtrace 0 + st r5, [r3, 168] ; Backtrace 0 + st r5, [r3, 172] ; Backtrace 0 + st r5, [r3, 176] ; Backtrace 0 + st r5, [r3, 180] ; Backtrace 0 ; ; /* Setup stack pointer. */ ; thread_ptr -> tx_thread_stack_ptr = r3; diff --git a/ports/arc_em/metaware/src/tx_thread_system_return.s b/ports/arc_em/metaware/src/tx_thread_system_return.s index fa061e1c..b3bbafed 100644 --- a/ports/arc_em/metaware/src/tx_thread_system_return.s +++ b/ports/arc_em/metaware/src/tx_thread_system_return.s @@ -8,69 +8,61 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Thread */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; + .equ KSTACK_TOP, 0x264 .equ KSTACK_BASE, 0x265 .equ STATUS32_SC, 0x4000 -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_thread.h" -;#include "tx_timer.h" -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_thread_system_return ARCv2_EM/MetaWare */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function is target processor specific. It is used to transfer */ -;/* control from a thread back to the ThreadX system. Only a */ -;/* minimal context is saved since the compiler assumes temp registers */ -;/* are going to get slicked by a function call anyway. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_thread_schedule Thread scheduling loop */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* ThreadX components */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +;/* 04-02-2021 Andres Mlinar Modified comments, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_system_return(VOID) @@ -105,7 +97,7 @@ _tx_thread_system_return: st r13, [sp, 64] ; Save r13 st r2, [sp, 68] ; Save status32 st r30, [sp, 72] ; Save r30 -; +; .ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY ; ; /* Call the thread exit function to indicate the thread is no longer executing. */ diff --git a/ports/arc_em/metaware/src/tx_timer_interrupt.s b/ports/arc_em/metaware/src/tx_timer_interrupt.s index 27141e01..a3aea5eb 100644 --- a/ports/arc_em/metaware/src/tx_timer_interrupt.s +++ b/ports/arc_em/metaware/src/tx_timer_interrupt.s @@ -8,32 +8,21 @@ ;/* and in the root directory of this software. */ ;/* */ ;/**************************************************************************/ -; -; + ;/**************************************************************************/ ;/**************************************************************************/ -;/** */ -;/** ThreadX Component */ +;/** */ +;/** ThreadX Component */ ;/** */ ;/** Timer */ ;/** */ ;/**************************************************************************/ ;/**************************************************************************/ -; -;#define TX_SOURCE_CODE -; -; -;/* Include necessary system files. */ -; -;#include "tx_api.h" -;#include "tx_timer.h" -;#include "tx_thread.h" -; -; -;/**************************************************************************/ -;/* */ -;/* FUNCTION RELEASE */ -;/* */ + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ ;/* _tx_timer_interrupt ARCv2_EM/MetaWare */ ;/* 6.1.3 */ ;/* AUTHOR */ @@ -41,34 +30,34 @@ ;/* William E. Lamie, Microsoft Corporation */ ;/* */ ;/* DESCRIPTION */ -;/* */ -;/* This function processes the hardware timer interrupt. This */ -;/* processing includes incrementing the system clock and checking for */ -;/* time slice and/or timer expiration. If either is found, the */ -;/* interrupt context save/restore functions are called along with the */ -;/* expiration functions. */ -;/* */ -;/* INPUT */ -;/* */ -;/* None */ -;/* */ -;/* OUTPUT */ -;/* */ -;/* None */ -;/* */ -;/* CALLS */ -;/* */ -;/* _tx_timer_expiration_process Process timer expiration */ -;/* _tx_thread_time_slice Time slice interrupted thread */ -;/* _tx_thread_context_save Save interrupt context */ -;/* _tx_thread_context_restore Restore interrupt context */ -;/* */ -;/* CALLED BY */ -;/* */ -;/* interrupt vector */ -;/* */ -;/* RELEASE HISTORY */ -;/* */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* interrupt context save/restore functions are called along with the */ +;/* expiration functions. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Process timer expiration */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* _tx_thread_context_save Save interrupt context */ +;/* _tx_thread_context_restore Restore interrupt context */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ @@ -81,7 +70,7 @@ ;VOID _tx_timer_interrupt(VOID) ;{ .global _tx_timer_interrupt - .type _tx_timer_interrupt, @function + .type _tx_timer_interrupt, @function _tx_timer_interrupt: ; ; /* Upon entry to this routine, it is assumed the interrupt stack frame has @@ -132,7 +121,7 @@ __tx_timer_no_time_slice: ; ld r0, [gp, _tx_timer_current_ptr@sda] ; Pickup current timer pointer ld r2, [r0, 0] ; Pickup examine actual list entry - breq r2, 0, __tx_timer_no_timer ; + breq r2, 0, __tx_timer_no_timer ; ; If NULL, no timer has expired, just move to the next entry ; ; /* Set expiration flag. */ @@ -220,7 +209,7 @@ __tx_timer_dont_activate: ; __tx_timer_not_ts_expiration: ; - st 0, [gp, _tx_timer_expired_time_slice@sda] + st 0, [gp, _tx_timer_expired_time_slice@sda] b _tx_thread_context_restore ; Go restore interrupt context.. ; ..clearing time-slice expired flag ; Note that we don't return from @@ -233,9 +222,9 @@ __tx_timer_nothing_expired: ld r0, [sp, 0] ; Recover r0 ld r1, [sp, 4] ; Recover r1 ld r2, [sp, 8] ; Recover r2 - add sp, sp, 160 ; Recover interrupt stack frame + add sp, sp, 160 ; Recover interrupt stack frame rtie ; Return to point of interrupt ; ;} .end - + diff --git a/ports/arc_hs/metaware/inc/tx_port.h b/ports/arc_hs/metaware/inc/tx_port.h index db08784e..d0cd7a99 100644 --- a/ports/arc_hs/metaware/inc/tx_port.h +++ b/ports/arc_hs/metaware/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARC_HS/MetaWare */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -288,7 +291,7 @@ ULONG _tx_misra_time_stamp_get(VOID); macros. */ -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; #define TX_DISABLE interrupt_save = _clri(); #define TX_RESTORE _seti(interrupt_save); @@ -322,7 +325,7 @@ VOID tx_thread_register_bank_assign(VOID *thread_ptr, UINT register_bank); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARC_HS/MetaWare Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arc_hs/metaware/readme_threadx.txt b/ports/arc_hs/metaware/readme_threadx.txt index 92b604b6..5e431c1d 100644 --- a/ports/arc_hs/metaware/readme_threadx.txt +++ b/ports/arc_hs/metaware/readme_threadx.txt @@ -241,6 +241,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 for ARC HS using MetaWare tools. diff --git a/ports/arm11/ac5/inc/tx_port.h b/ports/arm11/ac5/inc/tx_port.h index 0c873cc1..7b48f0c8 100644 --- a/ports/arm11/ac5/inc/tx_port.h +++ b/ports/arm11/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM11/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -317,7 +320,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/ac5/readme_threadx.txt b/ports/arm11/ac5/readme_threadx.txt index 114b5089..82a9dfa2 100644 --- a/ports/arm11/ac5/readme_threadx.txt +++ b/ports/arm11/ac5/readme_threadx.txt @@ -524,6 +524,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using AC5 tools. diff --git a/ports/arm11/gnu/inc/tx_port.h b/ports/arm11/gnu/inc/tx_port.h index 09c52000..037377ba 100644 --- a/ports/arm11/gnu/inc/tx_port.h +++ b/ports/arm11/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM11/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; ORR %1,%0,#0xC0; MSR CPSR_cxsf,%1 ": "=r" (interrupt_save), "=r" (tx_temp) ); @@ -306,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm11/gnu/readme_threadx.txt b/ports/arm11/gnu/readme_threadx.txt index 6c502efd..d7300854 100644 --- a/ports/arm11/gnu/readme_threadx.txt +++ b/ports/arm11/gnu/readme_threadx.txt @@ -486,6 +486,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for ARM11 using GNU tools. diff --git a/ports/arm11/iar/inc/tx_port.h b/ports/arm11/iar/inc/tx_port.h index 150c0578..75d7b613 100644 --- a/ports/arm11/iar/inc/tx_port.h +++ b/ports/arm11/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM11/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -334,9 +337,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -372,7 +375,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM11/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm11/iar/readme_threadx.txt b/ports/arm11/iar/readme_threadx.txt index 7b0400af..fbe7deeb 100644 --- a/ports/arm11/iar/readme_threadx.txt +++ b/ports/arm11/iar/readme_threadx.txt @@ -517,6 +517,9 @@ The project options "General Options -> Library Configuration" should also have 11. Revision History +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for ARM11 using IAR's ARM tools. diff --git a/ports/arm9/ac5/inc/tx_port.h b/ports/arm9/ac5/inc/tx_port.h index 0d5c2ac3..05712046 100644 --- a/ports/arm9/ac5/inc/tx_port.h +++ b/ports/arm9/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM9/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -267,7 +270,7 @@ typedef unsigned short USHORT; macros. */ #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -298,7 +301,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -319,7 +322,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/ac5/readme_threadx.txt b/ports/arm9/ac5/readme_threadx.txt index 47272b53..f07ea494 100644 --- a/ports/arm9/ac5/readme_threadx.txt +++ b/ports/arm9/ac5/readme_threadx.txt @@ -508,6 +508,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for ARM9 using AC5 tools. diff --git a/ports/arm9/gnu/inc/tx_port.h b/ports/arm9/gnu/inc/tx_port.h index 3535f75f..a7431396 100644 --- a/ports/arm9/gnu/inc/tx_port.h +++ b/ports/arm9/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM9/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; ORR %1,%0,#0xC0; MSR CPSR_cxsf,%1 ": "=r" (interrupt_save), "=r" (tx_temp) ); @@ -306,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/arm9/gnu/readme_threadx.txt b/ports/arm9/gnu/readme_threadx.txt index 41572f18..54046146 100644 --- a/ports/arm9/gnu/readme_threadx.txt +++ b/ports/arm9/gnu/readme_threadx.txt @@ -486,6 +486,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for ARM9 using GNU tools. diff --git a/ports/arm9/iar/inc/tx_port.h b/ports/arm9/iar/inc/tx_port.h index 2c14c396..352cac03 100644 --- a/ports/arm9/iar/inc/tx_port.h +++ b/ports/arm9/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h ARM9/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -334,9 +337,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -372,7 +375,7 @@ void _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARM9/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/arm9/iar/readme_threadx.txt b/ports/arm9/iar/readme_threadx.txt index dd7b087a..3f394604 100644 --- a/ports/arm9/iar/readme_threadx.txt +++ b/ports/arm9/iar/readme_threadx.txt @@ -518,6 +518,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for ARM9 using IAR's ARM tools. diff --git a/ports/c667x/ccs/inc/tx_port.h b/ports/c667x/ccs/inc/tx_port.h index 03feeac8..d650e737 100644 --- a/ports/c667x/ccs/inc/tx_port.h +++ b/ports/c667x/ccs/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h C667x/TI */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -237,7 +240,7 @@ typedef unsigned short USHORT; is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #ifdef TX_SKIP_INTRINSICS unsigned int _tx_thread_interrupt_control(unsigned int); @@ -264,7 +267,7 @@ unsigned int _tx_thread_interrupt_control(unsigned int); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX C667x/TI Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/c667x/ccs/readme_threadx.txt b/ports/c667x/ccs/readme_threadx.txt index c5cffbd4..8826de45 100644 --- a/ports/c667x/ccs/readme_threadx.txt +++ b/ports/c667x/ccs/readme_threadx.txt @@ -238,6 +238,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for TMS320C667x using TI Code Composer tools. diff --git a/ports/cortex_a15/ac6/inc/tx_port.h b/ports/cortex_a15/ac6/inc/tx_port.h index 59659cf0..de22d9a2 100644 --- a/ports/cortex_a15/ac6/inc/tx_port.h +++ b/ports/cortex_a15/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A15/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/ac6/readme_threadx.txt b/ports/cortex_a15/ac6/readme_threadx.txt index 27a3c8f4..8d81625a 100644 --- a/ports/cortex_a15/ac6/readme_threadx.txt +++ b/ports/cortex_a15/ac6/readme_threadx.txt @@ -332,6 +332,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A15 using AC6 tools. diff --git a/ports/cortex_a15/gnu/inc/tx_port.h b/ports/cortex_a15/gnu/inc/tx_port.h index 507f69ed..d054d283 100644 --- a/ports/cortex_a15/gnu/inc/tx_port.h +++ b/ports/cortex_a15/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A15/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a15/gnu/readme_threadx.txt b/ports/cortex_a15/gnu/readme_threadx.txt index b060b1b8..5bd5eb7c 100644 --- a/ports/cortex_a15/gnu/readme_threadx.txt +++ b/ports/cortex_a15/gnu/readme_threadx.txt @@ -503,6 +503,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A15 using GNU tools. diff --git a/ports/cortex_a15/iar/inc/tx_port.h b/ports/cortex_a15/iar/inc/tx_port.h index 7529be75..e2870721 100644 --- a/ports/cortex_a15/iar/inc/tx_port.h +++ b/ports/cortex_a15/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A15/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -336,9 +339,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif @@ -382,7 +385,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A15/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a15/iar/readme_threadx.txt b/ports/cortex_a15/iar/readme_threadx.txt index f7b0f20e..151c5253 100644 --- a/ports/cortex_a15/iar/readme_threadx.txt +++ b/ports/cortex_a15/iar/readme_threadx.txt @@ -534,6 +534,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for Cortex-A15 using IAR's ARM tools. diff --git a/ports/cortex_a35/ac6/inc/tx_port.h b/ports/cortex_a35/ac6/inc/tx_port.h index 41192cd5..cde96a4b 100644 --- a/ports/cortex_a35/ac6/inc/tx_port.h +++ b/ports/cortex_a35/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A35/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -311,7 +314,7 @@ unsigned long long temp; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -321,7 +324,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -354,7 +357,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/ac6/readme_threadx.txt b/ports/cortex_a35/ac6/readme_threadx.txt index 6dd1a997..fafe435c 100644 --- a/ports/cortex_a35/ac6/readme_threadx.txt +++ b/ports/cortex_a35/ac6/readme_threadx.txt @@ -243,6 +243,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools. diff --git a/ports/cortex_a35/gnu/inc/tx_port.h b/ports/cortex_a35/gnu/inc/tx_port.h index ca8a1149..4ca50721 100644 --- a/ports/cortex_a35/gnu/inc/tx_port.h +++ b/ports/cortex_a35/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A35/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -311,7 +314,7 @@ unsigned long long temp; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -321,7 +324,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -354,7 +357,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a35/gnu/readme_threadx.txt b/ports/cortex_a35/gnu/readme_threadx.txt index 5b2a3ef8..bab64522 100644 --- a/ports/cortex_a35/gnu/readme_threadx.txt +++ b/ports/cortex_a35/gnu/readme_threadx.txt @@ -243,6 +243,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using GCC tools. diff --git a/ports/cortex_a5/ac5/inc/tx_port.h b/ports/cortex_a5/ac5/inc/tx_port.h index 516f3f0f..4e51b123 100644 --- a/ports/cortex_a5/ac5/inc/tx_port.h +++ b/ports/cortex_a5/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -324,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/ac5/readme_threadx.txt b/ports/cortex_a5/ac5/readme_threadx.txt index d6a08426..12962be2 100644 --- a/ports/cortex_a5/ac5/readme_threadx.txt +++ b/ports/cortex_a5/ac5/readme_threadx.txt @@ -535,6 +535,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using AC5 tools. diff --git a/ports/cortex_a5/gnu/inc/tx_port.h b/ports/cortex_a5/gnu/inc/tx_port.h index 989d71ed..d3ca8b91 100644 --- a/ports/cortex_a5/gnu/inc/tx_port.h +++ b/ports/cortex_a5/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/gnu/readme_threadx.txt b/ports/cortex_a5/gnu/readme_threadx.txt index 28569eda..9653bd11 100644 --- a/ports/cortex_a5/gnu/readme_threadx.txt +++ b/ports/cortex_a5/gnu/readme_threadx.txt @@ -503,6 +503,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using GNU tools. diff --git a/ports/cortex_a5/green/inc/tx_port.h b/ports/cortex_a5/green/inc/tx_port.h index 037a85f0..f2de0496 100644 --- a/ports/cortex_a5/green/inc/tx_port.h +++ b/ports/cortex_a5/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -307,7 +310,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -391,8 +394,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5/green/readme_threadx.txt b/ports/cortex_a5/green/readme_threadx.txt index 58eb9de0..28e59b78 100644 --- a/ports/cortex_a5/green/readme_threadx.txt +++ b/ports/cortex_a5/green/readme_threadx.txt @@ -517,6 +517,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-A5/Green Hills port. diff --git a/ports/cortex_a5/iar/inc/tx_port.h b/ports/cortex_a5/iar/inc/tx_port.h index 7d02f22a..27c61956 100644 --- a/ports/cortex_a5/iar/inc/tx_port.h +++ b/ports/cortex_a5/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -335,9 +338,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -380,7 +383,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a5/iar/readme_threadx.txt b/ports/cortex_a5/iar/readme_threadx.txt index fc4d73d2..dc62701c 100644 --- a/ports/cortex_a5/iar/readme_threadx.txt +++ b/ports/cortex_a5/iar/readme_threadx.txt @@ -534,6 +534,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for Cortex-A5 using IAR's ARM tools. diff --git a/ports/cortex_a5x/ac6/inc/tx_port.h b/ports/cortex_a5x/ac6/inc/tx_port.h index 82de074d..129771ad 100644 --- a/ports/cortex_a5x/ac6/inc/tx_port.h +++ b/ports/cortex_a5x/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x/ARM */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -311,7 +314,7 @@ unsigned long long temp; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -321,7 +324,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -354,7 +357,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x/ARM Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a5x/ac6/readme_threadx.txt b/ports/cortex_a5x/ac6/readme_threadx.txt index 0e3a645a..c3de31bb 100644 --- a/ports/cortex_a5x/ac6/readme_threadx.txt +++ b/ports/cortex_a5x/ac6/readme_threadx.txt @@ -245,6 +245,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5x using ARM tools. diff --git a/ports/cortex_a7/ac5/inc/tx_port.h b/ports/cortex_a7/ac5/inc/tx_port.h index 7f3f43bc..7c0ee281 100644 --- a/ports/cortex_a7/ac5/inc/tx_port.h +++ b/ports/cortex_a7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -324,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac5/readme_threadx.txt b/ports/cortex_a7/ac5/readme_threadx.txt index 48b5a904..347a5ec9 100644 --- a/ports/cortex_a7/ac5/readme_threadx.txt +++ b/ports/cortex_a7/ac5/readme_threadx.txt @@ -534,6 +534,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using AC5 tools. diff --git a/ports/cortex_a7/ac6/inc/tx_port.h b/ports/cortex_a7/ac6/inc/tx_port.h index b418ea3b..83a43e76 100644 --- a/ports/cortex_a7/ac6/inc/tx_port.h +++ b/ports/cortex_a7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/ac6/readme_threadx.txt b/ports/cortex_a7/ac6/readme_threadx.txt index 82503ec4..b9d6bf88 100644 --- a/ports/cortex_a7/ac6/readme_threadx.txt +++ b/ports/cortex_a7/ac6/readme_threadx.txt @@ -332,6 +332,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using AC6 tools. diff --git a/ports/cortex_a7/gnu/inc/tx_port.h b/ports/cortex_a7/gnu/inc/tx_port.h index 997dd446..ada3bfa6 100644 --- a/ports/cortex_a7/gnu/inc/tx_port.h +++ b/ports/cortex_a7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/gnu/readme_threadx.txt b/ports/cortex_a7/gnu/readme_threadx.txt index b7186b39..446d6bcf 100644 --- a/ports/cortex_a7/gnu/readme_threadx.txt +++ b/ports/cortex_a7/gnu/readme_threadx.txt @@ -503,6 +503,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using GNU tools. diff --git a/ports/cortex_a7/green/inc/tx_port.h b/ports/cortex_a7/green/inc/tx_port.h index 76e55d62..6190db5f 100644 --- a/ports/cortex_a7/green/inc/tx_port.h +++ b/ports/cortex_a7/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -307,7 +310,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -391,8 +394,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/green/readme_threadx.txt b/ports/cortex_a7/green/readme_threadx.txt index 6ed148a0..3195b4e4 100644 --- a/ports/cortex_a7/green/readme_threadx.txt +++ b/ports/cortex_a7/green/readme_threadx.txt @@ -517,6 +517,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-A7/Green Hills port. diff --git a/ports/cortex_a7/iar/inc/tx_port.h b/ports/cortex_a7/iar/inc/tx_port.h index d339d526..5c2139fb 100644 --- a/ports/cortex_a7/iar/inc/tx_port.h +++ b/ports/cortex_a7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -335,9 +338,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -380,7 +383,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/IAR Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a7/iar/readme_threadx.txt b/ports/cortex_a7/iar/readme_threadx.txt index 534f8465..7f16ed21 100644 --- a/ports/cortex_a7/iar/readme_threadx.txt +++ b/ports/cortex_a7/iar/readme_threadx.txt @@ -534,6 +534,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for Cortex-A7 using IAR's ARM tools. diff --git a/ports/cortex_a8/ac5/inc/tx_port.h b/ports/cortex_a8/ac5/inc/tx_port.h index 3f3889d9..72b047df 100644 --- a/ports/cortex_a8/ac5/inc/tx_port.h +++ b/ports/cortex_a8/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -324,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac5/readme_threadx.txt b/ports/cortex_a8/ac5/readme_threadx.txt index 05355c12..13fa045f 100644 --- a/ports/cortex_a8/ac5/readme_threadx.txt +++ b/ports/cortex_a8/ac5/readme_threadx.txt @@ -537,6 +537,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A8 using AC5 tools. diff --git a/ports/cortex_a8/ac6/inc/tx_port.h b/ports/cortex_a8/ac6/inc/tx_port.h index 0dcdf194..fe8c562d 100644 --- a/ports/cortex_a8/ac6/inc/tx_port.h +++ b/ports/cortex_a8/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/ac6/readme_threadx.txt b/ports/cortex_a8/ac6/readme_threadx.txt index fc0697bb..a6e5a5c0 100644 --- a/ports/cortex_a8/ac6/readme_threadx.txt +++ b/ports/cortex_a8/ac6/readme_threadx.txt @@ -329,6 +329,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A8 using AC6 tools. diff --git a/ports/cortex_a8/gnu/inc/tx_port.h b/ports/cortex_a8/gnu/inc/tx_port.h index dac79ee2..120ac155 100644 --- a/ports/cortex_a8/gnu/inc/tx_port.h +++ b/ports/cortex_a8/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/gnu/readme_threadx.txt b/ports/cortex_a8/gnu/readme_threadx.txt index e06f0dc0..8f57bf4a 100644 --- a/ports/cortex_a8/gnu/readme_threadx.txt +++ b/ports/cortex_a8/gnu/readme_threadx.txt @@ -503,6 +503,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A8 using GNU tools. diff --git a/ports/cortex_a8/green/inc/tx_port.h b/ports/cortex_a8/green/inc/tx_port.h index 61b3db87..13d8f0f5 100644 --- a/ports/cortex_a8/green/inc/tx_port.h +++ b/ports/cortex_a8/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -307,7 +310,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -391,8 +394,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a8/green/readme_threadx.txt b/ports/cortex_a8/green/readme_threadx.txt index 330d21e2..be5de73a 100644 --- a/ports/cortex_a8/green/readme_threadx.txt +++ b/ports/cortex_a8/green/readme_threadx.txt @@ -518,6 +518,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-A8/Green Hills port. diff --git a/ports/cortex_a8/iar/inc/tx_port.h b/ports/cortex_a8/iar/inc/tx_port.h index 58c88d26..30fa56de 100644 --- a/ports/cortex_a8/iar/inc/tx_port.h +++ b/ports/cortex_a8/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A8/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -335,9 +338,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif @@ -381,7 +384,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A8/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a8/iar/readme_threadx.txt b/ports/cortex_a8/iar/readme_threadx.txt index 3f380c85..9c55e729 100644 --- a/ports/cortex_a8/iar/readme_threadx.txt +++ b/ports/cortex_a8/iar/readme_threadx.txt @@ -534,6 +534,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for Cortex-A8 using IAR's ARM tools. diff --git a/ports/cortex_a9/ac5/inc/tx_port.h b/ports/cortex_a9/ac5/inc/tx_port.h index b14def8c..3f648a56 100644 --- a/ports/cortex_a9/ac5/inc/tx_port.h +++ b/ports/cortex_a9/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -324,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac5/readme_threadx.txt b/ports/cortex_a9/ac5/readme_threadx.txt index 68fdde1c..56cff19c 100644 --- a/ports/cortex_a9/ac5/readme_threadx.txt +++ b/ports/cortex_a9/ac5/readme_threadx.txt @@ -535,6 +535,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using AC5 tools. diff --git a/ports/cortex_a9/ac6/inc/tx_port.h b/ports/cortex_a9/ac6/inc/tx_port.h index bc54c159..b03bdb85 100644 --- a/ports/cortex_a9/ac6/inc/tx_port.h +++ b/ports/cortex_a9/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/ac6/readme_threadx.txt b/ports/cortex_a9/ac6/readme_threadx.txt index ab150408..f8196fb5 100644 --- a/ports/cortex_a9/ac6/readme_threadx.txt +++ b/ports/cortex_a9/ac6/readme_threadx.txt @@ -332,6 +332,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using AC6 tools. diff --git a/ports/cortex_a9/gnu/inc/tx_port.h b/ports/cortex_a9/gnu/inc/tx_port.h index a9652aad..28bc2788 100644 --- a/ports/cortex_a9/gnu/inc/tx_port.h +++ b/ports/cortex_a9/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -313,7 +316,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/gnu/readme_threadx.txt b/ports/cortex_a9/gnu/readme_threadx.txt index c1b02ff8..d4d7627a 100644 --- a/ports/cortex_a9/gnu/readme_threadx.txt +++ b/ports/cortex_a9/gnu/readme_threadx.txt @@ -503,6 +503,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using GNU tools. diff --git a/ports/cortex_a9/green/inc/tx_port.h b/ports/cortex_a9/green/inc/tx_port.h index ba01cbdc..46367740 100644 --- a/ports/cortex_a9/green/inc/tx_port.h +++ b/ports/cortex_a9/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -307,7 +310,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -391,8 +394,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_a9/green/readme_threadx.txt b/ports/cortex_a9/green/readme_threadx.txt index 18e4fcdf..db232e1f 100644 --- a/ports/cortex_a9/green/readme_threadx.txt +++ b/ports/cortex_a9/green/readme_threadx.txt @@ -517,6 +517,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-A9/Green Hills port. diff --git a/ports/cortex_a9/iar/inc/tx_port.h b/ports/cortex_a9/iar/inc/tx_port.h index b67dafed..411dfe17 100644 --- a/ports/cortex_a9/iar/inc/tx_port.h +++ b/ports/cortex_a9/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A9/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -336,9 +339,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif @@ -382,7 +385,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A9/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_a9/iar/readme_threadx.txt b/ports/cortex_a9/iar/readme_threadx.txt index a9882a81..1b8ed694 100644 --- a/ports/cortex_a9/iar/readme_threadx.txt +++ b/ports/cortex_a9/iar/readme_threadx.txt @@ -534,6 +534,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for Cortex-A9 using IAR's ARM tools. diff --git a/ports/cortex_m0/ac5/inc/tx_port.h b/ports/cortex_m0/ac5/inc/tx_port.h index ce6a88c2..3a5afab1 100644 --- a/ports/cortex_m0/ac5/inc/tx_port.h +++ b/ports/cortex_m0/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -288,7 +291,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -318,7 +321,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/ac5/readme_threadx.txt b/ports/cortex_m0/ac5/readme_threadx.txt index 341d07e5..301aa31e 100644 --- a/ports/cortex_m0/ac5/readme_threadx.txt +++ b/ports/cortex_m0/ac5/readme_threadx.txt @@ -133,6 +133,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m0/ac6/inc/tx_port.h b/ports/cortex_m0/ac6/inc/tx_port.h index 6205113d..73a3cd4e 100644 --- a/ports/cortex_m0/ac6/inc/tx_port.h +++ b/ports/cortex_m0/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -335,7 +338,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -348,7 +351,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -359,7 +362,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/ac6/readme_threadx.txt b/ports/cortex_m0/ac6/readme_threadx.txt index 0cd9b4b7..a84dfa25 100644 --- a/ports/cortex_m0/ac6/readme_threadx.txt +++ b/ports/cortex_m0/ac6/readme_threadx.txt @@ -148,6 +148,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m0/gnu/inc/tx_port.h b/ports/cortex_m0/gnu/inc/tx_port.h index 63d7d427..798dbdb8 100644 --- a/ports/cortex_m0/gnu/inc/tx_port.h +++ b/ports/cortex_m0/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -50,6 +50,9 @@ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ /* 09-30-2020 William E. Lamie Modified comment(s), */ /* resulting in version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -337,7 +340,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -350,7 +353,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -361,7 +364,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m0/gnu/readme_threadx.txt b/ports/cortex_m0/gnu/readme_threadx.txt index cee11aac..6ef8a028 100644 --- a/ports/cortex_m0/gnu/readme_threadx.txt +++ b/ports/cortex_m0/gnu/readme_threadx.txt @@ -145,6 +145,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m0/iar/inc/tx_port.h b/ports/cortex_m0/iar/inc/tx_port.h index b8175994..2c671a74 100644 --- a/ports/cortex_m0/iar/inc/tx_port.h +++ b/ports/cortex_m0/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -349,7 +352,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/iar/readme_threadx.txt b/ports/cortex_m0/iar/readme_threadx.txt index f3eb001d..580a0736 100644 --- a/ports/cortex_m0/iar/readme_threadx.txt +++ b/ports/cortex_m0/iar/readme_threadx.txt @@ -148,6 +148,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m0/keil/inc/tx_port.h b/ports/cortex_m0/keil/inc/tx_port.h index 593e734b..68388adb 100644 --- a/ports/cortex_m0/keil/inc/tx_port.h +++ b/ports/cortex_m0/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M0/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -288,7 +291,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -318,7 +321,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M0/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m0/keil/readme_threadx.txt b/ports/cortex_m0/keil/readme_threadx.txt index ec9295a9..b1c1c0fd 100644 --- a/ports/cortex_m0/keil/readme_threadx.txt +++ b/ports/cortex_m0/keil/readme_threadx.txt @@ -139,6 +139,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m23/ac5/inc/tx_port.h b/ports/cortex_m23/ac5/inc/tx_port.h index 0ac7a7ff..7805b1eb 100644 --- a/ports/cortex_m23/ac5/inc/tx_port.h +++ b/ports/cortex_m23/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M23/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -377,7 +380,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -406,7 +409,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m23/ac5/readme_threadx.txt b/ports/cortex_m23/ac5/readme_threadx.txt index 7c60c2c4..1753a961 100644 --- a/ports/cortex_m23/ac5/readme_threadx.txt +++ b/ports/cortex_m23/ac5/readme_threadx.txt @@ -143,6 +143,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition 09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using AC5 tools. diff --git a/ports/cortex_m23/ac6/inc/tx_port.h b/ports/cortex_m23/ac6/inc/tx_port.h index 0781c2b0..0e3f401c 100644 --- a/ports/cortex_m23/ac6/inc/tx_port.h +++ b/ports/cortex_m23/ac6/inc/tx_port.h @@ -381,7 +381,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); diff --git a/ports/cortex_m23/ac6/readme_threadx.txt b/ports/cortex_m23/ac6/readme_threadx.txt index 66bf1636..45188e83 100644 --- a/ports/cortex_m23/ac6/readme_threadx.txt +++ b/ports/cortex_m23/ac6/readme_threadx.txt @@ -145,6 +145,12 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Added low power support + +03-02-2021 The following files were changed/added for version 6.1.5: + tx_port.h Added ULONG64_DEFINED 09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using AC6 tools. diff --git a/ports/cortex_m23/ac6/src/tx_thread_schedule.s b/ports/cortex_m23/ac6/src/tx_thread_schedule.s index 442a0567..dfe83983 100644 --- a/ports/cortex_m23/ac6/src/tx_thread_schedule.s +++ b/ports/cortex_m23/ac6/src/tx_thread_schedule.s @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s), added */ +/* low power code, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -253,11 +256,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting diff --git a/ports/cortex_m23/gnu/inc/tx_port.h b/ports/cortex_m23/gnu/inc/tx_port.h index 47850b84..d09ff80b 100644 --- a/ports/cortex_m23/gnu/inc/tx_port.h +++ b/ports/cortex_m23/gnu/inc/tx_port.h @@ -416,7 +416,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -429,7 +429,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); diff --git a/ports/cortex_m23/gnu/readme_threadx.txt b/ports/cortex_m23/gnu/readme_threadx.txt index 357990cb..435e3cb9 100644 --- a/ports/cortex_m23/gnu/readme_threadx.txt +++ b/ports/cortex_m23/gnu/readme_threadx.txt @@ -128,10 +128,16 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Added low power support + +03-02-2021 The following files were changed/added for version 6.1.5: + tx_port.h Added ULONG64_DEFINED + 12-31-2020 The following files were changed/added for port specific version 6.1.3: - tx_port.h Remove unneeded include files, use builtin functions, modified comments. diff --git a/ports/cortex_m23/gnu/src/tx_thread_schedule.s b/ports/cortex_m23/gnu/src/tx_thread_schedule.s index 9fefdb6e..24d64e64 100644 --- a/ports/cortex_m23/gnu/src/tx_thread_schedule.s +++ b/ports/cortex_m23/gnu/src/tx_thread_schedule.s @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M23/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s), added */ +/* low power code, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -253,11 +256,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting diff --git a/ports/cortex_m23/iar/readme_threadx.txt b/ports/cortex_m23/iar/readme_threadx.txt index 7f454e17..11717ae3 100644 --- a/ports/cortex_m23/iar/readme_threadx.txt +++ b/ports/cortex_m23/iar/readme_threadx.txt @@ -136,6 +136,13 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Added low power support + +03-02-2021 The following files were changed/added for version 6.1.5: + tx_port.h Added ULONG64_DEFINED + 09-30-2020 Initial ThreadX 6.1 version for Cortex-M23 using IAR's ARM tools. diff --git a/ports/cortex_m23/iar/src/tx_thread_schedule.s b/ports/cortex_m23/iar/src/tx_thread_schedule.s index 53b92102..2acf2f77 100644 --- a/ports/cortex_m23/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m23/iar/src/tx_thread_schedule.s @@ -32,6 +32,10 @@ EXTERN _tx_thread_secure_stack_context_save EXTERN _tx_thread_secure_mode_stack_allocate EXTERN _tx_thread_secure_mode_stack_free +#ifdef TX_LOW_POWER + EXTERN tx_low_power_enter + EXTERN tx_low_power_exit +#endif ; ; SECTION `.text`:CODE:NOROOT(2) @@ -41,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M23/IAR */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -74,6 +78,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 04-02-2021 Scott Larson Modified comment(s), added */ +;/* low power code, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -266,11 +273,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m3/ac5/inc/tx_port.h b/ports/cortex_m3/ac5/inc/tx_port.h index b68f3659..8f2ce32d 100644 --- a/ports/cortex_m3/ac5/inc/tx_port.h +++ b/ports/cortex_m3/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -329,7 +332,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/ac5/readme_threadx.txt b/ports/cortex_m3/ac5/readme_threadx.txt index 8b76305b..cc441de0 100644 --- a/ports/cortex_m3/ac5/readme_threadx.txt +++ b/ports/cortex_m3/ac5/readme_threadx.txt @@ -135,6 +135,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m3/ac6/inc/tx_port.h b/ports/cortex_m3/ac6/inc/tx_port.h index 71b052e8..c5a10d9c 100644 --- a/ports/cortex_m3/ac6/inc/tx_port.h +++ b/ports/cortex_m3/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -319,7 +322,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -332,7 +335,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -343,7 +346,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/ac6/readme_threadx.txt b/ports/cortex_m3/ac6/readme_threadx.txt index 81f47fb7..0772cdbf 100644 --- a/ports/cortex_m3/ac6/readme_threadx.txt +++ b/ports/cortex_m3/ac6/readme_threadx.txt @@ -146,6 +146,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m3/ghs/inc/tx_port.h b/ports/cortex_m3/ghs/inc/tx_port.h index 3ba5b354..f1b2c306 100644 --- a/ports/cortex_m3/ghs/inc/tx_port.h +++ b/ports/cortex_m3/ghs/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/GHS */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -324,7 +327,7 @@ typedef unsigned short USHORT; UINT _tx_thread_interrupt_disable(VOID); VOID _tx_thread_interrupt_restore(UINT previous_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); @@ -332,7 +335,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; /* Define ThreadX interrupt lockout and restore macros using asm macros. */ @@ -376,8 +379,8 @@ asm void restore_ints(int a) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/ghs/readme_threadx.txt b/ports/cortex_m3/ghs/readme_threadx.txt index f401b81e..ad1110fe 100644 --- a/ports/cortex_m3/ghs/readme_threadx.txt +++ b/ports/cortex_m3/ghs/readme_threadx.txt @@ -148,6 +148,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m3/gnu/inc/tx_port.h b/ports/cortex_m3/gnu/inc/tx_port.h index b5a75fd3..f70397a3 100644 --- a/ports/cortex_m3/gnu/inc/tx_port.h +++ b/ports/cortex_m3/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -50,6 +50,9 @@ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ /* 09-30-2020 William E. Lamie Modified comment(s), */ /* resulting in version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -321,7 +324,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -334,7 +337,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -345,7 +348,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m3/gnu/readme_threadx.txt b/ports/cortex_m3/gnu/readme_threadx.txt index cc9b14d2..ea4f807d 100644 --- a/ports/cortex_m3/gnu/readme_threadx.txt +++ b/ports/cortex_m3/gnu/readme_threadx.txt @@ -143,6 +143,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m3/iar/inc/tx_port.h b/ports/cortex_m3/iar/inc/tx_port.h index 6c18fab3..78c3575a 100644 --- a/ports/cortex_m3/iar/inc/tx_port.h +++ b/ports/cortex_m3/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -357,7 +360,7 @@ __istate_t interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/iar/readme_threadx.txt b/ports/cortex_m3/iar/readme_threadx.txt index 61eb7b07..24b8cd80 100644 --- a/ports/cortex_m3/iar/readme_threadx.txt +++ b/ports/cortex_m3/iar/readme_threadx.txt @@ -148,6 +148,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m3/keil/inc/tx_port.h b/ports/cortex_m3/keil/inc/tx_port.h index 39ed4e53..6aea4610 100644 --- a/ports/cortex_m3/keil/inc/tx_port.h +++ b/ports/cortex_m3/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/Keil */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -329,7 +332,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/Keil Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m3/keil/readme_threadx.txt b/ports/cortex_m3/keil/readme_threadx.txt index e7eeabb5..9cd94bc2 100644 --- a/ports/cortex_m3/keil/readme_threadx.txt +++ b/ports/cortex_m3/keil/readme_threadx.txt @@ -142,6 +142,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m33/ac5/inc/tx_port.h b/ports/cortex_m33/ac5/inc/tx_port.h index 855e0491..4cf5588e 100644 --- a/ports/cortex_m33/ac5/inc/tx_port.h +++ b/ports/cortex_m33/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -506,7 +509,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -535,7 +538,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m33/ac5/readme_threadx.txt b/ports/cortex_m33/ac5/readme_threadx.txt index 6846668b..65f9624e 100644 --- a/ports/cortex_m33/ac5/readme_threadx.txt +++ b/ports/cortex_m33/ac5/readme_threadx.txt @@ -204,6 +204,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using AC5 tools. diff --git a/ports/cortex_m33/ac6/inc/tx_port.h b/ports/cortex_m33/ac6/inc/tx_port.h index 061edfc5..c53e8b37 100644 --- a/ports/cortex_m33/ac6/inc/tx_port.h +++ b/ports/cortex_m33/ac6/inc/tx_port.h @@ -510,7 +510,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); diff --git a/ports/cortex_m33/ac6/readme_threadx.txt b/ports/cortex_m33/ac6/readme_threadx.txt index 74b488f8..e9a434ad 100644 --- a/ports/cortex_m33/ac6/readme_threadx.txt +++ b/ports/cortex_m33/ac6/readme_threadx.txt @@ -205,6 +205,13 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Added low power support + +03-02-2021 The following files were changed/added for version 6.1.5: + tx_port.h Added ULONG64_DEFINED + 09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using AC6 tools. diff --git a/ports/cortex_m33/ac6/src/tx_thread_schedule.S b/ports/cortex_m33/ac6/src/tx_thread_schedule.S index cd6b3e67..1f50c8bc 100644 --- a/ports/cortex_m33/ac6/src/tx_thread_schedule.S +++ b/ports/cortex_m33/ac6/src/tx_thread_schedule.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s), added */ +/* low power code, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -248,11 +251,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting diff --git a/ports/cortex_m33/gnu/inc/tx_port.h b/ports/cortex_m33/gnu/inc/tx_port.h index 4bfb27e3..653be90e 100644 --- a/ports/cortex_m33/gnu/inc/tx_port.h +++ b/ports/cortex_m33/gnu/inc/tx_port.h @@ -546,7 +546,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -559,7 +559,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); diff --git a/ports/cortex_m33/gnu/readme_threadx.txt b/ports/cortex_m33/gnu/readme_threadx.txt index 72f6e25e..51ab47f0 100644 --- a/ports/cortex_m33/gnu/readme_threadx.txt +++ b/ports/cortex_m33/gnu/readme_threadx.txt @@ -188,6 +188,13 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Added low power support + +03-02-2021 The following files were changed/added for version 6.1.5: + tx_port.h Added ULONG64_DEFINED + 09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using GNU tools. diff --git a/ports/cortex_m33/gnu/src/tx_thread_schedule.S b/ports/cortex_m33/gnu/src/tx_thread_schedule.S index 59717066..e88d6897 100644 --- a/ports/cortex_m33/gnu/src/tx_thread_schedule.S +++ b/ports/cortex_m33/gnu/src/tx_thread_schedule.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s), added */ +/* low power code, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -248,11 +251,25 @@ __tx_ts_wait: LDR r1, [r2] // Pickup the next thread to execute pointer STR r1, [r0] // Store it in the current pointer CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter // Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB // Ensure no outstanding memory transactions WFI // Wait for interrupt ISB // Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit // Exit low power mode + POP {r0-r3} +#endif + CPSIE i // Enable interrupts B __tx_ts_wait // Loop to continue waiting diff --git a/ports/cortex_m33/iar/readme_threadx.txt b/ports/cortex_m33/iar/readme_threadx.txt index 588fa29f..73895476 100644 --- a/ports/cortex_m33/iar/readme_threadx.txt +++ b/ports/cortex_m33/iar/readme_threadx.txt @@ -199,6 +199,13 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Added low power support + +03-02-2021 The following files were changed/added for version 6.1.5: + tx_port.h Added ULONG64_DEFINED + 09-30-2020 Initial ThreadX 6.1 version for Cortex-M33 using IAR's ARM tools. diff --git a/ports/cortex_m33/iar/src/tx_thread_schedule.s b/ports/cortex_m33/iar/src/tx_thread_schedule.s index e8962618..a00e03d3 100644 --- a/ports/cortex_m33/iar/src/tx_thread_schedule.s +++ b/ports/cortex_m33/iar/src/tx_thread_schedule.s @@ -32,6 +32,10 @@ EXTERN _tx_thread_secure_stack_context_save EXTERN _tx_thread_secure_mode_stack_allocate EXTERN _tx_thread_secure_mode_stack_free +#ifdef TX_LOW_POWER + EXTERN tx_low_power_enter + EXTERN tx_low_power_exit +#endif ; ; SECTION `.text`:CODE:NOROOT(2) @@ -41,7 +45,7 @@ ;/* FUNCTION RELEASE */ ;/* */ ;/* _tx_thread_schedule Cortex-M33/IAR */ -;/* 6.1 */ +;/* 6.1.6 */ ;/* AUTHOR */ ;/* */ ;/* Scott Larson, Microsoft Corporation */ @@ -74,6 +78,9 @@ ;/* DATE NAME DESCRIPTION */ ;/* */ ;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* 04-02-2021 Scott Larson Modified comment(s), added */ +;/* low power code, */ +;/* resulting in version 6.1.6 */ ;/* */ ;/**************************************************************************/ ;VOID _tx_thread_schedule(VOID) @@ -261,11 +268,25 @@ __tx_ts_wait: LDR r1, [r2] ; Pickup the next thread to execute pointer STR r1, [r0] ; Store it in the current pointer CBNZ r1, __tx_ts_ready ; If non-NULL, a new thread is ready! + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_enter ; Possibly enter low power mode + POP {r0-r3} +#endif + #ifdef TX_ENABLE_WFI DSB ; Ensure no outstanding memory transactions WFI ; Wait for interrupt ISB ; Ensure pipeline is flushed #endif + +#ifdef TX_LOW_POWER + PUSH {r0-r3} + BL tx_low_power_exit ; Exit low power mode + POP {r0-r3} +#endif + CPSIE i ; Enable interrupts B __tx_ts_wait ; Loop to continue waiting ; diff --git a/ports/cortex_m4/ac5/inc/tx_port.h b/ports/cortex_m4/ac5/inc/tx_port.h index c220665b..f4099d25 100644 --- a/ports/cortex_m4/ac5/inc/tx_port.h +++ b/ports/cortex_m4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -418,7 +421,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -454,7 +457,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/ac5/readme_threadx.txt b/ports/cortex_m4/ac5/readme_threadx.txt index 5f207167..7b91d12a 100644 --- a/ports/cortex_m4/ac5/readme_threadx.txt +++ b/ports/cortex_m4/ac5/readme_threadx.txt @@ -199,6 +199,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m4/ac6/inc/tx_port.h b/ports/cortex_m4/ac6/inc/tx_port.h index b6eb3929..d99bcbc8 100644 --- a/ports/cortex_m4/ac6/inc/tx_port.h +++ b/ports/cortex_m4/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -454,7 +457,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -467,7 +470,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -485,7 +488,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/ac6/readme_threadx.txt b/ports/cortex_m4/ac6/readme_threadx.txt index 7ae85c86..f09babe9 100644 --- a/ports/cortex_m4/ac6/readme_threadx.txt +++ b/ports/cortex_m4/ac6/readme_threadx.txt @@ -211,6 +211,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m4/ghs/inc/tx_port.h b/ports/cortex_m4/ghs/inc/tx_port.h index 3370092a..ce4c28ed 100644 --- a/ports/cortex_m4/ghs/inc/tx_port.h +++ b/ports/cortex_m4/ghs/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/GHS */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -324,7 +327,7 @@ typedef unsigned short USHORT; UINT _tx_thread_interrupt_disable(VOID); VOID _tx_thread_interrupt_restore(UINT previous_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); @@ -332,7 +335,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; /* Define ThreadX interrupt lockout and restore macros using asm macros. */ @@ -383,8 +386,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GHS Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GHS Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/ghs/readme_threadx.txt b/ports/cortex_m4/ghs/readme_threadx.txt index 4fa2dff2..86a49522 100644 --- a/ports/cortex_m4/ghs/readme_threadx.txt +++ b/ports/cortex_m4/ghs/readme_threadx.txt @@ -225,6 +225,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m4/gnu/inc/tx_port.h b/ports/cortex_m4/gnu/inc/tx_port.h index 604e27ba..6b65e04c 100644 --- a/ports/cortex_m4/gnu/inc/tx_port.h +++ b/ports/cortex_m4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -50,6 +50,9 @@ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ /* 09-30-2020 William E. Lamie Modified comment(s), */ /* resulting in version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -456,7 +459,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -469,7 +472,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -487,7 +490,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m4/gnu/readme_threadx.txt b/ports/cortex_m4/gnu/readme_threadx.txt index f3df3a68..383c72fd 100644 --- a/ports/cortex_m4/gnu/readme_threadx.txt +++ b/ports/cortex_m4/gnu/readme_threadx.txt @@ -208,6 +208,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m4/iar/inc/tx_port.h b/ports/cortex_m4/iar/inc/tx_port.h index 81656f62..11955598 100644 --- a/ports/cortex_m4/iar/inc/tx_port.h +++ b/ports/cortex_m4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -477,7 +480,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/iar/readme_threadx.txt b/ports/cortex_m4/iar/readme_threadx.txt index 13fcc758..cd999e46 100644 --- a/ports/cortex_m4/iar/readme_threadx.txt +++ b/ports/cortex_m4/iar/readme_threadx.txt @@ -214,6 +214,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m4/keil/inc/tx_port.h b/ports/cortex_m4/keil/inc/tx_port.h index 85489c1a..e1c5ac2e 100644 --- a/ports/cortex_m4/keil/inc/tx_port.h +++ b/ports/cortex_m4/keil/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/Keil */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -418,7 +421,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -454,7 +457,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/Keil Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m4/keil/readme_threadx.txt b/ports/cortex_m4/keil/readme_threadx.txt index a35fe950..12848341 100644 --- a/ports/cortex_m4/keil/readme_threadx.txt +++ b/ports/cortex_m4/keil/readme_threadx.txt @@ -200,6 +200,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m7/ac5/inc/tx_port.h b/ports/cortex_m7/ac5/inc/tx_port.h index e621a41a..21483048 100644 --- a/ports/cortex_m7/ac5/inc/tx_port.h +++ b/ports/cortex_m7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -418,7 +421,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -454,7 +457,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC5 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/ac5/readme_threadx.txt b/ports/cortex_m7/ac5/readme_threadx.txt index db1def58..24dd565c 100644 --- a/ports/cortex_m7/ac5/readme_threadx.txt +++ b/ports/cortex_m7/ac5/readme_threadx.txt @@ -199,6 +199,10 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + tx_thread_schedule.s Fix compilation error + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m7/ac6/inc/tx_port.h b/ports/cortex_m7/ac6/inc/tx_port.h index f73dc482..349eea9c 100644 --- a/ports/cortex_m7/ac6/inc/tx_port.h +++ b/ports/cortex_m7/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -451,7 +454,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -464,7 +467,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -482,7 +485,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/ac6/readme_threadx.txt b/ports/cortex_m7/ac6/readme_threadx.txt index 9fd4abc2..5519194e 100644 --- a/ports/cortex_m7/ac6/readme_threadx.txt +++ b/ports/cortex_m7/ac6/readme_threadx.txt @@ -202,6 +202,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m7/ghs/inc/tx_port.h b/ports/cortex_m7/ghs/inc/tx_port.h index acab31b7..82442c64 100644 --- a/ports/cortex_m7/ghs/inc/tx_port.h +++ b/ports/cortex_m7/ghs/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/GHS */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -324,7 +327,7 @@ typedef unsigned short USHORT; UINT _tx_thread_interrupt_disable(VOID); VOID _tx_thread_interrupt_restore(UINT previous_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); @@ -332,7 +335,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; /* Define ThreadX interrupt lockout and restore macros using asm macros. */ @@ -383,8 +386,8 @@ void tx_thread_fpu_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GHS Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GHS Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/ghs/readme_threadx.txt b/ports/cortex_m7/ghs/readme_threadx.txt index e90e0d9e..22466c4e 100644 --- a/ports/cortex_m7/ghs/readme_threadx.txt +++ b/ports/cortex_m7/ghs/readme_threadx.txt @@ -225,6 +225,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m7/gnu/inc/tx_port.h b/ports/cortex_m7/gnu/inc/tx_port.h index 6fdefd0b..cc552c1e 100644 --- a/ports/cortex_m7/gnu/inc/tx_port.h +++ b/ports/cortex_m7/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -50,6 +50,9 @@ /* 05-19-2020 William E. Lamie Initial Version 6.0 */ /* 09-30-2020 William E. Lamie Modified comment(s), */ /* resulting in version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -453,7 +456,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -466,7 +469,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -484,7 +487,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_m7/gnu/readme_threadx.txt b/ports/cortex_m7/gnu/readme_threadx.txt index 2afb4d21..7f5ace0c 100644 --- a/ports/cortex_m7/gnu/readme_threadx.txt +++ b/ports/cortex_m7/gnu/readme_threadx.txt @@ -199,6 +199,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_m7/iar/inc/tx_port.h b/ports/cortex_m7/iar/inc/tx_port.h index d465e382..c86f6c0f 100644 --- a/ports/cortex_m7/iar/inc/tx_port.h +++ b/ports/cortex_m7/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -483,7 +486,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_m7/iar/readme_threadx.txt b/ports/cortex_m7/iar/readme_threadx.txt index 97a1c926..9d178cfa 100644 --- a/ports/cortex_m7/iar/readme_threadx.txt +++ b/ports/cortex_m7/iar/readme_threadx.txt @@ -206,6 +206,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 03-02-2021 The following files were changed/added for version 6.1.5: tx_thread_schedule.s Added low power feature diff --git a/ports/cortex_r4/ac5/inc/tx_port.h b/ports/cortex_r4/ac5/inc/tx_port.h index d73a6c82..24f67c58 100644 --- a/ports/cortex_r4/ac5/inc/tx_port.h +++ b/ports/cortex_r4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -324,7 +327,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac5/readme_threadx.txt b/ports/cortex_r4/ac5/readme_threadx.txt index 01b3e2da..d27aa166 100644 --- a/ports/cortex_r4/ac5/readme_threadx.txt +++ b/ports/cortex_r4/ac5/readme_threadx.txt @@ -539,6 +539,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-R4 using AC5 tools. diff --git a/ports/cortex_r4/ac6/inc/tx_port.h b/ports/cortex_r4/ac6/inc/tx_port.h index 991db05d..b2feb970 100644 --- a/ports/cortex_r4/ac6/inc/tx_port.h +++ b/ports/cortex_r4/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -268,7 +271,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -299,7 +302,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -327,7 +330,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/ac6/readme_threadx.txt b/ports/cortex_r4/ac6/readme_threadx.txt index ab6eebfa..b861033f 100644 --- a/ports/cortex_r4/ac6/readme_threadx.txt +++ b/ports/cortex_r4/ac6/readme_threadx.txt @@ -382,6 +382,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-R4 using ARM tools. diff --git a/ports/cortex_r4/gnu/inc/tx_port.h b/ports/cortex_r4/gnu/inc/tx_port.h index 8ae22b85..7e95871a 100644 --- a/ports/cortex_r4/gnu/inc/tx_port.h +++ b/ports/cortex_r4/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -306,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/gnu/readme_threadx.txt b/ports/cortex_r4/gnu/readme_threadx.txt index 6bd41bcc..06712f8a 100644 --- a/ports/cortex_r4/gnu/readme_threadx.txt +++ b/ports/cortex_r4/gnu/readme_threadx.txt @@ -486,6 +486,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-R4 using GNU tools. diff --git a/ports/cortex_r4/green/inc/tx_port.h b/ports/cortex_r4/green/inc/tx_port.h index c066849d..446ef388 100644 --- a/ports/cortex_r4/green/inc/tx_port.h +++ b/ports/cortex_r4/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -296,7 +299,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -304,7 +307,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -381,8 +384,8 @@ asm void restore_ints(int a) /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r4/green/readme_threadx.txt b/ports/cortex_r4/green/readme_threadx.txt index 7b358c23..f0fe2220 100644 --- a/ports/cortex_r4/green/readme_threadx.txt +++ b/ports/cortex_r4/green/readme_threadx.txt @@ -500,6 +500,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-R4/Green Hills port. diff --git a/ports/cortex_r4/iar/inc/tx_port.h b/ports/cortex_r4/iar/inc/tx_port.h index 701b0308..bfa74d4d 100644 --- a/ports/cortex_r4/iar/inc/tx_port.h +++ b/ports/cortex_r4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -319,9 +322,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -364,7 +367,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r4/iar/readme_threadx.txt b/ports/cortex_r4/iar/readme_threadx.txt index 32832714..400eaa1f 100644 --- a/ports/cortex_r4/iar/readme_threadx.txt +++ b/ports/cortex_r4/iar/readme_threadx.txt @@ -416,6 +416,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version 6.1 for Cortex-R4 using IAR's ARM tools. diff --git a/ports/cortex_r5/ac5/inc/tx_port.h b/ports/cortex_r5/ac5/inc/tx_port.h index a6cf6036..d0257924 100644 --- a/ports/cortex_r5/ac5/inc/tx_port.h +++ b/ports/cortex_r5/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -265,7 +268,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -296,7 +299,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -317,7 +320,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac5/readme_threadx.txt b/ports/cortex_r5/ac5/readme_threadx.txt index d6b8b6d7..9910f87e 100644 --- a/ports/cortex_r5/ac5/readme_threadx.txt +++ b/ports/cortex_r5/ac5/readme_threadx.txt @@ -519,6 +519,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-R5 using AC5 tools. diff --git a/ports/cortex_r5/ac6/inc/tx_port.h b/ports/cortex_r5/ac6/inc/tx_port.h index e27c542d..ba23733f 100644 --- a/ports/cortex_r5/ac6/inc/tx_port.h +++ b/ports/cortex_r5/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -306,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/ac6/readme_threadx.txt b/ports/cortex_r5/ac6/readme_threadx.txt index bb3804c6..f2b1b0a4 100644 --- a/ports/cortex_r5/ac6/readme_threadx.txt +++ b/ports/cortex_r5/ac6/readme_threadx.txt @@ -315,6 +315,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-R5 using AC6 tools. diff --git a/ports/cortex_r5/gnu/inc/tx_port.h b/ports/cortex_r5/gnu/inc/tx_port.h index ec06dd37..204e623c 100644 --- a/ports/cortex_r5/gnu/inc/tx_port.h +++ b/ports/cortex_r5/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -272,14 +275,14 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save, tx_temp; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save, tx_temp; #ifdef TX_ENABLE_FIQ_SUPPORT #define TX_DISABLE asm volatile (" MRS %0,CPSR; CPSID if ": "=r" (interrupt_save) ); @@ -306,7 +309,7 @@ unsigned int _tx_thread_interrupt_restore(UINT old_posture); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/gnu/readme_threadx.txt b/ports/cortex_r5/gnu/readme_threadx.txt index 148bf630..a9a28305 100644 --- a/ports/cortex_r5/gnu/readme_threadx.txt +++ b/ports/cortex_r5/gnu/readme_threadx.txt @@ -486,6 +486,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-R5 using GNU tools. diff --git a/ports/cortex_r5/green/inc/tx_port.h b/ports/cortex_r5/green/inc/tx_port.h index c46ef3b8..54637fde 100644 --- a/ports/cortex_r5/green/inc/tx_port.h +++ b/ports/cortex_r5/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -307,7 +310,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -391,8 +394,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r5/green/readme_threadx.txt b/ports/cortex_r5/green/readme_threadx.txt index f2afb94d..62383547 100644 --- a/ports/cortex_r5/green/readme_threadx.txt +++ b/ports/cortex_r5/green/readme_threadx.txt @@ -517,6 +517,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-R5/Green Hills port. diff --git a/ports/cortex_r5/iar/inc/tx_port.h b/ports/cortex_r5/iar/inc/tx_port.h index f2a990ed..50e6f472 100644 --- a/ports/cortex_r5/iar/inc/tx_port.h +++ b/ports/cortex_r5/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R5/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -319,9 +322,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -364,7 +367,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R5/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports/cortex_r5/iar/readme_threadx.txt b/ports/cortex_r5/iar/readme_threadx.txt index e5bb364f..fd6174a7 100644 --- a/ports/cortex_r5/iar/readme_threadx.txt +++ b/ports/cortex_r5/iar/readme_threadx.txt @@ -416,6 +416,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX version for Cortex-R5 using IAR's ARM tools. diff --git a/ports/cortex_r7/green/inc/tx_port.h b/ports/cortex_r7/green/inc/tx_port.h index 6ed7fd94..8802da2b 100644 --- a/ports/cortex_r7/green/inc/tx_port.h +++ b/ports/cortex_r7/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R7/Green Hills */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -299,7 +302,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_disable(void); void _tx_thread_interrupt_restore(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); @@ -307,7 +310,7 @@ void _tx_thread_interrupt_restore(unsigned int new_po #else -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #if defined(__GHS_VERSION_NUMBER) && (__GHS_VERSION_NUMBER >= 350) @@ -391,8 +394,8 @@ void tx_thread_vfp_disable(void); /* Define the version ID of ThreadX. This may be utilized by the application. */ #ifdef TX_THREAD_INIT -CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R7/Green Hills Version 6.1 *"; +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R7/Green Hills Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/cortex_r7/green/readme_threadx.txt b/ports/cortex_r7/green/readme_threadx.txt index 4fd097d4..6f498f11 100644 --- a/ports/cortex_r7/green/readme_threadx.txt +++ b/ports/cortex_r7/green/readme_threadx.txt @@ -517,6 +517,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 05/19/2020 Initial ThreadX version of Cortex-R7/Green Hills port. diff --git a/ports/risc-v32/iar/inc/tx_port.h b/ports/risc-v32/iar/inc/tx_port.h index f2db9c14..670ebf57 100644 --- a/ports/risc-v32/iar/inc/tx_port.h +++ b/ports/risc-v32/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h RISC-V32/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -235,7 +238,7 @@ typedef unsigned short USHORT; unsigned int _tx_thread_interrupt_control(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -263,7 +266,7 @@ unsigned int _tx_thread_interrupt_control(uns #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RISC-V32/IAR Version G6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX RISC-V32/IAR Version G6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/risc-v32/iar/readme_threadx.txt b/ports/risc-v32/iar/readme_threadx.txt index 5b915792..99504275 100644 --- a/ports/risc-v32/iar/readme_threadx.txt +++ b/ports/risc-v32/iar/readme_threadx.txt @@ -233,6 +233,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 08/09/2020 Initial ThreadX version for RISC-V using IAR Tools. diff --git a/ports/rxv2/ccrx/inc/tx_port.h b/ports/rxv2/ccrx/inc/tx_port.h index 8c443e84..332a7711 100644 --- a/ports/rxv2/ccrx/inc/tx_port.h +++ b/ports/rxv2/ccrx/inc/tx_port.h @@ -222,7 +222,7 @@ static void _tx_thread_interrupt_restore(UINT old_posture){ MVTC r2,PSW ; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); diff --git a/ports/rxv2/ccrx/readme_threadx.txt b/ports/rxv2/ccrx/readme_threadx.txt index c496fbb3..c1544d5b 100644 --- a/ports/rxv2/ccrx/readme_threadx.txt +++ b/ports/rxv2/ccrx/readme_threadx.txt @@ -161,6 +161,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition 12-31-2020 Initial ThreadX release for the RXv2 using CC-RXX tools, version 6.1.3 diff --git a/ports/rxv2/gnu/readme_threadx.txt b/ports/rxv2/gnu/readme_threadx.txt index 5baf5961..d548a556 100644 --- a/ports/rxv2/gnu/readme_threadx.txt +++ b/ports/rxv2/gnu/readme_threadx.txt @@ -157,6 +157,8 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition 12-31-2020 Initial ThreadX release for the RXv2 using GNURX tools, version 6.1.3 diff --git a/ports/rxv2/iar/readme_threadx.txt b/ports/rxv2/iar/readme_threadx.txt index 0c0afd29..b672d4ff 100644 --- a/ports/rxv2/iar/readme_threadx.txt +++ b/ports/rxv2/iar/readme_threadx.txt @@ -154,6 +154,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 12-31-2020 Initial ThreadX release for the RXv2using IAR tools, version 6.1.3 diff --git a/ports/xtensa/xcc/inc/tx_port.h b/ports/xtensa/xcc/inc/tx_port.h index 9438a7c8..d06f927e 100644 --- a/ports/xtensa/xcc/inc/tx_port.h +++ b/ports/xtensa/xcc/inc/tx_port.h @@ -35,7 +35,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */ +/* 11-09-2020 Cadence Design Systems Initial Version 6.1.2 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -436,7 +439,7 @@ extern void _xt_coproc_release(void * coproc_sa_base); extern unsigned int _tx_thread_interrupt_control(unsigned int new_posture); -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; #ifdef TX_DISABLE_INLINE_MACROS #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); @@ -468,7 +471,7 @@ extern int xt_timer_intnum; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. * Azure RTOS Xtensa Version 6.1.3 *"; + "Copyright (c) Microsoft Corporation. * Azure RTOS Xtensa Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports/xtensa/xcc/readme_threadx.txt b/ports/xtensa/xcc/readme_threadx.txt index 90fc92d7..29413318 100644 --- a/ports/xtensa/xcc/readme_threadx.txt +++ b/ports/xtensa/xcc/readme_threadx.txt @@ -771,241 +771,11 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: -04/26/2019 ThreadX Xtensa version 5.12. This release adds support for the Xtensa XEA3 - exception architecture and the Xtensa NX processor family. The following - changes/enhancements are included: - Makefile Changes to support building for Xtensa - XEA3 configurations. - xtensa_vectors_xea3.S New file added, interrupt and exception - dispatch code for XEA3. +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition - tx_api_asm.h Changes and additions to support the Xtensa - tx_port.h XEA3 exception architecture. - xtensa_api.h - xtensa_context.h - xtensa_rtos.h - xtensa_timer.h - tx_initialize_low_level.c - tx_thread_context_restore.S - tx_thread_context_save.S - tx_thread_interrupt_control.c - tx_thread_schedule.S - tx_thread_stack_build.S - tx_thread_system_return.S - tx_timer_interrupt.S - tx_xtensa_stack_error_handler.c - xtensa_context.S - xtensa_coproc_handler.S - xtensa_init.c - xtensa_intr.c - xtensa_intr_asm.S - xtensa_intr_wrapper.c - xtensa_vectors.S - -08/01/2017 ThreadX Xtensa version 5.11. This release includes the following changes - and enhancements/modifications: - - Makefile Build execution profile module only - if the module has been selected. - tx_api_asm.h Changed field offsets for Xtensa- - specific fields in TCB. - tx_clib_lock.c Added thread wrapper function to handle - C library setup and cleanup properly. - tx_port.h Redefined macros as required as part of - the redesigned C library thread safety support. - tx_xtensa_stack_error_handler.c Included required headers. - xtensa_intr_asm.S Placed interrupt stack explicitly in .data - section. - xtensa_intr.c Fixed return values for set exception handler - and set interrupt handler functions. - xtensa_overlay_os_hook.c Added conditions so that code is now compiled - only if overlay option is selected. - xtensa_timer.h Include TIE header files conditionally. - *.h Modified comment(s). - *.S Modified comment(s). - -03/22/2016 ThreadX Xtensa version 5.10. This release includes the following changes - and enhancements: separate user-configurable interrupt stack, support for - Xtensa C library (xclib) thread safety, minor changes to the support for - the Execution Profile kit, and minor changes to remove some compiler warnings. - This release includes the following modifications: - - tx_port.h Added support for XCLIB C library thread safety, - added support for separate interrupt stack, - added support Execution Profile Kit (EPK), and - updated version string. - tx_initialize_low_level.S Replaced by tx_initialize_low_level.c, added - support for XCLIB C library thread safety, - added support for separate interrupt stack and - moved setup of thread stack check callback in here - from demo program. - tx_thread_context_restore.S Added support for Execution Profile Kit (EPK). - tx_thread_schedule.S Added support for Execution Profile Kit (EPK), and - added support for XCLIB C library thread safety. - tx_thread_system_return.S Added support for Execution Profile Kit (EPK). - tx_api_asm.h Added support for XCLIB C library thread safety. - tx_clib_lock.c Added support for XCLIB C library thread safety. - xtensa_api.h Corrected issues with function declarations. - xtensa_context.h Corrected build errors when TX_NO_TIMER defined. - xtensa_intr_asm.S Added support for separate interrupt stack. - xtensa_overlay_os_hook.c Corrected compiler warnings. - xtensa_vectors.S Added support for Execution Profile Kit (EPK), and - added compiler warnings. - xtensa_timer.h Added timer related defines to simplify timer setup code. - Makefile Various misc updates, removed some obsolete targets. - tx_intr_demo.c Added support for XCLIB C library thread safety. - *.h Modified comment(s). - *.S Modified comment(s). - -06/01/2015 ThreadX Xtensa version 5.9. This release includes the following modifications: - - tx_port.h Changed default timer thread stack size logic, - updated coprocessor support, and updated - version string. - tx_initialize_low_level.S Modified timer setup. - tx_thread_schedule.S Added setup for timing test option. - tx_thread_stack_build.S Added virtual priority mask setup. - tx_thread_system_return.S Added support for coprocessor save. - xtensa_context.h Added additional interrupt support, including - coprocessor save/restore. - xtensa_context.S Added additional interrupt support, including - coprocessor save/restore. - xtensa_overlay_os_hook.c Added include of overlay.h. - xtensa_vectors.S Added new interrupt support and functionality. - xtensa_api.h Added new file for this release. - xtensa_intr.c Added new file for this release. - xtensa_intr_asm.S Added new file for this release. - *.h Modified comment(s). - *.S Modified comment(s). - -07/31/2014 ThreadX Xtensa version 5.8. This release includes the following modifications: - - tx_port.h Added in-line interrupt disable and - restore macros, and updated version string. - tx_thread_system_return.S Added context save optimization. - xtensa_context.h Added overlay support. - xtensa_context.S Added overlay support. - xtensa_overlay_os_hook.c Added new file for overlay support. - *.h Modified comment(s). - *.S Modified comment(s). - -10/01/2011 ThreadX Xtensa version 5.7. This release includes the following modifications: - - tx_port.h Updated version string. - tx_thread_context_restore.S Changed to 16-bit save of tx_thread_cp_state. - tx_thread_schedule.S Changed to 16-bit restore of tx_thread_cp_state. - tx_thread_system_return.S Changed to 16-bit save of tx_thread_cp_state. - xtensa_context.h Modified alignment constants and macros. - xtensa_context.S Removed initial alignment adjustment. - *.h Modified comment(s). - *.S Modified comment(s). - -07/15/2011 ThreadX Xtensa version 5.6. This release includes the following modifications: - - tx_port.h Modified control block and thread processing - extensions to be compatible with all cores, - and updated version string. - - tx_clib_lock.c Added code to not use priority inheritance when - running the regression testsuite. - tx_timer_interrupt.S Added code to optionally call user timer ISR. - xtensa_timer.h Adjusted timer for testsuite to pass under - simulation. - xtensa_vectors.S Fixed several issues in coprocessor context - switch code. - *.S Modified comment(s). - -01/28/2011 ThreadX Xtensa version 5.5. This release includes the following modifications: - - tx_port.h Changed version ID and added alignment padding. - tx_thread_stack_build.s Added code to clear solicited stack frame flag. - xtensa_context.h Added logic to support Xtensa processors with - load/store units wider than 128-bits - xtensa_context.s Added logic to support Xtensa processors with - load/store units wider than 128-bits - xtensa_vectors.s Added logic to support Xtensa processors with - load/store units wider than 128-bits - *.s Modified comment(s). - -05/01/2010 ThreadX Xtensa version 5.4. This release includes the following modifications: - - tx_port.h Changed version ID. - tx_thread_system_return.s Changed code to preserve current time-slice value. - *.s Modified comment(s). - -07/15/2009 ThreadX Xtensa version 5.3. It includes the following modifications: - - tx_port.h Added include of string.h, added GDBIO - constants, and modified version ID string. - tx_clib_lock.c Added include of stdlib.h. - tx_thread_context_save.S Added "XCHAL_CP_NUM > 0" conditional around - _tx_thread_coproc_state function definition. - tx_thread_schedule.S Removed #else conditional and replaced RET - macro with assembly code. - tx_thread_system_return.S Replaced ENTRY macro with assembly code. - xtensa_context.h Modified call frame offsets. - xtensa_timer.h Modified timer constants and added extern - for _xt_tick_diviso_init function. - xtensa_vectors.S Replaced exit macros. - tx*.h Modified comment(s). - tx*.c Modified comment(s). - tx*.S Modified comment(s). - -06/18/2008 ThreadX Xtensa version 5.2. It includes the following modifications: - - tx_port.h Added "extern" to the interrupt control - function prototype, and modified - version ID string. - tx_api_asm.h Fixed bug whereby tx_thread_cp_state - was off by 1 word and overlapped - tx_thread_name if TX_THREAD_SAFE_CLIB - was not defined. - xtensa_vectors.S Strengthened syncs for strict ISA - conformance. Aligned exit dispatchers. - tx*.h Modified comment(s). - tx*.c Modified comment(s). - tx*.S Modified comment(s). - -04/02/2007 ThreadX Xtensa version 5.1. This release adds minor enhancements - and supports evaluation boards via a new board independent "XTBSP" - API (allowing ThreadX to take advantage of any supported board) - and deprecates board-specific code for the obsolete XT2000. - It includes the following modifications: - - tx_port.h Co-proc check uses XCHAL_CP_NUM, - deprecated XT_XT2000 option, - included tx_user.h first, and - made TX_MAX_PRIORITIES visible - to assembler code. - tx_xtensa_stack_error_handler.c Accessed board's display via API - and deprecated XT_XT2000 option. - tx_initialize_low_level.S Co-proc check uses XCHAL_CP_NUM, - modified timer setup and - supported TX_NO_TIMER. - tx_thread_context_restore.S Co-proc check uses XCHAL_CP_NUM. - tx_thread_schedule.S Co-proc check uses XCHAL_CP_NUM. - tx_thread_system_return.S Co-proc check uses XCHAL_CP_NUM. - tx_timer_interrupt.S Use tick divisor computed via - API and support TX_NO_TIMER. - xtensa_context.h Co-proc check uses XCHAL_CP_NUM. - xtensa_context.S Co-proc check uses XCHAL_CP_NUM. - xtensa_init.c Added new initialization code to - set tick timer using board API. - xtensa_rtos.h Allowed tx_user.h macros to - affect Xtensa-generic macros and - supported TX_NO_TIMER. - xtensa_timer.h Updated timer configuration - logic and supported TX_NO_TIMER. - xtensa_vectors.S Co-proc check uses XCHAL_CP_NUM - and updated logic for long jumps - and supported TX_NO_TIMER. - tx*.h Modified comment(s). - tx*.c Modified comment(s). - tx*.S Modified comment(s). - -10/10/2006 Initial ThreadX version for Xtensa configurable processors - and Diamond pre-configured processors using Xtensa Tools. +12-31-2020 Initial Version 6.1.3 Copyright(c) 1996-2020 Microsoft Corporation diff --git a/ports_module/cortex-a7/ac5/inc/tx_port.h b/ports_module/cortex-a7/ac5/inc/tx_port.h index d07741ca..15fdff8c 100644 --- a/ports_module/cortex-a7/ac5/inc/tx_port.h +++ b/ports_module/cortex-a7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A7/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -283,7 +286,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -314,7 +317,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -342,7 +345,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A7/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m3/ac5/inc/tx_port.h b/ports_module/cortex-m3/ac5/inc/tx_port.h index 47490dfa..b190243b 100644 --- a/ports_module/cortex-m3/ac5/inc/tx_port.h +++ b/ports_module/cortex-m3/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M3/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -424,7 +427,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); diff --git a/ports_module/cortex-m3/ac5/inc/txm_module_port.h b/ports_module/cortex-m3/ac5/inc/txm_module_port.h index c61a9346..667db1e4 100644 --- a/ports_module/cortex-m3/ac5/inc/txm_module_port.h +++ b/ports_module/cortex-m3/ac5/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/MPU/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,7 +40,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s) and */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -307,12 +310,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m3/ac6/inc/tx_port.h b/ports_module/cortex-m3/ac6/inc/tx_port.h index 27f69bbf..58db3ea3 100644 --- a/ports_module/cortex-m3/ac6/inc/tx_port.h +++ b/ports_module/cortex-m3/ac6/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -345,7 +348,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -358,7 +361,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -369,7 +372,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m3/ac6/inc/txm_module_port.h b/ports_module/cortex-m3/ac6/inc/txm_module_port.h index 139ed25a..90975e6c 100644 --- a/ports_module/cortex-m3/ac6/inc/txm_module_port.h +++ b/ports_module/cortex-m3/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/MPU/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,7 +40,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* 09-30-2020 Andres Mlinar Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s) and */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -314,12 +317,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m3/gnu/inc/tx_port.h b/ports_module/cortex-m3/gnu/inc/tx_port.h index 18624cbd..8d6be046 100644 --- a/ports_module/cortex-m3/gnu/inc/tx_port.h +++ b/ports_module/cortex-m3/gnu/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -338,7 +341,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -351,7 +354,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -362,7 +365,7 @@ unsigned int interrupt_save; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m3/gnu/inc/txm_module_port.h b/ports_module/cortex-m3/gnu/inc/txm_module_port.h index 68632492..e16ad79a 100644 --- a/ports_module/cortex-m3/gnu/inc/txm_module_port.h +++ b/ports_module/cortex-m3/gnu/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/MPU/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -40,7 +40,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s) and */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -292,12 +295,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m3/iar/inc/txm_module_port.h b/ports_module/cortex-m3/iar/inc/txm_module_port.h index 6e228d4d..04f97122 100644 --- a/ports_module/cortex-m3/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m3/iar/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M3/MPU/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -41,6 +41,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s) and */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -293,12 +296,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m4/ac5/inc/tx_port.h b/ports_module/cortex-m4/ac5/inc/tx_port.h index 07d26e6a..ebe5e751 100644 --- a/ports_module/cortex-m4/ac5/inc/tx_port.h +++ b/ports_module/cortex-m4/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M4/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -424,7 +427,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); diff --git a/ports_module/cortex-m4/ac5/inc/txm_module_port.h b/ports_module/cortex-m4/ac5/inc/txm_module_port.h index ae5a90fb..b9d2ea5b 100644 --- a/ports_module/cortex-m4/ac5/inc/txm_module_port.h +++ b/ports_module/cortex-m4/ac5/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/MPU/AC5 */ -/* 6.1.2 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* 11-09-2020 Scott Larson Modified comment(s), */ /* increase kernel stack size, */ /* resulting in version 6.1.2 */ +/* 04-02-2021 Scott Larson Modified comment(s), */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -300,12 +303,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m4/ac6/inc/tx_port.h b/ports_module/cortex-m4/ac6/inc/tx_port.h index 38d00353..7a5a13a1 100644 --- a/ports_module/cortex-m4/ac6/inc/tx_port.h +++ b/ports_module/cortex-m4/ac6/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -476,7 +479,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -489,7 +492,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -507,7 +510,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m4/ac6/inc/txm_module_port.h b/ports_module/cortex-m4/ac6/inc/txm_module_port.h index c504163b..0b144b3b 100644 --- a/ports_module/cortex-m4/ac6/inc/txm_module_port.h +++ b/ports_module/cortex-m4/ac6/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/MPU/AC6 */ -/* 6.1.2 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -43,6 +43,9 @@ /* 09-30-2020 Andres Mlinar Initial Version 6.1 */ /* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ +/* 04-02-2021 Scott Larson Modified comment(s), */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -294,12 +297,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m4/gnu/inc/tx_port.h b/ports_module/cortex-m4/gnu/inc/tx_port.h index 1cf859e1..4c67e788 100644 --- a/ports_module/cortex-m4/gnu/inc/tx_port.h +++ b/ports_module/cortex-m4/gnu/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -473,7 +476,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -486,7 +489,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -504,7 +507,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M4/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m4/gnu/inc/txm_module_port.h b/ports_module/cortex-m4/gnu/inc/txm_module_port.h index 554a3aad..68419fc1 100644 --- a/ports_module/cortex-m4/gnu/inc/txm_module_port.h +++ b/ports_module/cortex-m4/gnu/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/MPU/GNU */ -/* 6.1.2 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -43,6 +43,9 @@ /* 09-30-2020 Scott Larson Initial Version 6.1 */ /* 11-09-2020 Scott Larson Modified comment(s), */ /* resulting in version 6.1.2 */ +/* 04-02-2021 Scott Larson Modified comment(s), */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -294,12 +297,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m4/iar/inc/txm_module_port.h b/ports_module/cortex-m4/iar/inc/txm_module_port.h index 5c58bef3..6630204f 100644 --- a/ports_module/cortex-m4/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m4/iar/inc/txm_module_port.h @@ -26,7 +26,7 @@ /* APPLICATION INTERFACE DEFINITION RELEASE */ /* */ /* txm_module_port.h Cortex-M4/MPU/IAR */ -/* 6.1.2 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -44,6 +44,9 @@ /* 11-09-2020 Scott Larson Modified comment(s), */ /* increase kernel stack size, */ /* resulting in version 6.1.2 */ +/* 04-02-2021 Scott Larson Modified comment(s), */ +/* added check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -296,12 +299,14 @@ typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT /* Define macro to make sure object is inside the module's data. */ #define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + /* Check for overflow. */ \ + (((obj_ptr) < ((obj_ptr) + (obj_size))) && \ /* Check if it's inside module data. */ \ - ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ + ((((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && \ (((obj_ptr) + (obj_size)) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) || \ /* Check if it's inside shared memory. */ \ (((obj_ptr) >= (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address) && \ - (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length)))) + (((obj_ptr) + (obj_size)) <= (ALIGN_TYPE) (module_instance -> txm_module_instance_shared_memory_address + module_instance -> txm_module_instance_shared_memory_length))))) /* Define some internal prototypes to this module port. */ diff --git a/ports_module/cortex-m7/ac5/inc/tx_port.h b/ports_module/cortex-m7/ac5/inc/tx_port.h index 0962e1d9..ee66d1fe 100644 --- a/ports_module/cortex-m7/ac5/inc/tx_port.h +++ b/ports_module/cortex-m7/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M7/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -424,7 +427,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); diff --git a/ports_module/cortex-m7/ac5/inc/txm_module_port.h b/ports_module/cortex-m7/ac5/inc/txm_module_port.h index defc6a49..d876f338 100644 --- a/ports_module/cortex-m7/ac5/inc/txm_module_port.h +++ b/ports_module/cortex-m7/ac5/inc/txm_module_port.h @@ -107,11 +107,17 @@ The following extensions must also be defined in tx_port.h: /* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) * to reflect your system memory attributes (cache, shareable, memory type). */ /* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL #define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif /* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL #define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif /* Define constants specific to the tools the module can be built with for this particular modules port. */ diff --git a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c index 8afa4571..3dce9ab7 100644 --- a/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m7/ac5/module_manager/src/txm_module_manager_mm_register_setup.c @@ -461,7 +461,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -493,7 +493,10 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, added */ +/* check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -504,6 +507,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex-m7/ac6/inc/tx_port.h b/ports_module/cortex-m7/ac6/inc/tx_port.h index 8c761ecf..57a43e48 100644 --- a/ports_module/cortex-m7/ac6/inc/tx_port.h +++ b/ports_module/cortex-m7/ac6/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -476,7 +479,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -489,7 +492,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -507,7 +510,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m7/ac6/inc/txm_module_port.h b/ports_module/cortex-m7/ac6/inc/txm_module_port.h index bf4c3738..584134bb 100644 --- a/ports_module/cortex-m7/ac6/inc/txm_module_port.h +++ b/ports_module/cortex-m7/ac6/inc/txm_module_port.h @@ -101,11 +101,17 @@ The following extensions must also be defined in tx_port.h: /* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) * to reflect your system memory attributes (cache, shareable, memory type). */ /* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL #define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif /* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL #define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif /* Define constants specific to the tools the module can be built with for this particular modules port. */ diff --git a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 7a4e63d3..359b628b 100644 --- a/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m7/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -461,7 +461,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_inside_data_check Cortex-M7/MPU/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -493,7 +493,10 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, added */ +/* check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -504,6 +507,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex-m7/gnu/inc/tx_port.h b/ports_module/cortex-m7/gnu/inc/tx_port.h index 78c15c58..d0e61b60 100644 --- a/ports_module/cortex-m7/gnu/inc/tx_port.h +++ b/ports_module/cortex-m7/gnu/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -470,7 +473,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -483,7 +486,7 @@ unsigned int interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); #define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); @@ -501,7 +504,7 @@ void tx_thread_fpu_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M7/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-m7/gnu/inc/txm_module_port.h b/ports_module/cortex-m7/gnu/inc/txm_module_port.h index 16aacacd..4c883ddb 100644 --- a/ports_module/cortex-m7/gnu/inc/txm_module_port.h +++ b/ports_module/cortex-m7/gnu/inc/txm_module_port.h @@ -101,12 +101,17 @@ The following extensions must also be defined in tx_port.h: /* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) * to reflect your system memory attributes (cache, shareable, memory type). */ /* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL #define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif /* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL #define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 - +#endif /* Define constants specific to the tools the module can be built with for this particular modules port. */ diff --git a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index ec85828e..da7187ba 100644 --- a/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m7/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -461,7 +461,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_inside_data_check Cortex-M7/MPU/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -493,7 +493,10 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, added */ +/* check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -504,6 +507,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex-m7/iar/inc/txm_module_port.h b/ports_module/cortex-m7/iar/inc/txm_module_port.h index 496dc591..7d56647e 100644 --- a/ports_module/cortex-m7/iar/inc/txm_module_port.h +++ b/ports_module/cortex-m7/iar/inc/txm_module_port.h @@ -103,11 +103,17 @@ The following extensions must also be defined in tx_port.h: /* For the following 3 access control settings, change TEX and C, B, S (bits 21 through 16 of MPU_RASR) * to reflect your system memory attributes (cache, shareable, memory type). */ /* Code region access control: privileged read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_CODE_ACCESS_CONTROL #define TXM_MODULE_MPU_CODE_ACCESS_CONTROL 0x06070000 +#endif /* Data region access control: execute never, read/write, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_DATA_ACCESS_CONTROL #define TXM_MODULE_MPU_DATA_ACCESS_CONTROL 0x13070000 +#endif /* Shared region access control: execute never, read-only, outer & inner write-back, normal memory, shareable. */ +#ifndef TXM_MODULE_MPU_SHARED_ACCESS_CONTROL #define TXM_MODULE_MPU_SHARED_ACCESS_CONTROL 0x12070000 +#endif /* Define constants specific to the tools the module can be built with for this particular modules port. */ diff --git a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c index db5d8de9..d4cb11d9 100644 --- a/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-m7/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -461,7 +461,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_inside_data_check Cortex-M7/MPU/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -493,7 +493,10 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, added */ +/* check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -504,6 +507,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex-r4/ac6/inc/tx_port.h b/ports_module/cortex-r4/ac6/inc/tx_port.h index 52efe1bf..5f480c29 100644 --- a/ports_module/cortex-r4/ac6/inc/tx_port.h +++ b/ports_module/cortex-r4/ac6/inc/tx_port.h @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -284,7 +287,7 @@ typedef unsigned short USHORT; #ifndef __thumb -#define TX_INTERRUPT_SAVE_AREA register unsigned int interrupt_save_disabled; +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save_disabled; #ifdef TX_ENABLE_FIQ_SUPPORT @@ -315,7 +318,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); @@ -343,7 +346,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index 524f67b5..0ac981b1 100644 --- a/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-r4/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -469,7 +469,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_inside_data_check Cortex-R4/MPU/ARM */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -501,7 +501,10 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, added */ +/* check for overflow, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -512,6 +515,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex-r4/iar/inc/tx_port.h b/ports_module/cortex-r4/iar/inc/tx_port.h index 34a300e5..b653cd20 100644 --- a/ports_module/cortex-r4/iar/inc/tx_port.h +++ b/ports_module/cortex-r4/iar/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-R4/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -347,9 +350,9 @@ __intrinsic void __set_CPSR( unsigned long ); #if (__VER__ < 8002000) -#define TX_INTERRUPT_SAVE_AREA unsigned long interrupt_save; +#define TX_INTERRUPT_SAVE_AREA ULONG interrupt_save; #else -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #endif #define TX_DISABLE interrupt_save = __get_CPSR(); \ @@ -392,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-R4/IAR Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c index b2c21835..cc59721d 100644 --- a/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex-r4/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -464,7 +464,7 @@ UINT i; /* FUNCTION RELEASE */ /* */ /* _txm_module_manager_inside_data_check Cortex-R4/MPU/IAR */ -/* 6.1 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -496,7 +496,10 @@ UINT i; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comments, added */ +/* check for overflow, * +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -507,6 +510,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_a35/ac6/inc/tx_port.h b/ports_module/cortex_a35/ac6/inc/tx_port.h index 7072796c..ae951986 100644 --- a/ports_module/cortex_a35/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35/ac6/inc/tx_port.h @@ -344,7 +344,7 @@ unsigned long long temp; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -354,7 +354,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); diff --git a/ports_module/cortex_a35/gnu/inc/tx_port.h b/ports_module/cortex_a35/gnu/inc/tx_port.h index a05d95fb..e01f26d1 100644 --- a/ports_module/cortex_a35/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35/gnu/inc/tx_port.h @@ -344,7 +344,7 @@ unsigned long long temp; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupts(); #define TX_RESTORE __restore_interrupts(interrupt_save); @@ -354,7 +354,7 @@ unsigned int _tx_thread_interrupt_disable(void); unsigned int _tx_thread_interrupt_restore(UINT old_posture); -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); #define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); diff --git a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h index 4d354f97..ecda68b2 100644 --- a/ports_module/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/ac6/inc/tx_port.h @@ -407,7 +407,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); diff --git a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h index cf8ec0b1..fe98f3cc 100644 --- a/ports_module/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_module/cortex_a35_smp/gnu/inc/tx_port.h @@ -407,7 +407,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); diff --git a/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt b/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt new file mode 100644 index 00000000..259a3e72 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/ARMCM23_TZ_config.txt @@ -0,0 +1,154 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +idau.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included + +cpu0.SAU=0x8 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] + +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.sse200.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.sse200.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.sse200.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.sse200.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.sse200.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.sse200.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.sse200.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sse200.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.sse200.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sse200.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:48:c5" # (string, init-time) default = '00:02:f7:ef:48:c5' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.sse200.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.sse200.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.sse200.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.sse200.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.sse200.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/ports_module/cortex_m23/ac6/example_build/AzureRTOS.uvmpw b/ports_module/cortex_m23/ac6/example_build/AzureRTOS.uvmpw new file mode 100644 index 00000000..86988b8b --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/AzureRTOS.uvmpw @@ -0,0 +1,36 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\demo_secure_zone\demo_secure_zone.uvprojx + 1 + 1 + + + + .\demo_threadx_non-secure_zone\demo_threadx_non-secure_zone.uvprojx + 1 + + + + .\ThreadX_Library.uvprojx + 1 + + + + .\sample_threadx_module\sample_threadx_module.uvprojx + 1 + + + + .\txm\txm.uvprojx + 1 + + + diff --git a/ports_module/cortex_m23/ac6/example_build/Debug.ini b/ports_module/cortex_m23/ac6/example_build/Debug.ini new file mode 100644 index 00000000..9f305fef --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/Debug.ini @@ -0,0 +1,5 @@ +LOAD "..\\demo_threadx_non-secure_zone\\Objects\\demo_threadx_non-secure_zone.axf" incremental +LOAD "..\\demo_secure_zone\\Objects\\demo_secure_zone.axf" incremental +LOAD "..\\sample_threadx_module\\Objects\\sample_threadx_module.axf" incremental +RESET +g, \\demo_secure_zone\main_s\main \ No newline at end of file diff --git a/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..476361d7 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx new file mode 100644 index 00000000..cb51db51 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/ThreadX_Library.uvoptx @@ -0,0 +1,2960 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Library_Project + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\common\src\tx_block_allocate.c + tx_block_allocate.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\common\src\tx_block_pool_cleanup.c + tx_block_pool_cleanup.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 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..\..\..\..\common\src\txe_mutex_info_get.c + + + txe_mutex_prioritize.c + 1 + ..\..\..\..\common\src\txe_mutex_prioritize.c + + + txe_mutex_put.c + 1 + ..\..\..\..\common\src\txe_mutex_put.c + + + txe_queue_create.c + 1 + ..\..\..\..\common\src\txe_queue_create.c + + + txe_queue_delete.c + 1 + ..\..\..\..\common\src\txe_queue_delete.c + + + txe_queue_flush.c + 1 + ..\..\..\..\common\src\txe_queue_flush.c + + + txe_queue_front_send.c + 1 + ..\..\..\..\common\src\txe_queue_front_send.c + + + txe_queue_info_get.c + 1 + ..\..\..\..\common\src\txe_queue_info_get.c + + + txe_queue_prioritize.c + 1 + ..\..\..\..\common\src\txe_queue_prioritize.c + + + txe_queue_receive.c + 1 + ..\..\..\..\common\src\txe_queue_receive.c + + + txe_queue_send.c + 1 + ..\..\..\..\common\src\txe_queue_send.c + + + txe_queue_send_notify.c + 1 + ..\..\..\..\common\src\txe_queue_send_notify.c + + + txe_semaphore_ceiling_put.c + 1 + ..\..\..\..\common\src\txe_semaphore_ceiling_put.c + + + txe_semaphore_create.c + 1 + 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1 + ..\..\..\..\common\src\txe_thread_priority_change.c + + + txe_thread_relinquish.c + 1 + ..\..\..\..\common\src\txe_thread_relinquish.c + + + txe_thread_reset.c + 1 + ..\..\..\..\common\src\txe_thread_reset.c + + + txe_thread_resume.c + 1 + ..\..\..\..\common\src\txe_thread_resume.c + + + txe_thread_suspend.c + 1 + ..\..\..\..\common\src\txe_thread_suspend.c + + + txe_thread_terminate.c + 1 + ..\..\..\..\common\src\txe_thread_terminate.c + + + txe_thread_time_slice_change.c + 1 + ..\..\..\..\common\src\txe_thread_time_slice_change.c + + + txe_thread_wait_abort.c + 1 + ..\..\..\..\common\src\txe_thread_wait_abort.c + + + txe_timer_activate.c + 1 + ..\..\..\..\common\src\txe_timer_activate.c + + + txe_timer_change.c + 1 + ..\..\..\..\common\src\txe_timer_change.c + + + txe_timer_create.c + 1 + ..\..\..\..\common\src\txe_timer_create.c + + + txe_timer_deactivate.c + 1 + ..\..\..\..\common\src\txe_timer_deactivate.c + + + txe_timer_delete.c + 1 + ..\..\..\..\common\src\txe_timer_delete.c + + + txe_timer_info_get.c + 1 + ..\..\..\..\common\src\txe_timer_info_get.c + + + tx_trace_buffer_full_notify.c + 1 + ..\..\..\..\common\src\tx_trace_buffer_full_notify.c + + + tx_trace_event_filter.c + 1 + ..\..\..\..\common\src\tx_trace_event_filter.c + + + tx_trace_event_unfilter.c + 1 + ..\..\..\..\common\src\tx_trace_event_unfilter.c + + + txe_thread_secure_stack_allocate.c + 1 + ..\module_manager\src\txe_thread_secure_stack_allocate.c + + + txe_thread_secure_stack_free.c + 1 + ..\module_manager\src\txe_thread_secure_stack_free.c + + + tx_thread_stack_error_handler.c + 1 + ..\module_manager\src\tx_thread_stack_error_handler.c + + + tx_thread_stack_error_notify.c + 1 + ..\module_manager\src\tx_thread_stack_error_notify.c + + + tx_thread_context_restore.S + 2 + ..\module_manager\src\tx_thread_context_restore.S + + + tx_thread_context_save.S + 2 + ..\module_manager\src\tx_thread_context_save.S + + + tx_thread_interrupt_control.S + 2 + ..\module_manager\src\tx_thread_interrupt_control.S + + + tx_thread_interrupt_disable.S + 2 + ..\module_manager\src\tx_thread_interrupt_disable.S + + + tx_thread_interrupt_restore.S + 2 + ..\module_manager\src\tx_thread_interrupt_restore.S + + + tx_thread_schedule.S + 2 + ..\module_manager\src\tx_thread_schedule.S + + + tx_thread_secure_stack_allocate.S + 2 + ..\module_manager\src\tx_thread_secure_stack_allocate.S + + + tx_thread_secure_stack_free.S + 2 + ..\module_manager\src\tx_thread_secure_stack_free.S + + + tx_thread_stack_build.S + 2 + ..\module_manager\src\tx_thread_stack_build.S + + + tx_thread_system_return.S + 2 + ..\module_manager\src\tx_thread_system_return.S + + + tx_timer_interrupt.S + 2 + ..\module_manager\src\tx_timer_interrupt.S + + + tx_initialize_low_level.S + 2 + .\tx_initialize_low_level.S + + + txm_module_manager_application_request.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_application_request.c + + + txm_module_manager_callback_request.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_callback_request.c + + + txm_module_manager_event_flags_notify_trampoline.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_event_flags_notify_trampoline.c + + + txm_module_manager_file_load.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_file_load.c + + + txm_module_manager_in_place_load.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_in_place_load.c + + + txm_module_manager_initialize.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_initialize.c + + + txm_module_manager_internal_load.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_internal_load.c + + + txm_module_manager_kernel_dispatch.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_kernel_dispatch.c + + + txm_module_manager_maximum_module_priority_set.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_maximum_module_priority_set.c + + + txm_module_manager_memory_load.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_memory_load.c + + + txm_module_manager_object_allocate.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_allocate.c + + + txm_module_manager_object_deallocate.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_deallocate.c + + + txm_module_manager_object_pointer_get.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get.c + + + txm_module_manager_object_pointer_get_extended.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pointer_get_extended.c + + + txm_module_manager_object_pool_create.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_object_pool_create.c + + + txm_module_manager_properties_get.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_properties_get.c + + + txm_module_manager_queue_notify_trampoline.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_queue_notify_trampoline.c + + + txm_module_manager_semaphore_notify_trampoline.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_semaphore_notify_trampoline.c + + + txm_module_manager_start.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_start.c + + + txm_module_manager_stop.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_stop.c + + + txm_module_manager_thread_create.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_create.c + + + txm_module_manager_thread_notify_trampoline.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_notify_trampoline.c + + + txm_module_manager_thread_reset.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_thread_reset.c + + + txm_module_manager_timer_notify_trampoline.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_timer_notify_trampoline.c + + + txm_module_manager_unload.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_unload.c + + + txm_module_manager_util.c + 1 + ..\..\..\..\common_modules\module_manager\src\txm_module_manager_util.c + + + txm_module_manager_alignment_adjust.c + 1 + ..\module_manager\src\txm_module_manager_alignment_adjust.c + + + txm_module_manager_external_memory_enable.c + 1 + ..\module_manager\src\txm_module_manager_external_memory_enable.c + + + txm_module_manager_memory_fault_handler.c + 1 + ..\module_manager\src\txm_module_manager_memory_fault_handler.c + + + txm_module_manager_memory_fault_notify.c + 1 + ..\module_manager\src\txm_module_manager_memory_fault_notify.c + + + txm_module_manager_mm_register_setup.c + 1 + ..\module_manager\src\txm_module_manager_mm_register_setup.c + + + txm_module_manager_thread_stack_build.S + 2 + ..\module_manager\src\txm_module_manager_thread_stack_build.S + + + txm_module_manager_port_dispatch.c + 1 + ..\module_manager\src\txm_module_manager_port_dispatch.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct new file mode 100644 index 00000000..f71f6dd1 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -0,0 +1,81 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00040000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00020000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + SEAL +0 + { + *.o(.seal+FIRST) + } +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h new file mode 100644 index 00000000..2572a044 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/partition_ARMCM23.h @@ -0,0 +1,832 @@ +/**************************************************************************//** + * @file partition_ARMCM23.h + * @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23 + * @version V1.0.0 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_ARMCM23_H +#define PARTITION_ARMCM23_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00040000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0007FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20020000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x40040000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00200000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x002fffff /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + + +/* +// Setup behaviour of single SysTick +*/ +#define SCB_ICSR_INIT 0 + +/* +// in a single SysTick implementation, SysTick is +// <0=>Secure +// <1=>Non-Secure +// Value for SCB->ICSR register bit STTNS +// only for single SysTick implementation +*/ +#define SCB_ICSR_STTNS_VAL 0 + +/* +// +*/ + + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) + SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) | + ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk); + #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */ + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif /* PARTITION_ARMCM23_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c new file mode 100644 index 00000000..3a70c740 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c @@ -0,0 +1,154 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/* The linker will place this value at the bottom of the stack to seal the secure main stack. */ +const int stack_seal __attribute__((section (".seal"))) = 0xFEF5EDA5; + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c new file mode 100644 index 00000000..cf78a4ed --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -0,0 +1,96 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; + + *(uint32_t *)0xE000ED24 = 0x000F0000; /* S: enable secure, usage, bus, mem faults */ + *(uint32_t *)0xE002ED24 = 0x000F0000; /* NS: enable secure, usage, bus, mem faults */ +} + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +void HardFault_Handler(void) +{ + while(1); + +} + +void UsageFault_Handler(void) +{ + while(1); +} +#endif diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..a37b412e --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx new file mode 100644 index 00000000..fb2925de --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvoptx @@ -0,0 +1,467 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M23_MDK.exe" -MF"..\ARMCM23_TZ_config.txt" -PF -MA + + + 0 + DLGTARM + (6010=851,404,1328,1000,0)(6018=-1,-1,-1,-1,0)(6019=105,137,294,473,0)(6008=1511,0,1805,185,0)(6009=137,177,431,362,0)(6014=1310,310,1568,1041,0)(6015=1547,312,1805,934,0)(6003=1122,384,1704,920,0)(6000=758,242,1211,574,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=1039,107,1805,421,0)(107=-1,-1,-1,-1,0) + + + + + 0 + 0 + 120 + 1 +
263362
+ 0 + 0 + 0 + 0 + 0 + 1 + <2>.\sample_threadx_module_manager.c + + \\demo_threadx_non_secure_zone\sample_threadx_module_manager.c\120 + + + 1 + 0 + 244 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + <4>.\sample_threadx_module.c + + \\sample_threadx_module\sample_threadx_module.c\244 + + + 2 + 0 + 87 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + <1>RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + \\demo_secure_zone\RTE/Device/ARMCM23_TZ/system_ARMCM23.c\87 + + + 3 + 0 + 0 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + <3>..\..\..\..\common\src\tx_timer_initialize.c + + \\demo_threadx_non_secure_zone\../../../../common/src/tx_timer_initialize.c\274 + + + 5 + 0 + 0 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 1 + <4>.\sample_threadx_module.c + + \\sample_threadx_module\sample_threadx_module.c\304 + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + 8 + 1 + _tx_thread_current_ptr + + + 9 + 1 + _tx_thread_execute_ptr + + + 10 + 1 + my_module + + + 11 + 1 + _tx_timer_system_clock + + + + + 1 + 2 + 0x20040000 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\main_s.c + main_s.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\module_manager\src\tx_thread_secure_stack.c + tx_thread_secure_stack.c + 0 + 0 + + + + + Interface + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + .\interface.c + interface.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx new file mode 100644 index 00000000..03cde05e --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/demo_secure_zone.uvprojx @@ -0,0 +1,521 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 1 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 7 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\..\common\inc, ..\..\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM23_TZ\ARMCM23_AC6.sct + + + + + + + + + + + Secure Code + + + main_s.c + 1 + .\main_s.c + + + tx_thread_secure_stack.c + 1 + ..\..\module_manager\src\tx_thread_secure_stack.c + + + + + Interface + + + interface.c + 1 + .\interface.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + RTE\Device\ARMCM23_TZ\partition_ARMCM23.h + + + + + + + + RTE\Device\ARMCM23_TZ\startup_ARMCM23.c + + + + + + + + RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c new file mode 100644 index 00000000..4e6e8eee --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.c Secure/non-secure callable application code + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + + +#include // CMSE definitions +#include "interface.h" // Header file with secure interface API + +/* typedef for non-secure callback functions */ +typedef funcptr funcptr_NS __attribute__((cmse_nonsecure_call)); + +/* Non-secure callable (entry) function */ +int func1(int x) __attribute__((cmse_nonsecure_entry)) { + return x+3; +} + +/* Non-secure callable (entry) function, calling a non-secure callback function */ +int func2(funcptr callback, int x) __attribute__((cmse_nonsecure_entry)) { + funcptr_NS callback_NS; // non-secure callback function pointer + int y; + + /* return function pointer with cleared LSB */ + callback_NS = (funcptr_NS)cmse_nsfptr_create(callback); + + y = callback_NS (x+1); + + return (y+2); +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.h b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.h new file mode 100644 index 00000000..8215d5a3 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/interface.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * interface.h API definition for the non-secure state + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +/* Function pointer declaration */ +typedef int (*funcptr)(int); + +/* Non-secure callable functions */ +extern int func1(int x); +extern int func2(funcptr callback, int x); diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c new file mode 100644 index 00000000..a65b6880 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_ns.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * main_ns.c Non-secure main function - RTOS demo + * + * Version 1.0 + * Initial Release + *---------------------------------------------------------------------------*/ + +#include "..\demo_secure_zone\interface.h" // Interface API +//#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +//static osStatus_t Status; + +//static osThreadId_t ThreadA_Id; +//static osThreadId_t ThreadB_Id; +//static osThreadId_t ThreadC_Id; + +void ThreadA (void *argument); +void ThreadB (void *argument); +void ThreadC (void *argument); + + +extern volatile int counterA; +extern volatile int counterB; +extern volatile int counterC; + +volatile int counterA; +volatile int counterB; +volatile int counterC; + +/* +static int callbackA (int val) { + return (val); +} + +__attribute__((noreturn)) +void ThreadA (void *argument) { + (void)argument; + + for (;;) { + counterA = func1 (counterA); + counterA = func2 (callbackA, counterA); + osDelay(2U); + } +} + +static int callbackB (int val) { + uint32_t flags; + + flags = osThreadFlagsWait (1U, osFlagsWaitAny, osWaitForever); + if (flags == 1U) { + return (val+1); + } else { + return (0); + } +} + + +__attribute__((noreturn)) +void ThreadB (void *argument) { + (void)argument; + + for (;;) { + counterB = func1 (counterB); + counterB = func2 (callbackB, counterB); + } +} + +__attribute__((noreturn)) +void ThreadC (void *argument) { + (void)argument; + + for (;;) { + counterC = counterC + 1; + if ((counterC % 0x10) == 0) { + osThreadFlagsSet (ThreadB_Id, 1); + } + osDelay(1U); + } +} + +static const osThreadAttr_t ThreadAttr = { + .tz_module = 1U, // indicate calls to secure mode +}; +*/ +#if 1 +int main (void) { + + //Status = osKernelInitialize(); + + //ThreadA_Id = osThreadNew(ThreadA, NULL, &ThreadAttr); + //ThreadB_Id = osThreadNew(ThreadB, NULL, &ThreadAttr); + //ThreadC_Id = osThreadNew(ThreadC, NULL, NULL); + + //Status = osKernelStart(); + + for (;;); +} +#endif diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c new file mode 100644 index 00000000..9ff73190 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/main_s.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Code template for secure main function + * + *---------------------------------------------------------------------------*/ + +/* Use CMSE intrinsics */ +#include + #include +#include "RTE_Components.h" +#include CMSIS_device_header + +/* TZ_START_NS: Start address of non-secure application */ +#ifndef TZ_START_NS +#define TZ_START_NS (0x00040000U) +#endif + +/* typedef for non-secure callback functions */ +typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call)); + +/* Secure main() */ +int main(void) { + funcptr_void NonSecure_ResetHandler; + + /* Add user setup code for secure part here*/ + + /* Set non-secure main stack (MSP_NS) */ + __TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS))); + + /* Get non-secure reset handler */ + NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U))); + + /* Start non-secure state software application */ + NonSecure_ResetHandler(); + + /* Non-secure software does not return, this code is not executed */ + while (1) { + __NOP(); + } +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c new file mode 100644 index 00000000..f3152890 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/tz_context.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ---------------------------------------------------------------------------- + * + * $Date: 15. October 2016 + * $Revision: 1.1.0 + * + * Project: TrustZone for ARMv8-M + * Title: Context Management for ARMv8-M TrustZone - Sample implementation + * + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "tz_context.h" + +/// Number of process slots (threads may call secure library code) +#ifndef TZ_PROCESS_STACK_SLOTS +#define TZ_PROCESS_STACK_SLOTS 8U +#endif + +/// Stack size of the secure library code +#ifndef TZ_PROCESS_STACK_SIZE +#define TZ_PROCESS_STACK_SIZE 256U +#endif + +typedef struct { + uint32_t sp_top; // stack space top + uint32_t sp_limit; // stack space limit + uint32_t sp; // current stack pointer +} stack_info_t; + +static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS]; +static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U]; +static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU; + + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_InitContextSystem_S (void) { + uint32_t n; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) { + ProcessStackInfo[n].sp = 0U; + ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n]; + ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE; + *((uint32_t *)ProcessStackMemory[n]) = n + 1U; + } + *((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU; + + ProcessStackFreeSlot = 0U; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + // Privileged Thread Mode using PSP + __set_CONTROL(0x02U); + + return 1U; // Success +} + + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +__attribute__((cmse_nonsecure_entry)) +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) { + uint32_t slot; + + (void)module; // Ignore (fixed Stack size) + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if (ProcessStackFreeSlot == 0xFFFFFFFFU) { + return 0U; // No slot available + } + + slot = ProcessStackFreeSlot; + ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]); + + ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top; + + return (slot + 1U); +} + + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if (__get_IPSR() == 0U) { + return 0U; // Thread Mode + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + ProcessStackInfo[slot].sp = 0U; + + *((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot; + ProcessStackFreeSlot = slot; + + return 1U; // Success +} + + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) { + uint32_t slot; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + // Setup process stack pointer and stack limit + __set_PSPLIM(ProcessStackInfo[slot].sp_limit); + __set_PSP (ProcessStackInfo[slot].sp); + + return 1U; // Success +} + + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +__attribute__((cmse_nonsecure_entry)) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) { + uint32_t slot; + uint32_t sp; + + if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) { + return 0U; // Thread Mode or using Main Stack for threads + } + + if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) { + return 0U; // Invalid ID + } + + slot = id - 1U; + + if (ProcessStackInfo[slot].sp == 0U) { + return 0U; // Inactive slot + } + + sp = __get_PSP(); + if ((sp < ProcessStackInfo[slot].sp_limit) || + (sp > ProcessStackInfo[slot].sp_top)) { + return 0U; // SP out of range + } + ProcessStackInfo[slot].sp = sp; + + // Default process stack pointer and stack limit + __set_PSPLIM((uint32_t)ProcessStackMemory); + __set_PSP ((uint32_t)ProcessStackMemory); + + return 1U; // Success +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c new file mode 100644 index 00000000..e4871014 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h new file mode 100644 index 00000000..3021efbc --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2013-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 256 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x01U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x01U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x05U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x01U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x01U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x01U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x01U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x01U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x01U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x01U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x01U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct new file mode 100644 index 00000000..2b6482c7 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/ARMCM23_ac6.sct @@ -0,0 +1,85 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00040000 +#define __ROM_SIZE 0x00040000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20020000 +#define __RAM_SIZE 0x00020000 + +#define SHARED_MEM_BASE 0x20040000 +#define SHARED_MEM_SIZE 0x00000100 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) +; *(Veneer$$CMSE) ; uncomment for secure applications + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + SHARED_MEM SHARED_MEM_BASE SHARED_MEM_SIZE { + sample_threadx_module_manager.o (sharedmem) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c new file mode 100644 index 00000000..18633eb2 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/startup_ARMCM23.c @@ -0,0 +1,151 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M23 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c new file mode 100644 index 00000000..3381c1f5 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/system_ARMCM23.c @@ -0,0 +1,80 @@ +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#elif defined (ARMCM23_TZ) + #include "ARMCM23_TZ.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..1cde6a79 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'demo_threadx_non-secure_zone' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h new file mode 100644 index 00000000..1eb74752 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/_ThreadX_Library_Project/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'ThreadX_Library' + * Target: 'ThreadX_Library_Project' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM33_DSP_FP_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt new file mode 100644 index 00000000..7ec4b36b --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvopt @@ -0,0 +1,305 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX_Demo + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 1 + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + -1 + + + + + + + + + + + + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(102=-1,-1,-1,-1,0)(103=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(163=-1,-1,-1,-1,0)(164=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)(152=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)(1013=-1,-1,-1,-1,0)(171=-1,-1,-1,-1,0)(172=-1,-1,-1,-1,0)(173=-1,-1,-1,-1,0)(1014=-1,-1,-1,-1,0)(1016=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T5F + + + 0 + UL2CM3 + -UV0289BJE -O14 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0LM3S_16 -FS00 -FL04000 + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + _tx_thread_current_ptr + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 1 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 0 + .\tx_initialize_low_level.s + tx_initialize_low_level.s + 0 + 0 + + + 1 + 2 + 1 + 1 + 0 + 0 + .\demo_threadx.c + demo_threadx.c + 0 + 0 + + 44 + 0 + 1 + + -1 + -1 + + + -1 + -1 + + + 56 + 12 + 1633 + 671 + + + + + + + Library_Group + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + .\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj new file mode 100644 index 00000000..5f5dcbdb --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/ThreadX_Demo.uvproj @@ -0,0 +1,556 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + ThreadX_Demo + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + 0 + + + + Luminary\ + Luminary\ + + 0 + 0 + 0 + 0 + 1 + + .\ + threadx_demo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DCM.DLL + -pCM4F + SARMCM3.DLL + + TCM.DLL + -pCM4F + + + + 1 + 0 + 0 + 0 + 16 + + + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 0 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + -1 + + + + + + + + + + + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 0 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + --first __tx_vectors --entry=__main + + + + + + + + Source Group + + + 0 + 1 + 1 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 0 + + + + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + tx_initialize_low_level.s + 2 + .\tx_initialize_low_level.s + + + 2 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 2 + 2 + 1 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + demo_threadx.c + 1 + .\demo_threadx.c + + + + + Library_Group + + + ThreadX_Library.lib + 4 + .\ThreadX_Library.lib + + + + + + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx new file mode 100644 index 00000000..63fd727f --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvoptx @@ -0,0 +1,335 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + ..\Debug.ini + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + 0 + DbgFMv8M + -I -S -L"cpu0" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M33_MDK.exe" -MF"..\ARMCM33_DSP_FP_TZ_config.txt" -PF -MA + + + 0 + PWSTATINFO + 200,50,700 + + + 0 + DLGTARM + (6010=1243,118,1720,714,0)(6018=1284,352,1473,701,0)(6019=1328,34,1517,370,0)(6008=-1,-1,-1,-1,0)(6009=969,18,1263,203,0)(6014=1111,129,1369,860,0)(6015=872,146,1130,768,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=511,345,1277,660,0)(107=-1,-1,-1,-1,0) + + + + + + 0 + 1 + thread_0_counter + + + 1 + 1 + thread_1_counter + + + 2 + 1 + thread_2_counter + + + 3 + 1 + thread_3_counter + + + 4 + 1 + thread_4_counter + + + 5 + 1 + thread_5_counter + + + 6 + 1 + thread_6_counter + + + 7 + 1 + thread_7_counter + + + + + 1 + 2 + 0x20200a10 + 0 + + + + + 2 + 2 + 0xE000ED28 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Non-secure Code + 1 + 0 + 0 + 0 + + 1 + 1 + 4 + 0 + 0 + 0 + ..\ThreadX_Library.lib + ThreadX_Library.lib + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + .\sample_threadx_module_manager.c + sample_threadx_module_manager.c + 0 + 0 + + + + + CMSE Library + 0 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + ..\demo_secure_zone\interface.h + interface.h + 0 + 0 + + + 2 + 4 + 3 + 0 + 0 + 0 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + demo_secure_zone_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx new file mode 100644 index 00000000..2a4e0418 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/demo_threadx_non-secure_zone.uvprojx @@ -0,0 +1,596 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + demo_threadx_non-secure_zone + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + -1 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 1 + 1 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 1 + 1 + 1 + 0 + 0 + 0 + + -Wno-unused-function -Wno-visibility -Wno-missing-noreturn -Wno-unused-parameter + + + ..\..\..\..\..\common\inc, ..\..\inc, ..\..\..\..\..\common_modules\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + .\RTE\Device\ARMCM23_TZ\ARMCM23_AC6.sct + + + + + + + + + + + Non-secure Code + + + ThreadX_Library.lib + 4 + ..\ThreadX_Library.lib + + + sample_threadx_module_manager.c + 1 + .\sample_threadx_module_manager.c + + + + + CMSE Library + + + interface.h + 5 + ..\demo_secure_zone\interface.h + + + demo_secure_zone_CMSE_Lib.o + 3 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM23_TZ\ARMCM23_ac6.sct + + + + + + + + RTE\Device\ARMCM23_TZ\startup_ARMCM23.c + + + + + + + + RTE\Device\ARMCM23_TZ\system_ARMCM23.c + + + + + + + + RTE\Device\ARMCM33_DSP_FP\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\ARMCM33_ac6.sct + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.c + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_DSP_FP_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMCM33_TZ\partition_ARMCM33.h + + + + + + RTE\Device\ARMCM33_TZ\startup_ARMCM33.s + + + + + + RTE\Device\ARMCM33_TZ\system_ARMCM33.c + + + + + + RTE\Device\ARMv8MBL\partition_ARMv8MBL.h + + + + + + RTE\Device\ARMv8MBL\startup_ARMv8MBL.s + + + + + + RTE\Device\ARMv8MBL\system_ARMv8MBL.c + + + + + + RTE\Device\CMSDK_ARMv8MBL\RTE_Device.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\partition_CMSDK_ARMv8MBL.h + + + + + + RTE\Device\CMSDK_ARMv8MBL\startup_CMSDK_ARMv8MBL.s + + + + + + RTE\Device\CMSDK_ARMv8MBL\system_CMSDK_ARMv8MBL.c + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c new file mode 100644 index 00000000..57fcc32f --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/sample_threadx_module_manager.c @@ -0,0 +1,131 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +static TX_THREAD module_manager; +static TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +static UCHAR object_memory[16384]; + + +/* Define the module data pool area. */ + +#define MODULE_DATA_SIZE (64 * 1024) +static UCHAR module_data_area[MODULE_DATA_SIZE]; + + +/* The module code should be loaded here. */ + +#define MODULE_CODE (0x00200000) + + +/* Define the shared memory area. */ + +#define SHARED_MEMORY_SIZE (256) +__attribute__((section("sharedmem"))) +static UCHAR shared_memory[SHARED_MEMORY_SIZE] __attribute__((aligned (32))); + + +/* Define the count of memory faults. */ + +static ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +static VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + (void)thread_input; + + tx_thread_secure_stack_allocate(&module_manager, 256); + + /* Initialize the module manager. */ + txm_module_manager_initialize((void *) module_data_area, MODULE_DATA_SIZE); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Enable a read/write shared memory region. */ + txm_module_manager_external_memory_enable(&my_module, (void *) shared_memory, SHARED_MEMORY_SIZE, TXM_MODULE_ATTRIBUTE_READ_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (void *) MODULE_CODE); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h new file mode 100644 index 00000000..4470aa37 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/RTE/_FVP_Simulation_Model/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'sample_threadx_module' + * Target: 'FVP Simulation Model' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c new file mode 100644 index 00000000..4d3bdc0f --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.c @@ -0,0 +1,438 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +#include "interface.h" + +/* Define constants. */ + +#define DEMO_STACK_SIZE 1024 +#define DEMO_BYTE_POOL_SIZE 9120 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the external memory area. */ + +#define EXTERNAL_MEMORY (0x20040000) + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + tx_thread_secure_stack_allocate(thread_0, 256); + thread_0_counter = func1(thread_0_counter); + tx_thread_secure_stack_free(thread_0); + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test external memory sharing. */ + *(ULONG *)EXTERNAL_MEMORY = 0xABABABAB; + *(ULONG *)0x20040004 = 0x01010101; + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.uvoptx b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.uvoptx new file mode 100644 index 00000000..43fa3272 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.uvoptx @@ -0,0 +1,236 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + FVP Simulation Model + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 15 + + + + + + + + + + + BIN\DbgFMv8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Module Code + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + .\sample_threadx_module.c + sample_threadx_module.c + 0 + 0 + + + 1 + 2 + 2 + 0 + 0 + 0 + .\txm_module_preamble.S + txm_module_preamble.S + 0 + 0 + + + 1 + 3 + 4 + 0 + 0 + 0 + ..\txm\Objects\txm.lib + txm.lib + 0 + 0 + + + 1 + 4 + 3 + 0 + 0 + 0 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + demo_secure_zone_CMSE_Lib.o + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.uvprojx b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.uvprojx new file mode 100644 index 00000000..17627896 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/sample_threadx_module.uvprojx @@ -0,0 +1,453 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + FVP Simulation Model + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + ARMCM23_TZ + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M23") TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM23_TZ$Device\ARM\ARMCM23\Include\ARMCM23_TZ.h + + + + + + + + + + + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + sample_threadx_module + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM23 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 0 + 4101 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M23" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x200000 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x20200000 + 0x20000 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 3 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\..\..\..\common_modules\inc, ..\..\..\..\..\common\inc, ..\..\..\..\..\ports_module\cortex_m23\ac6\inc, ..\demo_secure_zone + + + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 1 + 1 + 0 + 1 + 0 + 0x00200000 + 0x00000000 + + + + + --entry demo_module_start --first __txm_module_preamble + + + + + + + + Module Code + + + sample_threadx_module.c + 1 + .\sample_threadx_module.c + + + txm_module_preamble.S + 2 + .\txm_module_preamble.S + + + txm.lib + 4 + ..\txm\Objects\txm.lib + + + demo_secure_zone_CMSE_Lib.o + 3 + ..\demo_secure_zone\Objects\demo_secure_zone_CMSE_Lib.o + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S new file mode 100644 index 00000000..f6530c9f --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/sample_threadx_module/txm_module_preamble.S @@ -0,0 +1,66 @@ + .text + .align 4 + .syntax unified + .section RESET + + // Define public symbols + .global __txm_module_preamble + + // Define application-specific start/stop entry points for the module + .global demo_module_start + + // Define common external references + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x01000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> ARM + // 2 -> GNU + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected) + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + .dc.l _txm_module_thread_shell_entry - __txm_module_preamble // Module Shell Entry Point + .dc.l demo_module_start - __txm_module_preamble // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - __txm_module_preamble // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + //the tools can't add two symbols together, but it should look like this: + //.dc.l Image$$ER_RO$$Length + Image$$ER_RW$$Length // Module Code Size + //.dc.l Image$$ER_RW$$Length + Image$$ER_ZI$$ZI$$Length // Module Data Size + //so instead we'll define hard values: + .dc.l 0x4000 // Module Code Size + .dc.l 0x4000 // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S new file mode 100644 index 00000000..3ea33abb --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/tx_initialize_low_level.S @@ -0,0 +1,210 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address + ADDS r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__Vectors // Pickup address of vector table + STR r1, [r0] // Set vector table address + +// /* Enable the cycle count register. */ +// +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__Vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOVW r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + + /* Do interrupt handler work here */ + /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. + B HardFault_Handler + + .end diff --git a/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h b/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h new file mode 100644 index 00000000..74656ec0 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/txm/RTE/_ThreadX_Module_Library/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'txm' + * Target: 'ThreadX Module Library' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM23_TZ.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/ports_module/cortex_m23/ac6/example_build/txm/txm.uvoptx b/ports_module/cortex_m23/ac6/example_build/txm/txm.uvoptx new file mode 100644 index 00000000..8e8c53b5 --- /dev/null +++ b/ports_module/cortex_m23/ac6/example_build/txm/txm.uvoptx @@ -0,0 +1,1412 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ThreadX Module Library + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FC1000 -FD20000000 + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c + txm_block_allocate.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c + txm_block_pool_create.c + 0 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..\..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c + + + txm_block_pool_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c + + + txm_block_pool_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c + + + txm_block_pool_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c + + + txm_block_pool_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c + + + txm_block_pool_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c + + + txm_block_pool_prioritize.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c + + + txm_block_release.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_block_release.c + + + txm_byte_allocate.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c + + + txm_byte_pool_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c + + + txm_byte_pool_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c + + + txm_byte_pool_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c + + + txm_byte_pool_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c + + + txm_byte_pool_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c + + + txm_byte_pool_prioritize.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c + + + txm_byte_release.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_byte_release.c + + + txm_event_flags_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c + + + txm_event_flags_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c + + + txm_event_flags_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c + + + txm_event_flags_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c + + + txm_event_flags_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c + + + txm_event_flags_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c + + + txm_event_flags_set.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c + + + txm_event_flags_set_notify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c + + + txm_module_application_request.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c + + + txm_module_callback_request_thread_entry.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c + + + txm_module_object_allocate.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c + + + txm_module_object_deallocate.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c + + + txm_module_object_pointer_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c + + + txm_module_object_pointer_get_extended.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get_extended.c + + + txm_module_thread_system_suspend.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c + + + txm_mutex_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c + + + txm_mutex_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c + + + txm_mutex_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c + + + txm_mutex_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c + + + txm_mutex_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c + + + txm_mutex_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c + + + txm_mutex_prioritize.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c + + + txm_mutex_put.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c + + + txm_queue_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_create.c + + + txm_queue_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c + + + txm_queue_flush.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c + + + txm_queue_front_send.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c + + + txm_queue_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c + + + txm_queue_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c + + + txm_queue_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c + + + txm_queue_prioritize.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c + + + txm_queue_receive.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c + + + txm_queue_send.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_send.c + + + txm_queue_send_notify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c + + + txm_semaphore_ceiling_put.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c + + + txm_semaphore_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c + + + txm_semaphore_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c + + + txm_semaphore_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c + + + txm_semaphore_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c + + + txm_semaphore_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c + + + txm_semaphore_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c + + + txm_semaphore_prioritize.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c + + + txm_semaphore_put.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c + + + txm_semaphore_put_notify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c + + + txm_thread_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_create.c + + + txm_thread_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c + + + txm_thread_entry_exit_notify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c + + + txm_thread_identify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c + + + txm_thread_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c + + + txm_thread_interrupt_control.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c + + + txm_thread_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c + + + txm_thread_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c + + + txm_thread_preemption_change.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c + + + txm_thread_priority_change.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c + + + txm_thread_relinquish.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c + + + txm_thread_reset.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c + + + txm_thread_resume.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c + + + txm_thread_sleep.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c + + + txm_thread_stack_error_notify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c + + + txm_thread_suspend.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c + + + txm_thread_terminate.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c + + + txm_thread_time_slice_change.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c + + + txm_thread_wait_abort.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c + + + txm_time_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_time_get.c + + + txm_time_set.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_time_set.c + + + txm_timer_activate.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c + + + txm_timer_change.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_change.c + + + txm_timer_create.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_create.c + + + txm_timer_deactivate.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c + + + txm_timer_delete.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c + + + txm_timer_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c + + + txm_timer_performance_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c + + + txm_timer_performance_system_info_get.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c + + + txm_trace_buffer_full_notify.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c + + + txm_trace_disable.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c + + + txm_trace_enable.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c + + + txm_trace_event_filter.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c + + + txm_trace_event_unfilter.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c + + + txm_trace_interrupt_control.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_interrupt_control.c + + + txm_trace_isr_enter_insert.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c + + + txm_trace_isr_exit_insert.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c + + + txm_trace_user_event_insert.c + 1 + ..\..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + + + txm_module_initialize.S + 2 + ..\..\module_lib\src\txm_module_initialize.S + + + txm_module_thread_shell_entry.c + 1 + ..\..\module_lib\src\txm_module_thread_shell_entry.c + + + txm_thread_secure_stack_allocate.c + 1 + ..\..\module_lib\src\txm_thread_secure_stack_allocate.c + + + txm_thread_secure_stack_free.c + 1 + ..\..\module_lib\src\txm_thread_secure_stack_free.c + + + + + ::CMSIS + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + + diff --git a/ports_module/cortex_m23/ac6/inc/tx_port.h b/ports_module/cortex_m23/ac6/inc/tx_port.h new file mode 100644 index 00000000..f2604699 --- /dev/null +++ b/ports_module/cortex_m23/ac6/inc/tx_port.h @@ -0,0 +1,584 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M23/AC6 */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include +#include +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M23 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +//register unsigned int _ipsr __asm ("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); +inline static unsigned int _get_ipsr(void); +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#ifdef __ARM_PCS_VFP + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else + +#ifdef TX_SOURCE_CODE + +static unsigned int _get_control(void); +static unsigned int _get_control(void) +{ + unsigned int _control; + __asm("MRS %[result], control" : [result] "=r" (_control) : ); + return _control; +} + +static void _set_control(unsigned int _control); +static void _set_control(unsigned int _control) +{ + __asm("MSR control, %[input]" : : [input] "r" (_control)); +} + +#endif +#endif + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state);; \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +void _tx_vfp_access(void); + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_vfp_access(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _get_control(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _set_control(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT)__clz(__rbit((m))); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifdef TX_DISABLE_INLINE + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); + +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); + +#else + +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; +#define TX_DISABLE was_masked = __disable_irq(); +#define TX_RESTORE if (was_masked == 0) __enable_irq(); + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +static void _tx_thread_system_return_inline(void) +{ +unsigned int was_masked; + + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + was_masked = __disable_irq(); + __enable_irq(); + if (was_masked != 0) + __disable_irq(); + } +} +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/AC6 Version 6.1.6 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif + + + diff --git a/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h new file mode 100644 index 00000000..c2779f40 --- /dev/null +++ b/ports_module/cortex_m23/ac6/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports_module/cortex_m23/ac6/inc/txm_module_port.h b/ports_module/cortex_m23/ac6/inc/txm_module_port.h new file mode 100644 index 00000000..16645dbb --- /dev/null +++ b/ports_module/cortex_m23/ac6/inc/txm_module_port.h @@ -0,0 +1,352 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M23/AC6 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M23 devices, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, one for module code protection, one for module data protection, + leaving five regions available for shared memory. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_CODE_INDEX 1 +#define TXM_MODULE_MPU_DATA_INDEX 2 + +#define TXM_MODULE_MPU_SHARED_INDEX 3 +#define TXM_MODULE_MPU_SHARED_ENTRIES 5 + +#define TXM_MODULE_ATTRIBUTE_NON_SHAREABLE 0x00 +#define TXM_MODULE_ATTRIBUTE_OUTER_SHAREABLE 0x10 +#define TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE 0x18 +#define TXM_MODULE_ATTRIBUTE_READ_WRITE 0x02 +#define TXM_MODULE_ATTRIBUTE_READ_ONLY 0x06 +#define TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER 0x01 +#define TXM_MODULE_ATTRIBUTE_REGION_ENABLE 0x01 +#define TXM_MODULE_ATTRIBUTE_MASK 0x1E +#define TXM_MODULE_ATTRIBUTE_INDEX 0x00 + +/* MAIR_ATTR settings +Device-nGnRE : 0b [Outer]0000 [Inner]0100 +Code WT RA : 0b [Outer]1010 [Inner]1010 +DATA WBWA RA : 0b [Outer]1111 [Inner]1111 +*/ + +/* Data aligned to 8 bytes (stacks must be 8-byte aligned). */ +#define TXM_MODULE_DATA_ALIGNMENT 8 + +/* MPU regions must be 32-byte aligned. */ +#define TXM_MODULE_MPU_ALIGNMENT 32 + +#define TXM_THREAD_SECURE_STACK_ALLOCATE_CALL TXM_MODULE_PORT_EXTENSION_API_ID_START +#define TXM_THREAD_SECURE_STACK_FREE_CALL (TXM_MODULE_PORT_EXTENSION_API_ID_START+1) + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RLAR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_base_address; + ULONG txm_module_mpu_region_limit_address; +} TXM_MODULE_MPU_INFO; + +/* Define the port-extensions to the module manager instance structure. */ +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#ifdef TX_SOURCE_CODE + +#endif + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2); + + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/AC6 Version 6.1.6 *"; + +#endif diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S new file mode 100644 index 00000000..2221f2fd --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_initialize.S @@ -0,0 +1,118 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .global __use_two_region_memory + .global __scatterload + + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 2 + + .text +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_initialize Cortex-M23/AC6 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the module c runtime. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __scatterload Initialize C runtime */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_thread_shell_entry Start module thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_initialize(VOID) + .global _txm_module_initialize + .thumb_func +_txm_module_initialize: + MOV r0, r8 // Copy r8-r11 + MOV r1, r9 + MOV r2, r10 + MOV r3, r11 + PUSH {r0-r7} // Save r4-r11 + MOV r0, r12 + MOV r1, lr + PUSH {r0-r1} // Save r12, lr + + //B __scatterload // Call ARM func to initialize variables + +// Override the __rt_exit function. + .global __rt_exit + .thumb_func +__rt_exit: + POP {r0-r1} // Restore r4-r12 and LR + MOV r12, r0 + MOV lr, r1 + POP {r0-r7} + MOV r8, r0 + MOV r9, r1 + MOV r10, r2 + MOV r11, r3 + BX lr // Return to caller + +#define TXM_MODULE_HEAP_SIZE 512 + +// returns heap start address in R0 +// returns heap end address in R2 +// does not touch SP, it is already set up before the module runs + .global __user_setup_stackheap + .thumb_func +__user_setup_stackheap: + LDR r1, _txm_heap // load heap offset + MOV r2, TXM_MODULE_HEAP_SIZE // load heap size + ADD r2, r2, r0 // calculate heap end address + BX lr + +// dummy main function + .global main + .thumb_func +main: + BX lr + + .align 8 +_txm_heap: + .zero TXM_MODULE_HEAP_SIZE diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..9a952615 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the ARM cstartup code. */ +extern VOID _txm_module_initialize(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M23/AC6 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_initialize cstartup initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the ARM C environment. */ + _txm_module_initialize(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c new file mode 100644 index 00000000..7a4bdf38 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_allocate.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocate a secure stack for the thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_ALLOCATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) stack_size, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c new file mode 100644 index 00000000..83e923fc --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_lib/src/txm_thread_secure_stack_free.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees the thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_FREE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h new file mode 100644 index 00000000..e612b45c --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/inc/txm_module_manager_dispatch_port.h @@ -0,0 +1,65 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Define port-specific dispatch functions. */ + +/* UINT _txe_thread_secure_stack_allocate( + TX_THREAD *thread_ptr, -> param_0 + ULONG stack_size -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate( + (TX_THREAD *) param_0, + (ULONG) param_1 + ); + return(return_value); +} + +/* UINT _txe_thread_secure_stack_free( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_free_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free( + (TX_THREAD *) param_0 + ); + return(return_value); +} \ No newline at end of file diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..b2989990 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_restore + .thumb_func +.type _tx_thread_context_restore, function +_tx_thread_context_restore: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..fefeb7b0 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_save + .thumb_func +.type _tx_thread_context_save, function +_tx_thread_context_save: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..7a24fffd --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .section .text + .balign 4 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_control + .thumb_func +.type _tx_thread_interrupt_control, function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..d99f1713 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_disable + .thumb_func +.type _tx_thread_interrupt_disable, function +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ + MRS r0, PRIMASK + CPSID i + BX lr +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..b03ad941 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_restore + .thumb_func +.type _tx_thread_interrupt_restore, function +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ + MSR PRIMASK, r0 + BX lr +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..2a39b955 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,643 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M23/AC6 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_schedule + .thumb_func +.type _tx_thread_schedule, function +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOVW r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + + .global MemManage_Handler + .global BusFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r2,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r2, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r2, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r2, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r2, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r2, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r2, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r2, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r2, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r2, #36] // Save r1 + LDR r0, [r1, #8] // Pickup saved r2 + STR r0, [r2, #40] // Save r2 + STR r3, [r2, #44] // Save r3 + STR r4, [r2, #48] // Save r4 + STR r5, [r2, #52] // Save r5 + STR r6, [r2, #56] // Save r6 + STR r7, [r2, #60] // Save r7 + MOV r0, r8 // Move r8 to moveable register + STR r0, [r2, #64] // Save r8 + MOV r0, r9 // Move r9 to moveable register + STR r0, [r2, #68] // Save r9 + MOV r0, r10 // Move r10 to moveable register + STR r0, [r2, #72] // Save r10 + MOV r0, r11 // Move r11 to moveable register + STR r0, [r2, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r2, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r2, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r2, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r2, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + MOVW r1, #0x1 // + BICS r0, r0, r1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOVW r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts +#ifdef TX_SINGLE_MODE_SECURE + LDR r0, =0xFFFFFFFD // Exception return to secure +#else + LDR r0, =0xFFFFFFBC // Exception return to non-secure +#endif + MOV lr, r0 // Move exception return to lr + BX lr // Return from exception + + + /* Generic context switching PendSV handler. */ + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global PendSV_Handler + .thumb_func +.type PendSV_Handler, function + /* Get current thread value and new thread pointer. */ +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, r1} // Recover LR + MOV lr, r1 + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + + MOVW r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 // Allocate stack space + STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // + MOV r5, r9 // + MOV r6, r10 // + MOV r7, r11 // + SUBS r3, r3, #32 // Allocate stack space + STM r3!, {r4-r7} // + SUBS r3, r3, #20 // Allocate stack space + MOV r5, lr // + STR r5, [r3] // Save LR on the stack + STR r3, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, =0xC4 // Secure stack index offset + LDR r5, [r1, r5] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0-r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0-r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + MOVW r5, #0 // Build clear value + STR r5, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + LDR r7, =0x08000000 // Build clear PendSV value + LDR r5, =0xE000ED04 // Build base NVIC address + STR r7, [r5] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADDS r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r5, =0xC4 // Secure stack index offset + LDR r0, [r1, r5] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0, r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0, r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + // Set up CONTROL register based on user mode flag (privileged/unprivileged mode) + MRS r5, CONTROL // Pickup current CONTROL register + MOVS r2, #0x98 // Index of current user mode flag + LDR r4, [r1, r2] // Pickup current user mode flag + MOVW r0, #0x1 + BICS r5, r5, r0 // Clear the UNPRIV bit + ORRS r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + // Determine if MPU needs to be configured + LDR r0, =0xE000ED94 // Build MPU control reg address + MOVW r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + MOVS r2, #0x90 // Index of module instance pointer + LDR r0, [r1, r2] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + MOV r8, r1 // Copy thread ptr + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + + // Initialize loop to configure MPU registers + MOVS r3, #0x64 // Index of MPU register settings in thread control block + ADD r0, r0, r3 // Build address of MPU register start in thread control block + MOVS r5, #0 // Select region 0 + LDR r4, =0xE000ED98 // Region register address + // Loop to load MPU registers +_tx_mpu_loop: + LDR r1, =0xE000ED9C // Build address of MPU base register + STR r5, [r4] // Set region + LDM r0!, {r2-r3} // Get MPU settings from the module + STM r1!, {r2-r3} // Set MPU registers for region + ADDS r5, r5, #1 // Increment to next region + CMP r5, #8 // Check if all regions have been set + BNE _tx_mpu_loop + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOVS r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU + MOV r1, r8 // Get copied thread ptr + +skip_mpu_setup: + + // Restore the thread context and PSP + LDR r3, [r1, #8] // Pickup thread's stack pointer + LDR r5, [r3] // Recover saved LR + ADDS r3, r3, #4 // Position past LR + MOV lr, r5 // Restore LR + LDM r3!, {r4-r7} // Recover thread's registers (r8-r11) + MOV r11, r7 + MOV r10, r6 + MOV r9, r5 + MOV r8, r4 + LDM r3!, {r4-r7} // Recover thread's registers (r4-r7) + MSR PSP, r3 // Setup the thread's stack pointer + + BX lr // Return to thread! + + + + /* SVC Handler. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SVC_Handler + .thumb_func +.type SVC_Handler, function +SVC_Handler: + MOV r0, lr + MOVS r1, #0x04 + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_load_msp + MRS r0, PSP // Get PSP + B _tx_get_svc +_tx_load_msp: + MRS r0, MSP // Get MSP +_tx_get_svc: + LDR r1, [r0,#24] // Load saved PC from stack + LDR r3, =-2 + LDRB r2, [r1,r3] // Load SVC number + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + CMP r2, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r2, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + CMP r2, #3 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 3, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + BEQ _tx_entry_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_entry_continue: + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0 // Build clear value + MOVS r0, #0x98 // Index of current user mode + STR r1, [r2, r0] // Clear the current user mode selection for thread + MOVS r0, #0xA0 // Index of saved LR + STR r3, [r2, r0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + MOVS r0, #0x90 // Index of module instance ptr + LDR r0, [r2, r0] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + MOVS r1, #2 // MPU protection flag + TST r0, r1 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + MOVS r0, #0xA8 // Index of module kernel stack end + LDR r0, [r2, r0] // Load the module kernel stack end + MOVS r1, #0xA4 // Index of module kernel stack start + LDR r1, [r2, r1] // Load the module kernel stack start + MSR PSPLIM, r1 // Set stack limit +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOVS r3, #0xAC // Index of module kernel stack size + LDR r3, [r2, r3] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + MOVS r1, #0xB0 // Index of module stack pointer + STR r3, [r2, r1] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + SUBS r0, r0, #32 // Start at top of hardware stack + LDMIA r3!, {r1,r2} // Get r0, r1 from thread stack + STMIA r0!, {r1,r2} // Insert r0, r1 into kernel stack + LDMIA r3!, {r1,r2} // Get r2, r3 from thread stack + STMIA r0!, {r1,r2} // Insert r2, r3 into kernel stack + LDMIA r3!, {r1,r2} // Get r12, lr from thread stack + STMIA r0!, {r1,r2} // Insert r12, lr into kernel stack + LDMIA r3!, {r1,r2} // Get pc, xpsr from thread stack + STMIA r0!, {r1,r2} // Insert pc, xpsr into kernel stack + SUBS r0, r0, #32 // Go back to top of stack + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + MOVW r1, #0x1 // + BICS r0, r0, r1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + BEQ _tx_exit_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_exit_continue: + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0x9C // Index of user mode + MOVS r3, #0x98 // Index of current user mode + LDR r1, [r2, r1] // Pick up user mode + STR r1, [r2, r3] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + MOVS r0, #0x90 // Index of module instance ptr + LDR r0, [r2, r0] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + MOVS r1, #2 // MPU protection flag + TST r0, r1 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + + MOVS r0, #0xB4 // Index of module thread stack start + LDR r0, [r2, r0] // Load the module thread stack start + MSR PSPLIM, r0 // Set stack limit +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOVS r1, #0xB8 // Index of module thread stack end + LDR r1, [r2, r1] // Load the module thread stack end + MOVS r3, #0xBC // Index of module thread stack size + LDR r3, [r2, r3] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + MOVS r1, #0xB0 // Index of module thread stack pointer + LDR r0, [r2, r1] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} // Get r0, r1 from kernel stack + STM r0!,{r1-r2} // Insert r0, r1 into thread stack + LDM r3!,{r1-r2} // Get r2, r3 from kernel stack + STM r0!,{r1-r2} // Insert r2, r3 into thread stack + LDM r3!,{r1-r2} // Get r12, lr from kernel stack + STM r0!,{r1-r2} // Insert r12, lr into thread stack + LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack + STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + SUBS r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0x9C // Index of user mode + LDR r1, [r2, r1] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORRS r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) +_tx_svc_secure_alloc: + LDR r2, =_tx_alloc_return // Load address of where we should have come from + CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? + BEQ _tx_alloc_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_alloc_continue: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr + +_tx_svc_secure_free: + LDR r2, =_tx_free_return // Load address of where we should have come from + CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? + BEQ _tx_free_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_free_continue: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 3 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR r2, =0xA0 // Index of saved LR + LDR r1, [r3, r2] // Pickup saved LR from original call + MOV lr, r1 + SVC 4 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } + +.end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..311e67b6 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack.c @@ -0,0 +1,485 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "ARMCM23_TZ.h" /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* 8 bytes added to stack size to "seal" stack. */ +#define TX_THREAD_STACK_SEAL_SIZE 8 +#define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/AC6 */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/AC6 */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* added stack sealing, */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG sp; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack & seal. */ + stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Seal bottom of stack. */ + *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at PSP_NS and seeing if it is within + the stack_start and stack_end range. */ + sp = __TZ_get_PSP_NS(); + if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/AC6 */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/AC6 */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/AC6 */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S new file mode 100644 index 00000000..de7098e7 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_allocate.S @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_allocate + .global _tx_alloc_return + .thumb_func +.type _tx_thread_secure_stack_allocate, function +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 1 +_tx_alloc_return: + CMP r3, #0 // If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_alloc_return_interrupt_enabled: + BX lr + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S new file mode 100644 index 00000000..837dba7e --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_secure_stack_free.S @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_free + .global _tx_free_return + .thumb_func +.type _tx_thread_secure_stack_free, function +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 2 +_tx_free_return: + CMP r3, #0 // If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_free_return_interrupt_enabled: + BX lr + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..5a95a14f --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_stack_build + .thumb_func +.type _tx_thread_stack_build, function +_tx_thread_stack_build: + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..175a9109 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_system_return + .thumb_func +.type _tx_thread_system_return, function +_tx_thread_system_return: + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..fdfcdcc5 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,262 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/AC6 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_timer_interrupt + .thumb_func +.type _tx_timer_interrupt, function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock + MOVT r1, #:upper16:_tx_timer_system_clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice + MOVT r3, #:upper16:_tx_timer_time_slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address + MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address + MOVT r3, #:upper16:_tx_timer_expired + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end + MOVT r3, #:upper16:_tx_timer_list_end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start + MOVT r3, #:upper16:_tx_timer_list_start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag + MOVT r0, #:upper16:_tx_thread_preempt_disable + + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address + MOVT r0, #:upper16:_tx_thread_current_ptr + + LDR r1, [r0] // Pickup the current thread pointer + MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address + MOVT r2, #:upper16:_tx_thread_execute_ptr + + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + // } + +__tx_timer_not_ts_expiration: + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } + .end diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..f3a37aa9 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + + /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ + *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); + *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); + + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ + *code_alignment = TXM_MODULE_MPU_ALIGNMENT; + *data_alignment = TXM_MODULE_MPU_ALIGNMENT; +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..4869407c --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. The start_address must be 32-byte aligned. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG address; +ULONG shared_index; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address must adhere to Cortex-M23 MPU alignment. */ + address = (ULONG) start_address; + if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address. Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Set base address register with start address, sanitized attributes and execute never. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; + + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..974ffebe --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..938e484c --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..faa7551f --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M23 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU settings for the module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* none */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; + + /* Setup MPU region for kernel mode entry. */ + /* Set base address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, inner shareable, read only. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_base_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY; + /* Set the limit address, attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_limit_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of kernel mode entry setup. */ + + + /* Setup MPU region for module code protection. */ + /* Set base address register to module code address, which should be at least 32-byte aligned. + Mask address to proper range, inner shareable, read only. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_code_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY; + /* Set the limit address (code start + code size-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_code_start + module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of module code protection. */ + + + /* Setup MPU region for module data protection. */ + /* Set base address register to module data address, which should be at least 32-byte aligned. + Mask address to proper range, inner shareable, read write, execute never. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of module data protection. */ + + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c new file mode 100644 index 00000000..ed9f0ea4 --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_port_dispatch.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_port_dispatch Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function dispatches the module's kernel request based upon the */ +/* ID and parameters specified in the request. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module pointer */ +/* kernel_request Module's kernel request */ +/* param_0 First parameter */ +/* param_1 Second parameter */ +/* param_2 Third parameter */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* Port-specific ThreadX API Calls */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value = TX_NOT_AVAILABLE; + + switch(kernel_request) + { + case TXM_THREAD_SECURE_STACK_ALLOCATE_CALL: + { + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate( + (TX_THREAD *) param_0, + (ULONG) param_1 + ); + break; + } + + case TXM_THREAD_SECURE_STACK_FREE_CALL: + { + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free( + (TX_THREAD *) param_0 + ); + break; + } + + default: + { + /* Unhandled kernel request, return an error! */ + break; + } + } + + return(return_value); +} diff --git a/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..80236fda --- /dev/null +++ b/ports_module/cortex_m23/ac6/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,144 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M23/AC6 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #8] // Store initial r9 (data base register) + MOVW r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex_m23/gnu/example_build/build_threadx.bat b/ports_module/cortex_m23/gnu/example_build/build_threadx.bat new file mode 100644 index 00000000..128de0a1 --- /dev/null +++ b/ports_module/cortex_m23/gnu/example_build/build_threadx.bat @@ -0,0 +1,249 @@ +del tx.a +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_initialize_low_level.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_context_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_context_save.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_interrupt_control.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_interrupt_disable.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_interrupt_restore.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_schedule.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_secure_stack_allocate.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_secure_stack_free.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_stack_build.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_thread_system_return.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/tx_timer_interrupt.S +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 ../module_manager/src/txm_module_manager_thread_stack_build.S + +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/txe_thread_secure_stack_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/txe_thread_secure_stack_free.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/tx_thread_stack_error_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../module_manager/src/tx_thread_stack_error_notify.c + +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_alignment_adjust.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_external_memory_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_memory_fault_handler.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_memory_fault_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_mm_register_setup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common_modules/module_manager/inc -I../../../../common_modules/inc -I../../../../common/inc -I../inc ../module_manager/src/txm_module_manager_port_dispatch.c + +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_pool_search.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_cleanup.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_initialize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/tx_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc 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-mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -I../../../../common/inc -I../inc ../../../../common/src/txe_timer_info_get.c + +arm-none-eabi-ar -r tx.a txm_module_manager_thread_stack_build.o txm_module_manager_alignment_adjust.o txm_module_manager_external_memory_enable.o +arm-none-eabi-ar -r tx.a txm_module_manager_memory_fault_handler.o txm_module_manager_memory_fault_notify.o txm_module_manager_mm_register_setup.o txm_module_manager_port_dispatch.o + +arm-none-eabi-ar -r tx.a tx_thread_secure_stack_allocate.o txe_thread_secure_stack_allocate.o tx_thread_secure_stack_free.o txe_thread_secure_stack_free.o +arm-none-eabi-ar -r tx.a tx_thread_stack_build.o tx_thread_schedule.o tx_thread_system_return.o tx_thread_context_save.o tx_thread_context_restore.o tx_timer_interrupt.o tx_thread_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_thread_interrupt_disable.o tx_thread_interrupt_restore.o tx_initialize_low_level.o +arm-none-eabi-ar -r tx.a tx_block_allocate.o tx_block_pool_cleanup.o tx_block_pool_create.o tx_block_pool_delete.o tx_block_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_block_pool_initialize.o tx_block_pool_performance_info_get.o tx_block_pool_performance_system_info_get.o tx_block_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_block_release.o tx_byte_allocate.o tx_byte_pool_cleanup.o tx_byte_pool_create.o tx_byte_pool_delete.o tx_byte_pool_info_get.o +arm-none-eabi-ar -r tx.a tx_byte_pool_initialize.o tx_byte_pool_performance_info_get.o tx_byte_pool_performance_system_info_get.o tx_byte_pool_prioritize.o +arm-none-eabi-ar -r tx.a tx_byte_pool_search.o tx_byte_release.o tx_event_flags_cleanup.o tx_event_flags_create.o tx_event_flags_delete.o tx_event_flags_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_info_get.o tx_event_flags_initialize.o tx_event_flags_performance_info_get.o tx_event_flags_performance_system_info_get.o +arm-none-eabi-ar -r tx.a tx_event_flags_set.o tx_event_flags_set_notify.o tx_initialize_high_level.o tx_initialize_kernel_enter.o tx_initialize_kernel_setup.o +arm-none-eabi-ar -r tx.a tx_mutex_cleanup.o tx_mutex_create.o tx_mutex_delete.o tx_mutex_get.o tx_mutex_info_get.o tx_mutex_initialize.o tx_mutex_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_mutex_performance_system_info_get.o tx_mutex_prioritize.o tx_mutex_priority_change.o tx_mutex_put.o tx_queue_cleanup.o tx_queue_create.o +arm-none-eabi-ar -r tx.a tx_queue_delete.o tx_queue_flush.o tx_queue_front_send.o tx_queue_info_get.o tx_queue_initialize.o tx_queue_performance_info_get.o +arm-none-eabi-ar -r tx.a tx_queue_performance_system_info_get.o tx_queue_prioritize.o tx_queue_receive.o tx_queue_send.o tx_queue_send_notify.o tx_semaphore_ceiling_put.o +arm-none-eabi-ar -r tx.a tx_semaphore_cleanup.o tx_semaphore_create.o tx_semaphore_delete.o tx_semaphore_get.o tx_semaphore_info_get.o tx_semaphore_initialize.o +arm-none-eabi-ar -r tx.a tx_semaphore_performance_info_get.o tx_semaphore_performance_system_info_get.o tx_semaphore_prioritize.o tx_semaphore_put.o tx_semaphore_put_notify.o +arm-none-eabi-ar -r tx.a tx_thread_create.o tx_thread_delete.o tx_thread_entry_exit_notify.o tx_thread_identify.o tx_thread_info_get.o tx_thread_initialize.o +arm-none-eabi-ar -r tx.a tx_thread_performance_info_get.o tx_thread_performance_system_info_get.o tx_thread_preemption_change.o tx_thread_priority_change.o tx_thread_relinquish.o +arm-none-eabi-ar -r tx.a tx_thread_reset.o tx_thread_resume.o tx_thread_shell_entry.o tx_thread_sleep.o tx_thread_stack_analyze.o tx_thread_stack_error_handler.o +arm-none-eabi-ar -r tx.a tx_thread_stack_error_notify.o tx_thread_suspend.o tx_thread_system_preempt_check.o tx_thread_system_resume.o tx_thread_system_suspend.o +arm-none-eabi-ar -r tx.a tx_thread_terminate.o tx_thread_time_slice.o tx_thread_time_slice_change.o tx_thread_timeout.o tx_thread_wait_abort.o tx_time_get.o +arm-none-eabi-ar -r tx.a tx_time_set.o tx_timer_activate.o tx_timer_change.o tx_timer_create.o tx_timer_deactivate.o tx_timer_delete.o tx_timer_expiration_process.o +arm-none-eabi-ar -r tx.a tx_timer_info_get.o tx_timer_initialize.o tx_timer_performance_info_get.o tx_timer_performance_system_info_get.o tx_timer_system_activate.o +arm-none-eabi-ar -r tx.a tx_timer_system_deactivate.o tx_timer_thread_entry.o tx_trace_enable.o tx_trace_disable.o tx_trace_initialize.o tx_trace_interrupt_control.o +arm-none-eabi-ar -r tx.a tx_trace_isr_enter_insert.o tx_trace_isr_exit_insert.o tx_trace_object_register.o tx_trace_object_unregister.o tx_trace_user_event_insert.o +arm-none-eabi-ar -r tx.a tx_trace_buffer_full_notify.o tx_trace_event_filter.o tx_trace_event_unfilter.o +arm-none-eabi-ar -r tx.a txe_block_allocate.o txe_block_pool_create.o txe_block_pool_delete.o txe_block_pool_info_get.o txe_block_pool_prioritize.o txe_block_release.o +arm-none-eabi-ar -r tx.a txe_byte_allocate.o txe_byte_pool_create.o txe_byte_pool_delete.o txe_byte_pool_info_get.o txe_byte_pool_prioritize.o txe_byte_release.o +arm-none-eabi-ar -r tx.a txe_event_flags_create.o txe_event_flags_delete.o txe_event_flags_get.o txe_event_flags_info_get.o txe_event_flags_set.o +arm-none-eabi-ar -r tx.a txe_event_flags_set_notify.o txe_mutex_create.o txe_mutex_delete.o txe_mutex_get.o txe_mutex_info_get.o txe_mutex_prioritize.o +arm-none-eabi-ar -r tx.a txe_mutex_put.o txe_queue_create.o txe_queue_delete.o txe_queue_flush.o txe_queue_front_send.o txe_queue_info_get.o txe_queue_prioritize.o +arm-none-eabi-ar -r tx.a txe_queue_receive.o txe_queue_send.o txe_queue_send_notify.o txe_semaphore_ceiling_put.o txe_semaphore_create.o txe_semaphore_delete.o +arm-none-eabi-ar -r tx.a txe_semaphore_get.o txe_semaphore_info_get.o txe_semaphore_prioritize.o txe_semaphore_put.o txe_semaphore_put_notify.o txe_thread_create.o +arm-none-eabi-ar -r tx.a txe_thread_delete.o txe_thread_entry_exit_notify.o txe_thread_info_get.o txe_thread_preemption_change.o txe_thread_priority_change.o +arm-none-eabi-ar -r tx.a txe_thread_relinquish.o txe_thread_reset.o txe_thread_resume.o txe_thread_suspend.o txe_thread_terminate.o txe_thread_time_slice_change.o +arm-none-eabi-ar -r tx.a txe_thread_wait_abort.o txe_timer_activate.o txe_timer_change.o txe_timer_create.o txe_timer_deactivate.o txe_timer_delete.o txe_timer_info_get.o diff --git a/ports_module/cortex_m23/gnu/example_build/build_threadx_module_library.bat b/ports_module/cortex_m23/gnu/example_build/build_threadx_module_library.bat new file mode 100644 index 00000000..1ef416ad --- /dev/null +++ b/ports_module/cortex_m23/gnu/example_build/build_threadx_module_library.bat @@ -0,0 +1,104 @@ +del txm.a + +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\module_lib\src\txm_module_thread_shell_entry.c + +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_block_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_pool_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_byte_release.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_event_flags_set_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_application_request.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_callback_request_thread_entry.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_allocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_deallocate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_object_pointer_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_module_thread_system_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_mutex_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_flush.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_front_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_receive.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_queue_send_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_ceiling_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_prioritize.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_semaphore_put_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_entry_exit_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_identify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_interrupt_control.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_preemption_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_priority_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_relinquish.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_reset.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_resume.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_sleep.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_stack_error_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_suspend.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_terminate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_time_slice_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_thread_wait_abort.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_time_set.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_activate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_change.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_create.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_deactivate.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_delete.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_timer_performance_system_info_get.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_buffer_full_notify.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_disable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_enable.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_filter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_event_unfilter.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_enter_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_isr_exit_insert.c +arm-none-eabi-gcc -c -g -mcpu=cortex-m23 -mthumb -fpic -fno-plt -mpic-data-is-text-relative -msingle-pic-base -I..\inc -I..\..\..\..\common\inc -I..\..\..\..\common_modules\inc ..\..\..\..\common_modules\module_lib\src\txm_trace_user_event_insert.c + +arm-none-eabi-ar -r txm.a txm_block_allocate.o txm_block_pool_create.o txm_block_pool_delete.o txm_block_pool_info_get.o txm_block_pool_performance_info_get.o txm_block_pool_performance_system_info_get.o txm_block_pool_prioritize.o txm_block_release.o txm_byte_allocate.o txm_byte_pool_create.o txm_byte_pool_delete.o txm_byte_pool_info_get.o txm_byte_pool_performance_info_get.o txm_byte_pool_performance_system_info_get.o txm_byte_pool_prioritize.o txm_byte_release.o txm_event_flags_create.o txm_event_flags_delete.o txm_event_flags_get.o txm_event_flags_info_get.o txm_event_flags_performance_info_get.o txm_event_flags_performance_system_info_get.o txm_event_flags_set.o txm_event_flags_set_notify.o txm_thread_create.o txm_thread_delete.o txm_thread_entry_exit_notify.o txm_thread_identify.o txm_thread_info_get.o txm_thread_interrupt_control.o txm_thread_performance_info_get.o txm_time_get.o txm_time_set.o +arm-none-eabi-ar -r txm.a txm_module_application_request.o txm_module_callback_request_thread_entry.o txm_module_object_allocate.o txm_module_object_deallocate.o txm_module_object_pointer_get.o txm_module_thread_shell_entry.o txm_module_thread_system_suspend.o txm_mutex_create.o txm_mutex_delete.o txm_mutex_get.o txm_mutex_info_get.o txm_mutex_performance_info_get.o txm_mutex_performance_system_info_get.o txm_mutex_prioritize.o txm_mutex_put.o txm_queue_create.o txm_queue_delete.o txm_queue_flush.o txm_queue_front_send.o txm_queue_info_get.o txm_queue_performance_info_get.o txm_queue_performance_system_info_get.o txm_queue_prioritize.o txm_queue_receive.o txm_queue_send.o txm_queue_send_notify.o txm_semaphore_ceiling_put.o txm_semaphore_create.o txm_semaphore_delete.o txm_semaphore_get.o txm_semaphore_info_get.o txm_semaphore_performance_info_get.o txm_semaphore_performance_system_info_get.o txm_semaphore_prioritize.o txm_semaphore_put.o txm_semaphore_put_notify.o +arm-none-eabi-ar -r txm.a txm_thread_performance_system_info_get.o txm_thread_preemption_change.o txm_thread_priority_change.o txm_thread_relinquish.o txm_thread_reset.o txm_thread_resume.o txm_thread_sleep.o txm_thread_stack_error_notify.o txm_thread_suspend.o txm_thread_terminate.o txm_thread_time_slice_change.o txm_thread_wait_abort.o txm_timer_activate.o txm_timer_change.o txm_timer_create.o txm_timer_deactivate.o txm_timer_delete.o txm_timer_info_get.o txm_timer_performance_info_get.o txm_timer_performance_system_info_get.o txm_trace_buffer_full_notify.o txm_trace_disable.o txm_trace_enable.o txm_trace_event_filter.o txm_trace_event_unfilter.o txm_trace_isr_enter_insert.o txm_trace_isr_exit_insert.o txm_trace_user_event_insert.o diff --git a/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c new file mode 100644 index 00000000..52557312 --- /dev/null +++ b/ports_module/cortex_m23/gnu/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 512 +#define DEMO_BYTE_POOL_SIZE 6000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x20010000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S new file mode 100644 index 00000000..a9413251 --- /dev/null +++ b/ports_module/cortex_m23/gnu/example_build/txm_module_preamble.S @@ -0,0 +1,58 @@ + .text + .align 4 + .syntax unified + + /* Define public symbols. */ + .global __txm_module_preamble + + /* Define application-specific start/stop entry points for the module. */ + .global demo_module_start + + /* Define common external refrences. */ + .global _txm_module_thread_shell_entry + .global _txm_module_callback_request_thread_entry + +__txm_module_preamble: + .dc.l 0x4D4F4455 // Module ID + .dc.l 0x6 // Module Major Version + .dc.l 0x1 // Module Minor Version + .dc.l 32 // Module Preamble Size in 32-bit words + .dc.l 0x12345678 // Module ID (application defined) + .dc.l 0x02000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> ARM + // 2 -> GNU + // Bits 23-3: Reserved + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected - bit 0 set) + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + .dc.l _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point + .dc.l demo_module_start - . - 0 // Module Start Thread Entry Point + .dc.l 0 // Module Stop Thread Entry Point + .dc.l 1 // Module Start/Stop Thread Priority + .dc.l 1024 // Module Start/Stop Thread Stack Size + .dc.l _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry + .dc.l 1 // Module Callback Thread Priority + .dc.l 1024 // Module Callback Thread Stack Size + .dc.l __code_size__ // Module Code Size + .dc.l __data_size__ // Module Data Size + .dc.l 0 // Reserved 0 + .dc.l 0 // Reserved 1 + .dc.l 0 // Reserved 2 + .dc.l 0 // Reserved 3 + .dc.l 0 // Reserved 4 + .dc.l 0 // Reserved 5 + .dc.l 0 // Reserved 6 + .dc.l 0 // Reserved 7 + .dc.l 0 // Reserved 8 + .dc.l 0 // Reserved 9 + .dc.l 0 // Reserved 10 + .dc.l 0 // Reserved 11 + .dc.l 0 // Reserved 12 + .dc.l 0 // Reserved 13 + .dc.l 0 // Reserved 14 + .dc.l 0 // Reserved 15 diff --git a/ports_module/cortex_m23/gnu/inc/tx_port.h b/ports_module/cortex_m23/gnu/inc/tx_port.h new file mode 100644 index 00000000..7c87baff --- /dev/null +++ b/ports_module/cortex_m23/gnu/inc/tx_port.h @@ -0,0 +1,485 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h Cortex-M23/GNU */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Scott Larson Modified comment(s), */ +/* remove unneeded headers, */ +/* use builtins, added */ +/* ULONG64_DEFINED,updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + +/* Determine if the optional ThreadX user define file should be used. */ +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + +/* Define compiler library include files. */ + +#include +#include + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M23 port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_secure_stack_context; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif +#define TX_THREAD_EXTENSION_3 + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + + +#ifndef TX_MISRA_ENABLE + +inline static unsigned int _get_ipsr(void) +{ + unsigned int _ipsr; + __asm("MRS %[result], ipsr" : [result] "=r" (_ipsr) : ); + return _ipsr; +} + +#endif + + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _get_ipsr()) +#else +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif +#endif + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + +/* Determine if the ARM architecture has the CLZ instruction. This is available on + architectures v5 and above. If available, redefine the macro for calculating the + lowest bit set. */ + +#ifndef TX_DISABLE_INLINE + +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __builtin_ctz(m); + +#endif + + +/* Define ThreadX interrupt lockout and restore macros for protection on + access of critical kernel information. The restore interrupt macro must + restore the interrupt posture of the running thread prior to the value + present prior to the disable macro. In most cases, the save area macro + is used to define a local function save area for the disable and restore + macros. */ + +#ifndef TX_DISABLE_INLINE + +/* Define GNU specific macros, with in-line assembly for performance. */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupts(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupts(unsigned int primask_value) +{ + + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ + +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupts(void) +{ + + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (_get_ipsr() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupts(); + __restore_interrupts(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = __disable_interrupts(); +#define TX_RESTORE __restore_interrupts(interrupt_save); + + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE); +#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save); +#endif + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M23/GNU Version 6.1.6 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + +#endif diff --git a/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h new file mode 100644 index 00000000..976f32be --- /dev/null +++ b/ports_module/cortex_m23/gnu/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports_module/cortex_m23/gnu/inc/txm_module_port.h b/ports_module/cortex_m23/gnu/inc/txm_module_port.h new file mode 100644 index 00000000..5d2de2a9 --- /dev/null +++ b/ports_module/cortex_m23/gnu/inc/txm_module_port.h @@ -0,0 +1,352 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M23/GNU */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M23 devices, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, one for module code protection, one for module data protection, + leaving five regions available for shared memory. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_CODE_INDEX 1 +#define TXM_MODULE_MPU_DATA_INDEX 2 + +#define TXM_MODULE_MPU_SHARED_INDEX 3 +#define TXM_MODULE_MPU_SHARED_ENTRIES 5 + +#define TXM_MODULE_ATTRIBUTE_NON_SHAREABLE 0x00 +#define TXM_MODULE_ATTRIBUTE_OUTER_SHAREABLE 0x10 +#define TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE 0x18 +#define TXM_MODULE_ATTRIBUTE_READ_WRITE 0x02 +#define TXM_MODULE_ATTRIBUTE_READ_ONLY 0x06 +#define TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER 0x01 +#define TXM_MODULE_ATTRIBUTE_REGION_ENABLE 0x01 +#define TXM_MODULE_ATTRIBUTE_MASK 0x1E +#define TXM_MODULE_ATTRIBUTE_INDEX 0x00 + +/* MAIR_ATTR settings +Device-nGnRE : 0b [Outer]0000 [Inner]0100 +Code WT RA : 0b [Outer]1010 [Inner]1010 +DATA WBWA RA : 0b [Outer]1111 [Inner]1111 +*/ + +/* Data aligned to 8 bytes (stacks must be 8-byte aligned). */ +#define TXM_MODULE_DATA_ALIGNMENT 8 + +/* MPU regions must be 32-byte aligned. */ +#define TXM_MODULE_MPU_ALIGNMENT 32 + +#define TXM_THREAD_SECURE_STACK_ALLOCATE_CALL TXM_MODULE_PORT_EXTENSION_API_ID_START +#define TXM_THREAD_SECURE_STACK_FREE_CALL (TXM_MODULE_PORT_EXTENSION_API_ID_START+1) + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RLAR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_base_address; + ULONG txm_module_mpu_region_limit_address; +} TXM_MODULE_MPU_INFO; + +/* Define the port-extensions to the module manager instance structure. */ +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#ifdef TX_SOURCE_CODE + +#endif + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2); + + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/GNU Version 6.1.6 *"; + +#endif diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..a7992839 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the GCC startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID _gcc_setup(TXM_MODULE_INSTANCE *); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M23/GNU */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _gcc_setup GNU global init function */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the GNU C environment. */ + _gcc_setup(thread_info -> txm_module_thread_entry_info_code_base_address); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c new file mode 100644 index 00000000..7a4bdf38 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_allocate.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocate a secure stack for the thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_ALLOCATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) stack_size, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c new file mode 100644 index 00000000..83e923fc --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_lib/src/txm_thread_secure_stack_free.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees the thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_FREE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h new file mode 100644 index 00000000..e612b45c --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/inc/txm_module_manager_dispatch_port.h @@ -0,0 +1,65 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Define port-specific dispatch functions. */ + +/* UINT _txe_thread_secure_stack_allocate( + TX_THREAD *thread_ptr, -> param_0 + ULONG stack_size -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate( + (TX_THREAD *) param_0, + (ULONG) param_1 + ); + return(return_value); +} + +/* UINT _txe_thread_secure_stack_free( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_free_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free( + (TX_THREAD *) param_0 + ); + return(return_value); +} \ No newline at end of file diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S new file mode 100644 index 00000000..08b635c4 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_initialize_low_level.S @@ -0,0 +1,210 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Initialize */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +SYSTEM_CLOCK = 6000000 +SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1) + +/* Setup the stack and heap areas. */ + +STACK_SIZE = 0x00000400 +HEAP_SIZE = 0x00000000 + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_initialize_low_level Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for any low-level processor */ +/* initialization, including setting up interrupt vectors, setting */ +/* up a periodic timer interrupt source, saving the system stack */ +/* pointer for use in ISR processing later, and finding the first */ +/* available RAM memory address for tx_application_define. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_initialize_low_level(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_initialize_low_level + .thumb_func +.type _tx_initialize_low_level, function +_tx_initialize_low_level: + + /* Disable interrupts during ThreadX initialization. */ + CPSID i + + /* Set base of available memory to end of non-initialised RAM area. */ + LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer + LDR r1, =Image$$ARM_LIB_STACK$$ZI$$Limit // Build first free address + ADDS r1, r1, #4 // + STR r1, [r0] // Setup first unused memory pointer + + /* Setup Vector Table Offset Register. */ + LDR r0, =0xE000ED08 // Build address of NVIC registers + LDR r1, =__Vectors // Pickup address of vector table + STR r1, [r0] // Set vector table address + +// /* Enable the cycle count register. */ +// +// LDR r0, =0xE0001000 // Build address of DWT register +// LDR r1, [r0] // Pickup the current value +// ORR r1, r1, #1 // Set the CYCCNTENA bit +// STR r1, [r0] // Enable the cycle count register + + /* Set system stack pointer from vector value. */ + LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer + LDR r1, =__Vectors // Pickup address of vector table + LDR r1, [r1] // Pickup reset stack pointer + STR r1, [r0] // Save system stack pointer + + /* Configure SysTick. */ + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] // Setup SysTick Reload Value + MOVW r1, #0x7 // Build SysTick Control Enable Value + STR r1, [r0, #0x10] // Setup SysTick Control + + /* Configure handler priorities. */ + LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD18 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD1C // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 8-11 Priority Registers + // Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 // Build address of NVIC registers + LDR r2, =0xD20 // + ADD r0, r0, r2 // + STR r1, [r0] // Setup System Handlers 12-15 Priority Registers + // Note: PnSV must be lowest priority, which is 0xFF + + /* Return to caller. */ + BX lr +// } + + +/* Define shells for each of the unused vectors. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_BadHandler + .thumb_func +.type __tx_BadHandler, function +__tx_BadHandler: + B __tx_BadHandler + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global __tx_IntHandler + .thumb_func +.type __tx_IntHandler, function +__tx_IntHandler: +// VOID InterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + + /* Do interrupt handler work here */ + /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SysTick_Handler + .thumb_func +.type SysTick_Handler, function +SysTick_Handler: +// VOID TimerInterruptHandler (VOID) +// { + PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +// } + + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global HardFault_Handler + .thumb_func +.type HardFault_Handler, function +HardFault_Handler: + // A stack overflow will trigger a hardfault. + // There is no CFSR in M23, so we will not try to + // determine if the fault is caused by a stack overflow + // or some other condition. + B HardFault_Handler + + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S new file mode 100644 index 00000000..14d772fb --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_restore.S @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_restore Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_restore(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_restore + .thumb_func +.type _tx_thread_context_restore, function +_tx_thread_context_restore: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S new file mode 100644 index 00000000..25050678 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_context_save.S @@ -0,0 +1,74 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_context_save Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is not needed for Cortex-M. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* None */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_context_save(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_context_save + .thumb_func +.type _tx_thread_context_save, function +_tx_thread_context_save: + /* Return to interrupt processing. */ + BX lr +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S new file mode 100644 index 00000000..4f05f3ff --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_control.S @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_control Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for changing the interrupt lockout */ +/* posture of the system. */ +/* */ +/* INPUT */ +/* */ +/* new_posture New interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_control(UINT new_posture) +// { + .section .text + .balign 4 + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_control + .thumb_func +.type _tx_thread_interrupt_control, function +_tx_thread_interrupt_control: + + /* Pickup current interrupt lockout posture. */ + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S new file mode 100644 index 00000000..3a1fc9f6 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_disable.S @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_disable Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for disabling interrupts and returning */ +/* the previous interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* old_posture Old interrupt lockout posture */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_interrupt_disable(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_disable + .thumb_func +.type _tx_thread_interrupt_disable, function +_tx_thread_interrupt_disable: + /* Return current interrupt lockout posture. */ + MRS r0, PRIMASK + CPSID i + BX lr +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S new file mode 100644 index 00000000..696c227b --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_interrupt_restore.S @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_interrupt_restore Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is responsible for restoring the previous */ +/* interrupt lockout posture. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* previous_posture Previous interrupt posture */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_interrupt_restore(UINT new_posture) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_interrupt_restore + .thumb_func +.type _tx_thread_interrupt_restore, function +_tx_thread_interrupt_restore: + /* Restore previous interrupt lockout posture. */ + MSR PRIMASK, r0 + BX lr +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S new file mode 100644 index 00000000..98caf079 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_schedule.S @@ -0,0 +1,645 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M23/GNU */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_schedule + .thumb_func +.type _tx_thread_schedule, function +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOVW r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + + .global MemManage_Handler + .global BusFault_Handler + .thumb_func +MemManage_Handler: + .thumb_func +BusFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r2,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r2, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r2, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r2, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r2, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r2, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r2, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r2, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r2, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r2, #36] // Save r1 + LDR r0, [r1, #8] // Pickup saved r2 + STR r0, [r2, #40] // Save r2 + STR r3, [r2, #44] // Save r3 + STR r4, [r2, #48] // Save r4 + STR r5, [r2, #52] // Save r5 + STR r6, [r2, #56] // Save r6 + STR r7, [r2, #60] // Save r7 + MOV r0, r8 // Move r8 to moveable register + STR r0, [r2, #64] // Save r8 + MOV r0, r9 // Move r9 to moveable register + STR r0, [r2, #68] // Save r9 + MOV r0, r10 // Move r10 to moveable register + STR r0, [r2, #72] // Save r10 + MOV r0, r11 // Move r11 to moveable register + STR r0, [r2, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r2, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r2, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r2, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r2, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + MOVW r1, #0x1 // + BICS r0, r0, r1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOVW r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts +#ifdef TX_SINGLE_MODE_SECURE + LDR r0, =0xFFFFFFFD // Exception return to secure +#else + LDR r0, =0xFFFFFFBC // Exception return to non-secure +#endif + MOV lr, r0 // Move exception return to lr + BX lr // Return from exception + + + /* Generic context switching PendSV handler. */ + + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global PendSV_Handler + .thumb_func +.type PendSV_Handler, function + /* Get current thread value and new thread pointer. */ +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, r1} // Recover LR + MOV lr, r1 + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + + MOVW r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 // Allocate stack space + STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // + MOV r5, r9 // + MOV r6, r10 // + MOV r7, r11 // + SUBS r3, r3, #32 // Allocate stack space + STM r3!, {r4-r7} // + SUBS r3, r3, #20 // Allocate stack space + MOV r5, lr // + STR r5, [r3] // Save LR on the stack + STR r3, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, =0xC4 // Secure stack index offset + LDR r5, [r1, r5] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0-r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0-r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + MOVW r5, #0 // Build clear value + STR r5, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + LDR r7, =0x08000000 // Build clear PendSV value + LDR r5, =0xE000ED04 // Build base NVIC address + STR r7, [r5] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADDS r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r5, =0xC4 // Secure stack index offset + LDR r0, [r1, r5] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0, r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0, r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + // Set up CONTROL register based on user mode flag (privileged/unprivileged mode) + MRS r5, CONTROL // Pickup current CONTROL register + MOVS r2, #0x98 // Index of current user mode flag + LDR r4, [r1, r2] // Pickup current user mode flag + MOVW r0, #0x1 + BICS r5, r5, r0 // Clear the UNPRIV bit + ORRS r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + // Determine if MPU needs to be configured + LDR r0, =0xE000ED94 // Build MPU control reg address + MOVW r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + MOVS r2, #0x90 // Index of module instance pointer + LDR r0, [r1, r2] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + MOV r8, r1 // Copy thread ptr + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + + // Initialize loop to configure MPU registers + // Order doesn't matter, so txm_module_instance_mpu_registers[0] + // will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0. + MOVS r3, #0x64 // Index of MPU register settings in thread control block + ADD r0, r0, r3 // Build address of MPU register start in thread control block + MOVS r5, #0 // Select region 0 + LDR r4, =0xE000ED98 // Region register address + // Loop to load MPU registers +_tx_mpu_loop: + LDR r1, =0xE000ED9C // Build address of MPU base register + STR r5, [r4] // Set region + LDM r0!, {r2-r3} // Get MPU settings from the module + STM r1!, {r2-r3} // Set MPU registers for region + ADDS r5, r5, #1 // Increment to next region + CMP r5, #8 // Check if all regions have been set + BNE _tx_mpu_loop + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOVS r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU + MOV r1, r8 // Get copied thread ptr + +skip_mpu_setup: + + // Restore the thread context and PSP + LDR r3, [r1, #8] // Pickup thread's stack pointer + LDR r5, [r3] // Recover saved LR + ADDS r3, r3, #4 // Position past LR + MOV lr, r5 // Restore LR + LDM r3!, {r4-r7} // Recover thread's registers (r8-r11) + MOV r11, r7 + MOV r10, r6 + MOV r9, r5 + MOV r8, r4 + LDM r3!, {r4-r7} // Recover thread's registers (r4-r7) + MSR PSP, r3 // Setup the thread's stack pointer + + BX lr // Return to thread! + + + + /* SVC Handler. */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global SVC_Handler + .thumb_func +.type SVC_Handler, function +SVC_Handler: + MOV r0, lr + MOVS r1, #0x04 + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_load_msp + MRS r0, PSP // Get PSP + B _tx_get_svc +_tx_load_msp: + MRS r0, MSP // Get MSP +_tx_get_svc: + LDR r1, [r0,#24] // Load saved PC from stack + LDR r3, =-2 + LDRB r2, [r1,r3] // Load SVC number + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + CMP r2, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r2, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + CMP r2, #3 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 3, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + BEQ _tx_entry_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_entry_continue: + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0 // Build clear value + MOVS r0, #0x98 // Index of current user mode + STR r1, [r2, r0] // Clear the current user mode selection for thread + MOVS r0, #0xA0 // Index of saved LR + STR r3, [r2, r0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + MOVS r0, #0x90 // Index of module instance ptr + LDR r0, [r2, r0] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + MOVS r1, #2 // MPU protection flag + TST r0, r1 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + MOVS r0, #0xA8 // Index of module kernel stack end + LDR r0, [r2, r0] // Load the module kernel stack end + MOVS r1, #0xA4 // Index of module kernel stack start + LDR r1, [r2, r1] // Load the module kernel stack start + MSR PSPLIM, r1 // Set stack limit +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOVS r3, #0xAC // Index of module kernel stack size + LDR r3, [r2, r3] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + MOVS r1, #0xB0 // Index of module stack pointer + STR r3, [r2, r1] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + SUBS r0, r0, #32 // Start at top of hardware stack + LDMIA r3!, {r1,r2} // Get r0, r1 from thread stack + STMIA r0!, {r1,r2} // Insert r0, r1 into kernel stack + LDMIA r3!, {r1,r2} // Get r2, r3 from thread stack + STMIA r0!, {r1,r2} // Insert r2, r3 into kernel stack + LDMIA r3!, {r1,r2} // Get r12, lr from thread stack + STMIA r0!, {r1,r2} // Insert r12, lr into kernel stack + LDMIA r3!, {r1,r2} // Get pc, xpsr from thread stack + STMIA r0!, {r1,r2} // Insert pc, xpsr into kernel stack + SUBS r0, r0, #32 // Go back to top of stack + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + MOVW r1, #0x1 // + BICS r0, r0, r1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + BEQ _tx_exit_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_exit_continue: + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0x9C // Index of user mode + MOVS r3, #0x98 // Index of current user mode + LDR r1, [r2, r1] // Pick up user mode + STR r1, [r2, r3] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + MOVS r0, #0x90 // Index of module instance ptr + LDR r0, [r2, r0] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + MOVS r1, #2 // MPU protection flag + TST r0, r1 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + + MOVS r0, #0xB4 // Index of module thread stack start + LDR r0, [r2, r0] // Load the module thread stack start + MSR PSPLIM, r0 // Set stack limit +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOVS r1, #0xB8 // Index of module thread stack end + LDR r1, [r2, r1] // Load the module thread stack end + MOVS r3, #0xBC // Index of module thread stack size + LDR r3, [r2, r3] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + MOVS r1, #0xB0 // Index of module thread stack pointer + LDR r0, [r2, r1] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} // Get r0, r1 from kernel stack + STM r0!,{r1-r2} // Insert r0, r1 into thread stack + LDM r3!,{r1-r2} // Get r2, r3 from kernel stack + STM r0!,{r1-r2} // Insert r2, r3 into thread stack + LDM r3!,{r1-r2} // Get r12, lr from kernel stack + STM r0!,{r1-r2} // Insert r12, lr into thread stack + LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack + STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + SUBS r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0x9C // Index of user mode + LDR r1, [r2, r1] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORRS r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) +_tx_svc_secure_alloc: + LDR r2, =_tx_alloc_return // Load address of where we should have come from + CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? + BEQ _tx_alloc_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_alloc_continue: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr + +_tx_svc_secure_free: + LDR r2, =_tx_free_return // Load address of where we should have come from + CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? + BEQ _tx_free_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_free_continue: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + + /* Kernel entry function from user mode. */ + + .global _txm_module_manager_kernel_dispatch + .align 5 + .syntax unified +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + .global _txm_module_manager_user_mode_entry + .thumb_func +_txm_module_manager_user_mode_entry: + SVC 3 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR r2, =0xA0 // Index of saved LR + LDR r1, [r3, r2] // Pickup saved LR from original call + MOV lr, r1 + SVC 4 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } + +.end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..0e8cbde0 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack.c @@ -0,0 +1,497 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* 8 bytes added to stack size to "seal" stack. */ +#define TX_THREAD_STACK_SEAL_SIZE 8 +#define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/GNU */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* 12-31-2020 Scott Larson Modified comment(s), and */ +/* fixed M23 GCC build, */ +/* resulting in version 6.1.3 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + ULONG control; + + /* Set secure mode to use PSP. */ + asm volatile("MRS %0, CONTROL" : "=r" (control)); /* Get CONTROL register. */ + control |= 2; /* Use PSP. */ + asm volatile("MSR CONTROL, %0" :: "r" (control)); /* Set CONTROL register. */ + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/GNU */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* added stack sealing, */ +/* resulting in version 6.1.1 */ +/* 12-31-2020 Scott Larson Modified comment(s), and */ +/* fixed M23 GCC build, */ +/* resulting in version 6.1.3 */ + +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG ipsr; +ULONG psplim_ns; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack & seal. */ + stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Seal bottom of stack. */ + *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at its stack start and PSPLIM_NS */ + asm volatile("MRS %0, PSPLIM_NS" : "=r" (psplim_ns)); /* Get PSPLIM_NS register. */ + if(((ULONG) thread_ptr -> tx_thread_stack_start & 0xFFFFFFF8) == psplim_ns) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_limit))); + asm volatile("MSR PSP, %0" :: "r" ((ULONG)(info_ptr -> tx_thread_secure_stack_ptr))); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/GNU */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* 12-31-2020 Scott Larson Modified comment(s), and */ +/* fixed M23 GCC build, */ +/* resulting in version 6.1.3 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG ipsr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/GNU */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* 12-31-2020 Scott Larson Modified comment(s), and */ +/* fixed M23 GCC build, */ +/* resulting in version 6.1.3 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; +ULONG ipsr; + + /* This function should be called from scheduler only. */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + asm volatile("MRS %0, PSP" : "=r" (sp)); /* Get PSP register. */ + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + asm volatile("MSR PSPLIM, %0" :: "r" (0)); + asm volatile("MSR PSP, %0" :: "r" (0)); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/GNU */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* 12-31-2020 Scott Larson Modified comment(s), and */ +/* fixed M23 GCC build, */ +/* resulting in version 6.1.3 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG ipsr; + + /* This function should be called from scheduler only. */ + asm volatile("MRS %0, IPSR" : "=r" (ipsr)); /* Get IPSR register. */ + if (ipsr == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + asm volatile("MSR PSPLIM, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_limit)); + asm volatile("MSR PSP, %0" :: "r" ((ULONG)info_ptr -> tx_thread_secure_stack_ptr)); + + return; +} + +#endif diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S new file mode 100644 index 00000000..1dfbc482 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_allocate.S @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_allocate Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to allocate a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 1 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_allocate + .global _tx_alloc_return + .thumb_func +.type _tx_thread_secure_stack_allocate, function +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 1 +_tx_alloc_return: + CMP r3, #0 // If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_alloc_return_interrupt_enabled: + BX lr + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S new file mode 100644 index 00000000..cfe400fa --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_secure_stack_free.S @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_free Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enters the SVC handler to free a secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* SVC 2 */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_secure_stack_free + .global _tx_free_return + .thumb_func +.type _tx_thread_secure_stack_free, function +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK // Save interrupt mask + CPSIE i // Enable interrupts for SVC call + SVC 2 +_tx_free_return: + CMP r3, #0 // If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i // Otherwise, disable interrupts +#else + // Executing in single mode - this function is not needed. + MOVS r0, #0xFF // Feature not enabled +#endif +_free_return_interrupt_enabled: + BX lr + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S new file mode 100644 index 00000000..704c5dfd --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_build.S @@ -0,0 +1,141 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_build Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread control blk */ +/* function_ptr Pointer to return function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_stack_build + .thumb_func +.type _tx_thread_stack_build, function +_tx_thread_stack_build: + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M23 should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #8] // Store initial r9 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r3, [r2, #36] // Store initial r0 + STR r3, [r2, #40] // Store initial r1 + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's + // control block + BX lr // Return to caller +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S new file mode 100644 index 00000000..7aa911b0 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_thread_system_return.S @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_system_return Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is target processor specific. It is used to transfer */ +/* control from a thread back to the ThreadX system. Only a */ +/* minimal context is saved since the compiler assumes temp registers */ +/* are going to get slicked by a function call anyway. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_schedule Thread scheduling loop */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_system_return(VOID) +// { + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_thread_system_return + .thumb_func +.type _tx_thread_system_return, function +_tx_thread_system_return: + /* Return to real scheduler via PendSV. Note that this routine is often + replaced with in-line assembly in tx_port.h to improved performance. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + MRS r0, IPSR // Pickup IPSR + CMP r0, #0 // Is it a thread returning? + BNE _isr_context // If ISR, skip interrupt enable + MRS r1, PRIMASK // Thread context returning, pickup PRIMASK + CPSIE i // Enable interrupts + MSR PRIMASK, r1 // Restore original interrupt posture +_isr_context: + BX lr // Return to caller +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S new file mode 100644 index 00000000..0e2ea836 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/tx_timer_interrupt.S @@ -0,0 +1,262 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Timer */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_timer_interrupt Cortex-M23/GNU */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes the hardware timer interrupt. This */ +/* processing includes incrementing the system clock and checking for */ +/* time slice and/or timer expiration. If either is found, the */ +/* interrupt context save/restore functions are called along with the */ +/* expiration functions. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_timer_expiration_process Timer expiration processing */ +/* _tx_thread_time_slice Time slice interrupted thread */ +/* */ +/* CALLED BY */ +/* */ +/* interrupt vector */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +/* VOID _tx_timer_interrupt(VOID) +{ */ + .section .text + .balign 4 + .syntax unified + .eabi_attribute Tag_ABI_align_preserved, 1 + .global _tx_timer_interrupt + .thumb_func +.type _tx_timer_interrupt, function +_tx_timer_interrupt: + + /* Upon entry to this routine, it is assumed that the compiler scratch registers are available + for use. */ + + /* Increment the system clock. */ + // _tx_timer_system_clock++; + + MOVW r1, #:lower16:_tx_timer_system_clock // Pickup address of system clock + MOVT r1, #:upper16:_tx_timer_system_clock + LDR r0, [r1, #0] // Pickup system clock + ADDS r0, r0, #1 // Increment system clock + STR r0, [r1, #0] // Store new system clock + + /* Test for time-slice expiration. */ + // if (_tx_timer_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_time_slice // Pickup address of time-slice + MOVT r3, #:upper16:_tx_timer_time_slice + LDR r2, [r3, #0] // Pickup time-slice + CBZ r2, __tx_timer_no_time_slice // Is it non-active? + // Yes, skip time-slice processing + + /* Decrement the time_slice. */ + // _tx_timer_time_slice--; + + SUBS r2, r2, #1 // Decrement the time-slice + STR r2, [r3, #0] // Store new time-slice value + + /* Check for expiration. */ + // if (__tx_timer_time_slice == 0) + + CBNZ r2, __tx_timer_no_time_slice // Has it expired? + + /* Set the time-slice expired flag. */ + // _tx_timer_expired_time_slice = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup address of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + MOVW r0, #1 // Build expired value + STR r0, [r3, #0] // Set time-slice expiration flag + + // } + +__tx_timer_no_time_slice: + + /* Test for timer expiration. */ + // if (*_tx_timer_current_ptr) + // { + + MOVW r1, #:lower16:_tx_timer_current_ptr // Pickup current timer pointer address + MOVT r1, #:upper16:_tx_timer_current_ptr + LDR r0, [r1, #0] // Pickup current timer + LDR r2, [r0, #0] // Pickup timer list entry + CBZ r2, __tx_timer_no_timer // Is there anything in the list? + // No, just increment the timer + + /* Set expiration flag. */ + // _tx_timer_expired = TX_TRUE; + + MOVW r3, #:lower16:_tx_timer_expired // Pickup expiration flag address + MOVT r3, #:upper16:_tx_timer_expired + MOVW r2, #1 // Build expired value + STR r2, [r3, #0] // Set expired flag + B __tx_timer_done // Finished timer processing + + // } + // else + // { +__tx_timer_no_timer: + + /* No timer expired, increment the timer pointer. */ + // _tx_timer_current_ptr++; + + ADDS r0, r0, #4 // Move to next timer + + /* Check for wrap-around. */ + // if (_tx_timer_current_ptr == _tx_timer_list_end) + + MOVW r3, #:lower16:_tx_timer_list_end // Pickup addr of timer list end + MOVT r3, #:upper16:_tx_timer_list_end + LDR r2, [r3, #0] // Pickup list end + CMP r0, r2 // Are we at list end? + BNE __tx_timer_skip_wrap // No, skip wrap-around logic + + /* Wrap to beginning of list. */ + // _tx_timer_current_ptr = _tx_timer_list_start; + + MOVW r3, #:lower16:_tx_timer_list_start // Pickup addr of timer list start + MOVT r3, #:upper16:_tx_timer_list_start + LDR r0, [r3, #0] // Set current pointer to list start + +__tx_timer_skip_wrap: + + STR r0, [r1, #0] // Store new current timer pointer + // } + +__tx_timer_done: + + + /* See if anything has expired. */ + // if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of expired flag + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup time-slice expired flag + CBNZ r2, __tx_something_expired // Did a time-slice expire? + // If non-zero, time-slice expired + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of other expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired // Did a timer expire? + // No, nothing expired + +__tx_something_expired: + + PUSH {r0, lr} // Save the lr register on the stack + // and save r0 just to keep 8-byte alignment + + /* Did a timer expire? */ + // if (_tx_timer_expired) + // { + + MOVW r1, #:lower16:_tx_timer_expired // Pickup addr of expired flag + MOVT r1, #:upper16:_tx_timer_expired + LDR r0, [r1, #0] // Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate // Check for timer expiration + // If not set, skip timer activation + + /* Process timer expiration. */ + // _tx_timer_expiration_process(); + + BL _tx_timer_expiration_process // Call the timer expiration handling routine + + // } +__tx_timer_dont_activate: + + /* Did time slice expire? */ + // if (_tx_timer_expired_time_slice) + // { + + MOVW r3, #:lower16:_tx_timer_expired_time_slice // Pickup addr of time-slice expired + MOVT r3, #:upper16:_tx_timer_expired_time_slice + LDR r2, [r3, #0] // Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration // See if the flag is set + // No, skip time-slice processing + + /* Time slice interrupted thread. */ + // _tx_thread_time_slice(); + + BL _tx_thread_time_slice // Call time-slice processing + MOVW r0, #:lower16:_tx_thread_preempt_disable // Build address of preempt disable flag + MOVT r0, #:upper16:_tx_thread_preempt_disable + + LDR r1, [r0] // Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice // Yes, skip the PendSV logic + MOVW r0, #:lower16:_tx_thread_current_ptr // Build current thread pointer address + MOVT r0, #:upper16:_tx_thread_current_ptr + + LDR r1, [r0] // Pickup the current thread pointer + MOVW r2, #:lower16:_tx_thread_execute_ptr // Build execute thread pointer address + MOVT r2, #:upper16:_tx_thread_execute_ptr + + LDR r3, [r2] // Pickup the execute thread pointer + LDR r0, =0xE000ED04 // Build address of control register + LDR r2, =0x10000000 // Build value for PendSV bit + CMP r1, r3 // Are they the same? + BEQ __tx_timer_skip_time_slice // If the same, there was no time-slice performed + STR r2, [r0] // Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: + // } + +__tx_timer_not_ts_expiration: + + POP {r0, r1} // Recover lr register (r0 is just there for + MOV lr, r1 // the 8-byte stack alignment + + // } + +__tx_timer_nothing_expired: + + DSB // Complete all memory access + BX lr // Return to caller + +// } + .end diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..f3a37aa9 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + + /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ + *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); + *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); + + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ + *code_alignment = TXM_MODULE_MPU_ALIGNMENT; + *data_alignment = TXM_MODULE_MPU_ALIGNMENT; +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..4869407c --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. The start_address must be 32-byte aligned. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG address; +ULONG shared_index; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address must adhere to Cortex-M23 MPU alignment. */ + address = (ULONG) start_address; + if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address. Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Set base address register with start address, sanitized attributes and execute never. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; + + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..974ffebe --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..938e484c --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..faa7551f --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M23 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU settings for the module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* none */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; + + /* Setup MPU region for kernel mode entry. */ + /* Set base address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, inner shareable, read only. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_base_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY; + /* Set the limit address, attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_limit_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of kernel mode entry setup. */ + + + /* Setup MPU region for module code protection. */ + /* Set base address register to module code address, which should be at least 32-byte aligned. + Mask address to proper range, inner shareable, read only. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_code_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY; + /* Set the limit address (code start + code size-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_code_start + module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of module code protection. */ + + + /* Setup MPU region for module data protection. */ + /* Set base address register to module data address, which should be at least 32-byte aligned. + Mask address to proper range, inner shareable, read write, execute never. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of module data protection. */ + + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c new file mode 100644 index 00000000..ed9f0ea4 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_port_dispatch.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_port_dispatch Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function dispatches the module's kernel request based upon the */ +/* ID and parameters specified in the request. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module pointer */ +/* kernel_request Module's kernel request */ +/* param_0 First parameter */ +/* param_1 Second parameter */ +/* param_2 Third parameter */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* Port-specific ThreadX API Calls */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value = TX_NOT_AVAILABLE; + + switch(kernel_request) + { + case TXM_THREAD_SECURE_STACK_ALLOCATE_CALL: + { + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate( + (TX_THREAD *) param_0, + (ULONG) param_1 + ); + break; + } + + case TXM_THREAD_SECURE_STACK_FREE_CALL: + { + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free( + (TX_THREAD *) param_0 + ); + break; + } + + default: + { + /* Unhandled kernel request, return an error! */ + break; + } + } + + return(return_value); +} diff --git a/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S new file mode 100644 index 00000000..1309b9a9 --- /dev/null +++ b/ports_module/cortex_m23/gnu/module_manager/src/txm_module_manager_thread_stack_build.S @@ -0,0 +1,144 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + .text + .align 4 + .syntax unified +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M23/GNU */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + .global _txm_module_manager_thread_stack_build + .thumb_func +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #8] // Store initial r9 (data base register) + MOVW r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c new file mode 100644 index 00000000..939433cd --- /dev/null +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.c @@ -0,0 +1,428 @@ +/* This is a small demo of the high-performance ThreadX kernel running as a module. It includes + examples of eight threads of different priorities, using a message queue, semaphore, mutex, + event flags group, byte pool, and block pool. */ + +/* Specify that this is a module! */ + +#define TXM_MODULE + + +/* Include the ThreadX module definitions. */ + +#include "txm_module.h" + + +/* Define constants. */ + +#define DEMO_STACK_SIZE 512 +#define DEMO_BYTE_POOL_SIZE 6000 +#define DEMO_BLOCK_POOL_SIZE 100 +#define DEMO_QUEUE_SIZE 100 + + +/* Define the pool space in the bss section of the module. ULONG is used to + get the word alignment. */ + +ULONG demo_module_pool_space[DEMO_BYTE_POOL_SIZE / 4]; + + +/* Define the ThreadX object control blocks... */ + +TX_THREAD *thread_0; +TX_THREAD *thread_1; +TX_THREAD *thread_2; +TX_THREAD *thread_3; +TX_THREAD *thread_4; +TX_THREAD *thread_5; +TX_THREAD *thread_6; +TX_THREAD *thread_7; +TX_QUEUE *queue_0; +TX_SEMAPHORE *semaphore_0; +TX_MUTEX *mutex_0; +TX_EVENT_FLAGS_GROUP *event_flags_0; +TX_BYTE_POOL *byte_pool_0; +TX_BLOCK_POOL *block_pool_0; + + +/* Define the counters used in the demo application... */ + +ULONG thread_0_counter; +ULONG thread_1_counter; +ULONG thread_1_messages_sent; +ULONG thread_2_counter; +ULONG thread_2_messages_received; +ULONG thread_3_counter; +ULONG thread_4_counter; +ULONG thread_5_counter; +ULONG thread_6_counter; +ULONG thread_7_counter; +ULONG semaphore_0_puts; +ULONG event_0_sets; +ULONG queue_0_sends; + +/* Define thread prototypes. */ + +void thread_0_entry(ULONG thread_input); +void thread_1_entry(ULONG thread_input); +void thread_2_entry(ULONG thread_input); +void thread_3_and_4_entry(ULONG thread_input); +void thread_5_entry(ULONG thread_input); +void thread_6_and_7_entry(ULONG thread_input); + +void semaphore_0_notify(TX_SEMAPHORE *semaphore_ptr) +{ + + if (semaphore_ptr == semaphore_0) + semaphore_0_puts++; +} + + +void event_0_notify(TX_EVENT_FLAGS_GROUP *event_flag_group_ptr) +{ + + if (event_flag_group_ptr == event_flags_0) + event_0_sets++; +} + + +void queue_0_notify(TX_QUEUE *queue_ptr) +{ + + if (queue_ptr == queue_0) + queue_0_sends++; +} + + +/* Define the module start function. */ + +void demo_module_start(ULONG id) +{ + +CHAR *pointer; + + /* Allocate all the objects. In MPU mode, modules cannot allocate control blocks within + their own memory area so they cannot corrupt the resident portion of ThreadX by overwriting + the control block(s). */ + txm_module_object_allocate((void*)&thread_0, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_1, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_2, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_3, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_4, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_5, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_6, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&thread_7, sizeof(TX_THREAD)); + txm_module_object_allocate((void*)&queue_0, sizeof(TX_QUEUE)); + txm_module_object_allocate((void*)&semaphore_0, sizeof(TX_SEMAPHORE)); + txm_module_object_allocate((void*)&mutex_0, sizeof(TX_MUTEX)); + txm_module_object_allocate((void*)&event_flags_0, sizeof(TX_EVENT_FLAGS_GROUP)); + txm_module_object_allocate((void*)&byte_pool_0, sizeof(TX_BYTE_POOL)); + txm_module_object_allocate((void*)&block_pool_0, sizeof(TX_BLOCK_POOL)); + + + /* Create a byte memory pool from which to allocate the thread stacks. */ + tx_byte_pool_create(byte_pool_0, "module byte pool 0", (UCHAR*)demo_module_pool_space, DEMO_BYTE_POOL_SIZE); + + /* Put system definition stuff in here, e.g. thread creates and other assorted + create information. */ + + /* Allocate the stack for thread 0. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create the main thread. */ + tx_thread_create(thread_0, "module thread 0", thread_0_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + + + /* Allocate the stack for thread 1. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 1 and 2. These threads pass information through a ThreadX + message queue. It is also interesting to note that these threads have a time + slice. */ + tx_thread_create(thread_1, "module thread 1", thread_1_entry, 1, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 2. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_2, "module thread 2", thread_2_entry, 2, + pointer, DEMO_STACK_SIZE, + 16, 16, 4, TX_AUTO_START); + + /* Allocate the stack for thread 3. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 3 and 4. These threads compete for a ThreadX counting semaphore. + An interesting thing here is that both threads share the same instruction area. */ + tx_thread_create(thread_3, "module thread 3", thread_3_and_4_entry, 3, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 4. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_4, "module thread 4", thread_3_and_4_entry, 4, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 5. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create thread 5. This thread simply pends on an event flag which will be set + by thread_0. */ + tx_thread_create(thread_5, "module thread 5", thread_5_entry, 5, + pointer, DEMO_STACK_SIZE, + 4, 4, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 6. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + /* Create threads 6 and 7. These threads compete for a ThreadX mutex. */ + tx_thread_create(thread_6, "module thread 6", thread_6_and_7_entry, 6, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the stack for thread 7. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT); + + tx_thread_create(thread_7, "module thread 7", thread_6_and_7_entry, 7, + pointer, DEMO_STACK_SIZE, + 8, 8, TX_NO_TIME_SLICE, TX_AUTO_START); + + /* Allocate the message queue. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_QUEUE_SIZE*sizeof(ULONG), TX_NO_WAIT); + + /* Create the message queue shared by threads 1 and 2. */ + tx_queue_create(queue_0, "module queue 0", TX_1_ULONG, pointer, DEMO_QUEUE_SIZE*sizeof(ULONG)); + + tx_queue_send_notify(queue_0, queue_0_notify); + + /* Create the semaphore used by threads 3 and 4. */ + tx_semaphore_create(semaphore_0, "module semaphore 0", 1); + + tx_semaphore_put_notify(semaphore_0, semaphore_0_notify); + + /* Create the event flags group used by threads 1 and 5. */ + tx_event_flags_create(event_flags_0, "module event flags 0"); + + tx_event_flags_set_notify(event_flags_0, event_0_notify); + + /* Create the mutex used by thread 6 and 7 without priority inheritance. */ + tx_mutex_create(mutex_0, "module mutex 0", TX_NO_INHERIT); + + /* Allocate the memory for a small block pool. */ + tx_byte_allocate(byte_pool_0, (VOID **) &pointer, DEMO_BLOCK_POOL_SIZE, TX_NO_WAIT); + + /* Create a block memory pool to allocate a message buffer from. */ + tx_block_pool_create(block_pool_0, "module block pool 0", sizeof(ULONG), pointer, DEMO_BLOCK_POOL_SIZE); + + /* Allocate a block and release the block memory. */ + tx_block_allocate(block_pool_0, (VOID **) &pointer, TX_NO_WAIT); + + /* Release the block back to the pool. */ + tx_block_release(pointer); +} + + +/* Define the test threads. */ + +void thread_0_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sits in while-forever-sleep loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_0_counter++; + + /* Sleep for 10 ticks. */ + tx_thread_sleep(10); + + /* Set event flag 0 to wakeup thread 5. */ + status = tx_event_flags_set(event_flags_0, 0x1, TX_OR); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_1_entry(ULONG thread_input) +{ + +UINT status; + + + /* This thread simply sends messages to a queue shared by thread 2. */ + while(1) + { + + /* Increment the thread counter. */ + thread_1_counter++; + + /* Send message to queue 0. */ + status = tx_queue_send(queue_0, &thread_1_messages_sent, TX_WAIT_FOREVER); + + /* Check completion status. */ + if (status != TX_SUCCESS) + break; + + /* Increment the message sent. */ + thread_1_messages_sent++; + } +} + + +void thread_2_entry(ULONG thread_input) +{ + +ULONG received_message; +UINT status; + + /* This thread retrieves messages placed on the queue by thread 1. */ + while(1) + { + /* Test memory handler. */ + *(ULONG *)0x64005000 = 0xCDCDCDCD; + + + /* Increment the thread counter. */ + thread_2_counter++; + + /* Retrieve a message from the queue. */ + status = tx_queue_receive(queue_0, &received_message, TX_WAIT_FOREVER); + + /* Check completion status and make sure the message is what we + expected. */ + if ((status != TX_SUCCESS) || (received_message != thread_2_messages_received)) + break; + + /* Otherwise, all is okay. Increment the received message count. */ + thread_2_messages_received++; + } +} + + +void thread_3_and_4_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 3 and thread 4. As the loop + below shows, these function compete for ownership of semaphore_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 3) + thread_3_counter++; + else + thread_4_counter++; + + /* Get the semaphore with suspension. */ + status = tx_semaphore_get(semaphore_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the semaphore. */ + tx_thread_sleep(2); + + /* Release the semaphore. */ + status = tx_semaphore_put(semaphore_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + +void thread_5_entry(ULONG thread_input) +{ + +UINT status; +ULONG actual_flags; + + + /* This thread simply waits for an event in a forever loop. */ + while(1) + { + + /* Increment the thread counter. */ + thread_5_counter++; + + /* Wait for event flag 0. */ + status = tx_event_flags_get(event_flags_0, 0x1, TX_OR_CLEAR, + &actual_flags, TX_WAIT_FOREVER); + + /* Check status. */ + if ((status != TX_SUCCESS) || (actual_flags != 0x1)) + break; + } +} + + +void thread_6_and_7_entry(ULONG thread_input) +{ + +UINT status; + + + /* This function is executed from thread 6 and thread 7. As the loop + below shows, these function compete for ownership of mutex_0. */ + while(1) + { + + /* Increment the thread counter. */ + if (thread_input == 6) + thread_6_counter++; + else + thread_7_counter++; + + /* Get the mutex with suspension. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Get the mutex again with suspension. This shows + that an owning thread may retrieve the mutex it + owns multiple times. */ + status = tx_mutex_get(mutex_0, TX_WAIT_FOREVER); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Sleep for 2 ticks to hold the mutex. */ + tx_thread_sleep(2); + + /* Release the mutex. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + + /* Release the mutex again. This will actually + release ownership since it was obtained twice. */ + status = tx_mutex_put(mutex_0); + + /* Check status. */ + if (status != TX_SUCCESS) + break; + } +} + + diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf new file mode 100644 index 00000000..8cfe4766 --- /dev/null +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module.icf @@ -0,0 +1,53 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x080f0000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080fffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x64002800; +define symbol __ICFEDIT_region_RAM_end__ = 0x64100000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0; +define symbol __ICFEDIT_size_svcstack__ = 0; +define symbol __ICFEDIT_size_irqstack__ = 0; +define symbol __ICFEDIT_size_fiqstack__ = 0; +define symbol __ICFEDIT_size_undstack__ = 0; +define symbol __ICFEDIT_size_abtstack__ = 0; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +//define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +//define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +//define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +//define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +//define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +//define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +//place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +define movable block ROPI with alignment = 4, fixed order +{ + ro object txm_module_preamble.o, + ro, + ro data +}; + +define movable block RWPI with alignment = 8, fixed order, static base +{ + rw, + block HEAP +}; + +place in ROM_region { block ROPI }; +place in RAM_region { block RWPI }; + diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c new file mode 100644 index 00000000..28299f6c --- /dev/null +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.c @@ -0,0 +1,107 @@ +/* Small demonstration of the ThreadX module manager. */ + +#include "tx_api.h" +#include "txm_module.h" + + +#define DEMO_STACK_SIZE 1024 + +/* Define the ThreadX object control blocks... */ + +TX_THREAD module_manager; +TXM_MODULE_INSTANCE my_module; + + +/* Define the object pool area. */ + +UCHAR object_memory[16384]; + + +/* Define the count of memory faults. */ + +ULONG memory_faults; + + +/* Define thread prototypes. */ + +void module_manager_entry(ULONG thread_input); + + +/* Define fault handler. */ + +VOID module_fault_handler(TX_THREAD *thread, TXM_MODULE_INSTANCE *module) +{ + + /* Just increment the fault counter. */ + memory_faults++; +} + +/* Define main entry point. */ + +int main() +{ + /* Enter the ThreadX kernel. */ + tx_kernel_enter(); +} + + +/* Define what the initial system looks like. */ + +void tx_application_define(void *first_unused_memory) +{ + +CHAR *pointer = (CHAR*)first_unused_memory; + + + tx_thread_create(&module_manager, "Module Manager Thread", module_manager_entry, 0, + pointer, DEMO_STACK_SIZE, + 1, 1, TX_NO_TIME_SLICE, TX_AUTO_START); + pointer = pointer + DEMO_STACK_SIZE; +} + + + + +/* Define the test threads. */ + +void module_manager_entry(ULONG thread_input) +{ + + /* Initialize the module manager. */ + txm_module_manager_initialize((VOID *) 0x64000000, 0x1000000); + + txm_module_manager_object_pool_create(object_memory, sizeof(object_memory)); + + /* Register a fault handler. */ + txm_module_manager_memory_fault_notify(module_fault_handler); + + /* Load the module that is already there, in this example it is placed there by the multiple image download. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); + + /* Enable 128 byte read/write shared memory region at 0x64005000. */ + txm_module_manager_external_memory_enable(&my_module, (void *) 0x64005000, 128, TXM_MODULE_ATTRIBUTE_READ_WRITE); + + /* Start the module. */ + txm_module_manager_start(&my_module); + + /* Sleep for a while.... */ + tx_thread_sleep(1000); + + /* Stop the module. */ + txm_module_manager_stop(&my_module); + + /* Unload the module. */ + txm_module_manager_unload(&my_module); + + /* Load the module that is already there. */ + txm_module_manager_in_place_load(&my_module, "my module", (VOID *) 0x080F0000); + + /* Start the module again. */ + txm_module_manager_start(&my_module); + + /* Now just spin... */ + while(1) + { + tx_thread_sleep(100); + } +} diff --git a/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.icf b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.icf new file mode 100644 index 00000000..c112bf12 --- /dev/null +++ b/ports_module/cortex_m23/iar/example_build/sample_threadx_module_manager.icf @@ -0,0 +1,38 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20020000; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define symbol __EXTRAM_start__ = 0x64000000; +define symbol __EXTRAM_end__ = 0x641FFFFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region EXTRAM_region = mem:[from __EXTRAM_start__ to __EXTRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in EXTRAM_region { section EXT_RAM }; + +place in RAM_region { last section FREE_MEM}; diff --git a/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s new file mode 100644 index 00000000..92a5f4d2 --- /dev/null +++ b/ports_module/cortex_m23/iar/example_build/tx_initialize_low_level.s @@ -0,0 +1,204 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __main + EXTERN __vector_table + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_stack_error_handler +; +; +SYSTEM_CLOCK EQU 96000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =__tx_free_memory_start ; Build first free address + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000ED08 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define shells for each of the unused vectors. */ +; + PUBLIC __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + + PUBLIC __tx_IntHandler +__tx_IntHandler: +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + + PUBLIC __tx_SysTickHandler + PUBLIC SysTick_Handler +SysTick_Handler: +__tx_SysTickHandler: +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + + PUBLIC HardFault_Handler +HardFault_Handler: + ; A stack overflow will trigger a hardfault. + ; There is no CFSR in M23, so we will not try to + ; determine if the fault is caused by a stack overflow + ; or some other condition. + B HardFault_Handler + + + END diff --git a/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s b/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s new file mode 100644 index 00000000..6a462980 --- /dev/null +++ b/ports_module/cortex_m23/iar/example_build/txm_module_preamble.s @@ -0,0 +1,69 @@ + SECTION .text:CODE + + AAPCS INTERWORK, ROPI, RWPI_COMPATIBLE, VFP_COMPATIBLE + PRESERVE8 + + /* Define public symbols. */ + + PUBLIC __txm_module_preamble + + + /* Define application-specific start/stop entry points for the module. */ + + EXTERN demo_module_start + + + /* Define common external refrences. */ + + EXTERN _txm_module_thread_shell_entry + EXTERN _txm_module_callback_request_thread_entry + EXTERN ROPI$$Length + EXTERN RWPI$$Length + + DATA +__txm_module_preamble: + DC32 0x4D4F4455 // Module ID + DC32 0x6 // Module Major Version + DC32 0x1 // Module Minor Version + DC32 32 // Module Preamble Size in 32-bit words + DC32 0x12345678 // Module ID (application defined) + DC32 0x00000007 // Module Properties where: + // Bits 31-24: Compiler ID + // 0 -> IAR + // 1 -> ARM + // 2 -> GNU + // Bits 23-3: Reserved + // Bit 2: 0 -> Disable shared/external memory access + // 1 -> Enable shared/external memory access + // Bit 1: 0 -> No MPU protection + // 1 -> MPU protection (must have user mode selected - bit 0 set) + // Bit 0: 0 -> Privileged mode execution + // 1 -> User mode execution + DC32 _txm_module_thread_shell_entry - . - 0 // Module Shell Entry Point + DC32 demo_module_start - . - 0 // Module Start Thread Entry Point + DC32 0 // Module Stop Thread Entry Point + DC32 1 // Module Start/Stop Thread Priority + DC32 1024 // Module Start/Stop Thread Stack Size + DC32 _txm_module_callback_request_thread_entry - . - 0 // Module Callback Thread Entry + DC32 1 // Module Callback Thread Priority + DC32 1024 // Module Callback Thread Stack Size + DC32 ROPI$$Length // Module Code Size + DC32 RWPI$$Length // Module Data Size + DC32 0 // Reserved 0 + DC32 0 // Reserved 1 + DC32 0 // Reserved 2 + DC32 0 // Reserved 3 + DC32 0 // Reserved 4 + DC32 0 // Reserved 5 + DC32 0 // Reserved 6 + DC32 0 // Reserved 7 + DC32 0 // Reserved 8 + DC32 0 // Reserved 9 + DC32 0 // Reserved 10 + DC32 0 // Reserved 11 + DC32 0 // Reserved 12 + DC32 0 // Reserved 13 + DC32 0 // Reserved 14 + DC32 0 // Reserved 15 + + END diff --git a/ports_module/cortex_m23/iar/inc/tx_port.h b/ports_module/cortex_m23/iar/inc/tx_port.h new file mode 100644 index 00000000..71c81e2c --- /dev/null +++ b/ports_module/cortex_m23/iar/inc/tx_port.h @@ -0,0 +1,708 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* tx_port.h ARMv8-M */ +/* 6.1.6 */ +/* */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the ThreadX */ +/* real-time kernel function identically on a variety of different */ +/* processor architectures. For example, the size or number of bits */ +/* in an "int" data type vary between microprocessor architectures and */ +/* even C compilers for the same microprocessor. ThreadX does not */ +/* directly use native C data types. Instead, ThreadX creates its */ +/* own special types that can be mapped to actual data types by this */ +/* file to guarantee consistency in the interface and functionality. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TX_PORT_H +#define TX_PORT_H + + +/* Determine if the optional ThreadX user define file should be used. */ + +#ifdef TX_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in tx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "tx_user.h" +#endif + + +/* Define compiler library include files. */ + +#include +#include + +#ifdef __ICCARM__ +#include /* IAR Intrinsics */ +#define __asm__ __asm /* Define to make all inline asm look similar */ +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +#include +#endif +#endif /* __ICCARM__ */ + + +/* Define ThreadX basic types for this port. */ + +#define VOID void +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef unsigned long long ULONG64; +typedef short SHORT; +typedef unsigned short USHORT; +#define ULONG64_DEFINED + +/* Function prototypes for this port. */ +struct TX_THREAD_STRUCT; +UINT _txe_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *thread_ptr, ULONG stack_size); +UINT _txe_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); +UINT _tx_thread_secure_stack_allocate(struct TX_THREAD_STRUCT *tx_thread, ULONG stack_size); +UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *tx_thread); + +/* This hardware has stack checking that we take advantage of - do NOT define. */ +#ifdef TX_ENABLE_STACK_CHECKING + #error "Do not define TX_ENABLE_STACK_CHECKING" +#endif + +/* If user does not want to terminate thread on stack overflow, + #define the TX_THREAD_NO_TERMINATE_STACK_ERROR symbol. + The thread will be rescheduled and continue to cause the exception. + It is suggested user code handle this by registering a notification with the + tx_thread_stack_error_notify function. */ +/*#define TX_THREAD_NO_TERMINATE_STACK_ERROR */ + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef TX_SOURCE_CODE + + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef TX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define tx_thread_secure_stack_allocate _tx_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _tx_thread_secure_stack_free + +#else + +/* Services with error checking. */ + +#define tx_thread_secure_stack_allocate _txe_thread_secure_stack_allocate +#define tx_thread_secure_stack_free _txe_thread_secure_stack_free + +#endif +#endif + + + +/* Define the priority levels for ThreadX. Legal values range + from 32 to 1024 and MUST be evenly divisible by 32. */ + +#ifndef TX_MAX_PRIORITIES +#define TX_MAX_PRIORITIES 32 +#endif + + +/* Define the minimum stack for a ThreadX thread on this processor. If the size supplied during + thread creation is less than this value, the thread create call will return an error. */ + +#ifndef TX_MINIMUM_STACK +#define TX_MINIMUM_STACK 200 /* Minimum stack size for this port */ +#endif + + +/* Define the system timer thread's default stack size and priority. These are only applicable + if TX_TIMER_PROCESS_IN_ISR is not defined. */ + +#ifndef TX_TIMER_THREAD_STACK_SIZE +#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */ +#endif + +#ifndef TX_TIMER_THREAD_PRIORITY +#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */ +#endif + + +/* Define various constants for the ThreadX Cortex-M port. */ + +#define TX_INT_DISABLE 1 /* Disable interrupts */ +#define TX_INT_ENABLE 0 /* Enable interrupts */ + + +/* Define the clock source for trace event entry time stamp. The following two item are port specific. + For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock + source constants would be: + +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024) +#define TX_TRACE_TIME_MASK 0x0000FFFFUL + +*/ + +#ifndef TX_MISRA_ENABLE +#ifndef TX_TRACE_TIME_SOURCE +#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) +#endif +#else +ULONG _tx_misra_time_stamp_get(VOID); +#define TX_TRACE_TIME_SOURCE _tx_misra_time_stamp_get() +#endif + +#ifndef TX_TRACE_TIME_MASK +#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL +#endif + + +/* Define the port specific options for the _tx_build_options variable. This variable indicates + how the ThreadX library was built. */ + +#define TX_PORT_SPECIFIC_BUILD_OPTIONS (0) + + +/* Define the in-line initialization constant so that modules with in-line + initialization capabilities can prevent their initialization from being + a function call. */ + +#ifdef TX_MISRA_ENABLE +#define TX_DISABLE_INLINE +#else +#define TX_INLINE_INITIALIZATION +#endif + + +/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is + disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack + checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING + define is negated, thereby forcing the stack fill which is necessary for the stack checking + logic. */ + +#ifndef TX_MISRA_ENABLE +#ifdef TX_ENABLE_STACK_CHECKING +#undef TX_DISABLE_STACK_FILLING +#endif +#endif + + +/* Define the TX_THREAD control block extensions for this port. The main reason + for the multiple macros is so that backward compatibility can be maintained with + existing ThreadX kernel awareness modules. */ + +#define TX_THREAD_EXTENSION_0 +#define TX_THREAD_EXTENSION_1 +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +/* IAR library support */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* ThreadX in non-secure zone with calls to secure zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_secure_stack_context; \ + VOID *tx_thread_iar_tls_pointer; +#else +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; +#endif + +#else +/* No IAR library support */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* ThreadX in non-secure zone with calls to secure zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_secure_stack_context; +#else +/* ThreadX in only one zone. */ +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; +#endif + +#endif +#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY +#define TX_THREAD_EXTENSION_3 +#else +#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \ + unsigned long long tx_thread_execution_time_last_start; +#endif + + +/* Define the port extensions of the remaining ThreadX objects. */ + +#define TX_BLOCK_POOL_EXTENSION +#define TX_BYTE_POOL_EXTENSION +#define TX_MUTEX_EXTENSION +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); + + +/* Define the user extension field of the thread control block. Nothing + additional is needed for this port so it is defined as white space. */ + +#ifndef TX_THREAD_USER_EXTENSION +#define TX_THREAD_USER_EXTENSION +#endif + + +/* Define the macros for processing extensions in tx_thread_create, tx_thread_delete, + tx_thread_shell_entry, and tx_thread_terminate. */ + + +#ifdef TX_ENABLE_IAR_LIBRARY_SUPPORT +void *_tx_iar_create_per_thread_tls_area(void); +void _tx_iar_destroy_per_thread_tls_area(void *tls_ptr); +void __iar_Initlocks(void); + +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) thread_ptr -> tx_thread_iar_tls_pointer = _tx_iar_create_per_thread_tls_area(); + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); \ + if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) do {_tx_iar_destroy_per_thread_tls_area(thread_ptr -> tx_thread_iar_tls_pointer); \ + thread_ptr -> tx_thread_iar_tls_pointer = TX_NULL; } while(0); +#endif +#define TX_PORT_SPECIFIC_PRE_SCHEDULER_INITIALIZATION do {__iar_Initlocks();} while(0); +#else /* No IAR library support. */ +#define TX_THREAD_CREATE_EXTENSION(thread_ptr) +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) if(thread_ptr -> tx_thread_secure_stack_context){_tx_thread_secure_stack_free(thread_ptr);} +#else +#define TX_THREAD_DELETE_EXTENSION(thread_ptr) +#endif +#endif /* TX_ENABLE_IAR_LIBRARY_SUPPORT */ + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Define the size of the secure stack for the timer thread and use the extension to allocate the secure stack. */ +#define TX_TIMER_THREAD_SECURE_STACK_SIZE 256 +#define TX_TIMER_INITIALIZE_EXTENSION(status) _tx_thread_secure_stack_allocate(&_tx_timer_thread, TX_TIMER_THREAD_SECURE_STACK_SIZE); +#endif + +#if defined(__ARMVFP__) || defined(__ARM_PCS_VFP) || defined(__TARGET_FPU_VFP) + +#ifdef TX_MISRA_ENABLE + +ULONG _tx_misra_control_get(void); +void _tx_misra_control_set(ULONG value); +ULONG _tx_misra_fpccr_get(void); +void _tx_misra_vfp_touch(void); + +#else /* TX_MISRA_ENABLE not defined */ + +/* Define some helper functions (these are intrinsics in some compilers). */ +#ifdef __GNUC__ +__attribute__( ( always_inline ) ) static inline ULONG __get_CONTROL(void) +{ +ULONG control_value; + + __asm__ volatile (" MRS %0,CONTROL ": "=r" (control_value) ); + return(control_value); +} + +__attribute__( ( always_inline ) ) static inline void __set_CONTROL(ULONG control_value) +{ + __asm__ volatile (" MSR CONTROL,%0": : "r" (control_value): "memory" ); +} + +#define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0"); + +#endif /* __GNUC__ */ + +#ifdef __ICCARM__ +#define TX_VFP_TOUCH() __asm__ volatile ("VMOV.F32 s0, s0"); +#endif /* __ICCARM__ */ + +#endif /* TX_MISRA_ENABLE */ + + +/* A completed thread falls into _thread_shell_entry and we can simply deactivate the FPU via CONTROL.FPCA + in order to ensure no lazy stacking will occur. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } +#else + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } + +#endif + +/* A thread can be terminated by another thread, so we first check if it's self-terminating and not in an ISR. + If so, deactivate the FPU via CONTROL.FPCA. Otherwise we are in an interrupt or another thread is terminating + this one, so if the FPCCR.LSPACT bit is set, we need to save the CONTROL.FPCA state, touch the FPU to flush + the lazy FPU save, then restore the CONTROL.FPCA state. */ + +#ifndef TX_MISRA_ENABLE + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = *((ULONG *) 0xE000EF34); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + TX_VFP_TOUCH(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = __get_CONTROL(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + __set_CONTROL(_tx_vfp_state); \ + } \ + } \ + } \ + } +#else + +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) { \ + ULONG _tx_system_state; \ + _tx_system_state = TX_THREAD_GET_SYSTEM_STATE(); \ + if ((_tx_system_state == ((ULONG) 0)) && ((thread_ptr) == _tx_thread_current_ptr)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + else \ + { \ + ULONG _tx_fpccr; \ + _tx_fpccr = _tx_misra_fpccr_get(); \ + _tx_fpccr = _tx_fpccr & ((ULONG) 0x01); \ + if (_tx_fpccr == ((ULONG) 0x01)) \ + { \ + ULONG _tx_vfp_state; \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ((ULONG) 0x4); \ + _tx_misra_vfp_touch(); \ + if (_tx_vfp_state == ((ULONG) 0)) \ + { \ + _tx_vfp_state = _tx_misra_control_get(); \ + _tx_vfp_state = _tx_vfp_state & ~((ULONG) 0x4); \ + _tx_misra_control_set(_tx_vfp_state); \ + } \ + } \ + } \ + } +#endif + +#else /* No VFP in use */ + +#define TX_THREAD_COMPLETED_EXTENSION(thread_ptr) +#define TX_THREAD_TERMINATED_EXTENSION(thread_ptr) + +#endif /* defined(__ARMVFP__) || defined(__ARM_PCS_VFP) || defined(__TARGET_FPU_VFP) */ + + +/* Define the ThreadX object creation extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_CREATE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_CREATE_EXTENSION(group_ptr) +#define TX_MUTEX_CREATE_EXTENSION(mutex_ptr) +#define TX_QUEUE_CREATE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_CREATE_EXTENSION(semaphore_ptr) +#define TX_TIMER_CREATE_EXTENSION(timer_ptr) + + +/* Define the ThreadX object deletion extensions for the remaining objects. */ + +#define TX_BLOCK_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_BYTE_POOL_DELETE_EXTENSION(pool_ptr) +#define TX_EVENT_FLAGS_GROUP_DELETE_EXTENSION(group_ptr) +#define TX_MUTEX_DELETE_EXTENSION(mutex_ptr) +#define TX_QUEUE_DELETE_EXTENSION(queue_ptr) +#define TX_SEMAPHORE_DELETE_EXTENSION(semaphore_ptr) +#define TX_TIMER_DELETE_EXTENSION(timer_ptr) + + +/* Define the get system state macro. */ + +#ifndef TX_THREAD_GET_SYSTEM_STATE +#ifndef TX_MISRA_ENABLE + +#ifdef __GNUC__ /* GCC and ARM Compiler 6 */ + +__attribute__( ( always_inline ) ) static inline unsigned int __get_IPSR(void) +{ +unsigned int ipsr_value; + __asm__ volatile (" MRS %0,IPSR ": "=r" (ipsr_value) ); + return(ipsr_value); +} + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) + +#elif defined(__ICCARM__) /* IAR */ + +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __get_IPSR()) + +#endif /* TX_THREAD_GET_SYSTEM_STATE for different compilers */ + +#else /* TX_MISRA_ENABLE is defined, use MISRA function. */ +ULONG _tx_misra_ipsr_get(VOID); +#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | _tx_misra_ipsr_get()) +#endif /* TX_MISRA_ENABLE */ +#endif /* TX_THREAD_GET_SYSTEM_STATE */ + + +/* Define the check for whether or not to call the _tx_thread_system_return function. A non-zero value + indicates that _tx_thread_system_return should not be called. This overrides the definition in tx_thread.h + for Cortex-M since so we don't waste time checking the _tx_thread_system_state variable that is always + zero after initialization for Cortex-M ports. */ + +#ifndef TX_THREAD_SYSTEM_RETURN_CHECK +#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable); +#endif + +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) +/* Initialize secure stacks for threads calling secure functions. */ +extern void _tx_thread_secure_stack_initialize(void); +#define TX_INITIALIZE_KERNEL_ENTER_EXTENSION _tx_thread_secure_stack_initialize(); +#endif + +/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to + prevent early scheduling on Cortex-M parts. */ + +#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++; + + + + +#ifndef TX_DISABLE_INLINE + +/* Define the TX_LOWEST_SET_BIT_CALCULATE macro for each compiler. */ +#ifdef __ICCARM__ /* IAR Compiler */ +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) (b) = (UINT) __CLZ(__RBIT((m))); +#elif defined(__GNUC__) /* GCC and AC6 Compiler */ +#define TX_LOWEST_SET_BIT_CALCULATE(m, b) __asm__ volatile (" RBIT %0,%1 ": "=r" (m) : "r" (m) ); \ + __asm__ volatile (" CLZ %0,%1 ": "=r" (b) : "r" (m) ); +#endif + +/* Define the interrupt disable/restore macros for each compiler. */ + +#ifdef __GNUC__ /* GCC and AC6 */ + +__attribute__( ( always_inline ) ) static inline unsigned int __disable_interrupt(void) +{ +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + __asm__ volatile (" CPSID i" : : : "memory" ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __restore_interrupt(unsigned int primask_value) +{ + __asm__ volatile (" MSR PRIMASK,%0": : "r" (primask_value): "memory" ); +} + +__attribute__( ( always_inline ) ) static inline unsigned int __get_primask_value(void) +{ +unsigned int primask_value; + + __asm__ volatile (" MRS %0,PRIMASK ": "=r" (primask_value) ); + return(primask_value); +} + +__attribute__( ( always_inline ) ) static inline void __enable_interrupt(void) +{ + __asm__ volatile (" CPSIE i": : : "memory" ); +} + + +__attribute__( ( always_inline ) ) static inline void _tx_thread_system_return_inline(void) +{ +unsigned int interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_primask_value(); + __enable_interrupt(); + __restore_interrupt(interrupt_save); + } +} + + +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; +#define TX_DISABLE interrupt_save = __disable_interrupt(); +#define TX_RESTORE __restore_interrupt(interrupt_save); + +#elif defined(__ICCARM__) /* IAR */ + +static void _tx_thread_system_return_inline(void) +{ +__istate_t interrupt_save; + + /* Set PendSV to invoke ThreadX scheduler. */ + *((ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); + if (__get_IPSR() == 0) + { + interrupt_save = __get_interrupt_state(); + __enable_interrupt(); + __set_interrupt_state(interrupt_save); + } +} + +#define TX_INTERRUPT_SAVE_AREA __istate_t interrupt_save; +#define TX_DISABLE {interrupt_save = __get_interrupt_state();__disable_interrupt();}; +#define TX_RESTORE {__set_interrupt_state(interrupt_save);}; + +#endif /* Interrupt disable/restore macros for each compiler. */ + +/* Redefine _tx_thread_system_return for improved performance. */ + +#define _tx_thread_system_return _tx_thread_system_return_inline + + +#else /* TX_DISABLE_INLINE is defined */ + +UINT _tx_thread_interrupt_disable(VOID); +VOID _tx_thread_interrupt_restore(UINT previous_posture); + +#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save; + +#define TX_DISABLE interrupt_save = _tx_thread_interrupt_disable(); +#define TX_RESTORE _tx_thread_interrupt_restore(interrupt_save); +#endif /* TX_DISABLE_INLINE */ + + +/* Define the version ID of ThreadX. This may be utilized by the application. */ + +#ifdef TX_THREAD_INIT +CHAR _tx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Modules ARMv8-M Version 6.1.6 *"; +#else +#ifdef TX_MISRA_ENABLE +extern CHAR _tx_version_id[100]; +#else +extern CHAR _tx_version_id[]; +#endif +#endif + + +#endif diff --git a/ports_module/cortex_m23/iar/inc/tx_secure_interface.h b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h new file mode 100644 index 00000000..c2779f40 --- /dev/null +++ b/ports_module/cortex_m23/iar/inc/tx_secure_interface.h @@ -0,0 +1,60 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* tx_secure_interface.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the ThreadX secure thread stack components, */ +/* including data types and external references. */ +/* It is assumed that tx_api.h and tx_port.h have already been */ +/* included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef TX_SECURE_INTERFACE_H +#define TX_SECURE_INTERFACE_H + +/* Define internal secure thread stack function prototypes. */ + +extern void _tx_thread_secure_stack_initialize(void); +extern UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size); +extern UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr); +extern void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr); + +#endif diff --git a/ports_module/cortex_m23/iar/inc/txm_module_port.h b/ports_module/cortex_m23/iar/inc/txm_module_port.h new file mode 100644 index 00000000..2b1729af --- /dev/null +++ b/ports_module/cortex_m23/iar/inc/txm_module_port.h @@ -0,0 +1,355 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* txm_module_port.h Cortex-M23/IAR */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic module constants, interface structures, */ +/* and function prototypes. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ + +#ifndef TXM_MODULE_PORT_H +#define TXM_MODULE_PORT_H + +/* Determine if the optional Modules user define file should be used. */ + +#ifdef TXM_MODULE_INCLUDE_USER_DEFINE_FILE + +/* Yes, include the user defines in txm_module_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "txm_module_user.h" +#endif + +/* It is assumed that the base ThreadX tx_port.h file has been modified to add the + following extensions to the ThreadX thread control block (this code should replace + the corresponding macro define in tx_port.h): + +#define TX_THREAD_EXTENSION_2 VOID *tx_thread_module_instance_ptr; \ + VOID *tx_thread_module_entry_info_ptr; \ + ULONG tx_thread_module_current_user_mode; \ + ULONG tx_thread_module_user_mode; \ + ULONG tx_thread_module_saved_lr; \ + VOID *tx_thread_module_kernel_stack_start; \ + VOID *tx_thread_module_kernel_stack_end; \ + ULONG tx_thread_module_kernel_stack_size; \ + VOID *tx_thread_module_stack_ptr; \ + VOID *tx_thread_module_stack_start; \ + VOID *tx_thread_module_stack_end; \ + ULONG tx_thread_module_stack_size; \ + VOID *tx_thread_module_reserved; \ + VOID *tx_thread_iar_tls_pointer; + +The following extensions must also be defined in tx_port.h: + +#define TX_EVENT_FLAGS_GROUP_EXTENSION VOID *tx_event_flags_group_module_instance; \ + VOID (*tx_event_flags_group_set_module_notify)(struct TX_EVENT_FLAGS_GROUP_STRUCT *group_ptr); + +#define TX_QUEUE_EXTENSION VOID *tx_queue_module_instance; \ + VOID (*tx_queue_send_module_notify)(struct TX_QUEUE_STRUCT *queue_ptr); + +#define TX_SEMAPHORE_EXTENSION VOID *tx_semaphore_module_instance; \ + VOID (*tx_semaphore_put_module_notify)(struct TX_SEMAPHORE_STRUCT *semaphore_ptr); + +#define TX_TIMER_EXTENSION VOID *tx_timer_module_instance; \ + VOID (*tx_timer_module_expiration_function)(ULONG id); +*/ + +/* Define the kernel stack size for a module thread. */ +#ifndef TXM_MODULE_KERNEL_STACK_SIZE +#define TXM_MODULE_KERNEL_STACK_SIZE 768 +#endif + +/* Define constants specific to the tools the module can be built with for this particular modules port. */ + +#define TXM_MODULE_IAR_COMPILER 0x00000000 +#define TXM_MODULE_RVDS_COMPILER 0x01000000 +#define TXM_MODULE_GNU_COMPILER 0x02000000 +#define TXM_MODULE_COMPILER_MASK 0xFF000000 +#define TXM_MODULE_OPTIONS_MASK 0x000000FF + + +/* Define the properties for this particular module port. */ + +#define TXM_MODULE_PORT_DISPATCH + +#define TXM_MODULE_MEMORY_PROTECTION_ENABLED + +#ifdef TXM_MODULE_MEMORY_PROTECTION_ENABLED +#define TXM_MODULE_REQUIRE_ALLOCATED_OBJECT_MEMORY +#else +#define TXM_MODULE_REQUIRE_LOCAL_OBJECT_MEMORY +#endif + +#define TXM_MODULE_USER_MODE 0x00000001 +#define TXM_MODULE_MEMORY_PROTECTION 0x00000002 +#define TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS 0x00000004 + + +/* Define the supported options for this module. */ + +#define TXM_MODULE_MANAGER_SUPPORTED_OPTIONS (TXM_MODULE_USER_MODE | TXM_MODULE_MEMORY_PROTECTION | TXM_MODULE_SHARED_EXTERNAL_MEMORY_ACCESS) +#define TXM_MODULE_MANAGER_REQUIRED_OPTIONS 0 + + +/* Define offset adjustments according to the compiler used to build the module. */ + +#define TXM_MODULE_IAR_SHELL_ADJUST 24 +#define TXM_MODULE_IAR_START_ADJUST 28 +#define TXM_MODULE_IAR_STOP_ADJUST 32 +#define TXM_MODULE_IAR_CALLBACK_ADJUST 44 + +#define TXM_MODULE_RVDS_SHELL_ADJUST 0 +#define TXM_MODULE_RVDS_START_ADJUST 0 +#define TXM_MODULE_RVDS_STOP_ADJUST 0 +#define TXM_MODULE_RVDS_CALLBACK_ADJUST 0 + +#define TXM_MODULE_GNU_SHELL_ADJUST 24 +#define TXM_MODULE_GNU_START_ADJUST 28 +#define TXM_MODULE_GNU_STOP_ADJUST 32 +#define TXM_MODULE_GNU_CALLBACK_ADJUST 44 + + +/* Define other module port-specific constants. */ + +/* Define INLINE_DECLARE to inline for ARM compiler. */ + +#define INLINE_DECLARE inline + +/* Define the number of MPU entries assigned to the code and data sections. + On Cortex-M23 devices, there are 8 total entries. ThreadX uses one for access + to the kernel entry function, one for module code protection, one for module data protection, + leaving five regions available for shared memory. */ +#define TXM_MODULE_MPU_TOTAL_ENTRIES 8 +#define TXM_MODULE_MPU_KERNEL_ENTRY_INDEX 0 +#define TXM_MODULE_MPU_CODE_INDEX 1 +#define TXM_MODULE_MPU_DATA_INDEX 2 + +#define TXM_MODULE_MPU_SHARED_INDEX 3 +#define TXM_MODULE_MPU_SHARED_ENTRIES 5 + +#define TXM_MODULE_ATTRIBUTE_NON_SHAREABLE 0x00 +#define TXM_MODULE_ATTRIBUTE_OUTER_SHAREABLE 0x10 +#define TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE 0x18 +#define TXM_MODULE_ATTRIBUTE_READ_WRITE 0x02 +#define TXM_MODULE_ATTRIBUTE_READ_ONLY 0x06 +#define TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER 0x01 +#define TXM_MODULE_ATTRIBUTE_REGION_ENABLE 0x01 +#define TXM_MODULE_ATTRIBUTE_MASK 0x1E +#define TXM_MODULE_ATTRIBUTE_INDEX 0x00 + +/* MAIR_ATTR settings +Device-nGnRE : 0b [Outer]0000 [Inner]0100 +Code WT RA : 0b [Outer]1010 [Inner]1010 +DATA WBWA RA : 0b [Outer]1111 [Inner]1111 +*/ + +/* Data aligned to 8 bytes (stacks must be 8-byte aligned). */ +#define TXM_MODULE_DATA_ALIGNMENT 8 + +/* MPU regions must be 32-byte aligned. */ +#define TXM_MODULE_MPU_ALIGNMENT 32 + +#define TXM_THREAD_SECURE_STACK_ALLOCATE_CALL TXM_MODULE_PORT_EXTENSION_API_ID_START +#define TXM_THREAD_SECURE_STACK_FREE_CALL (TXM_MODULE_PORT_EXTENSION_API_ID_START+1) + +/* There are 2 registers to set up each MPU region: MPU_RBAR, MPU_RLAR. */ +typedef struct TXM_MODULE_MPU_INFO_STRUCT +{ + ULONG txm_module_mpu_region_base_address; + ULONG txm_module_mpu_region_limit_address; +} TXM_MODULE_MPU_INFO; + +/* Define the port-extensions to the module manager instance structure. */ +#define TXM_MODULE_MANAGER_PORT_EXTENSION \ + TXM_MODULE_MPU_INFO txm_module_instance_mpu_registers[TXM_MODULE_MPU_TOTAL_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_count; \ + ULONG txm_module_instance_shared_memory_address[TXM_MODULE_MPU_SHARED_ENTRIES]; \ + ULONG txm_module_instance_shared_memory_length[TXM_MODULE_MPU_SHARED_ENTRIES]; + + +/* Define the memory fault information structure that is populated when a memory fault occurs. */ + +typedef struct TXM_MODULE_MANAGER_MEMORY_FAULT_INFO_STRUCT +{ + TX_THREAD *txm_module_manager_memory_fault_info_thread_ptr; + VOID *txm_module_manager_memory_fault_info_code_location; + ULONG txm_module_manager_memory_fault_info_shcsr; + ULONG txm_module_manager_memory_fault_info_cfsr; + ULONG txm_module_manager_memory_fault_info_mmfar; + ULONG txm_module_manager_memory_fault_info_bfar; + ULONG txm_module_manager_memory_fault_info_control; + ULONG txm_module_manager_memory_fault_info_sp; + ULONG txm_module_manager_memory_fault_info_r0; + ULONG txm_module_manager_memory_fault_info_r1; + ULONG txm_module_manager_memory_fault_info_r2; + ULONG txm_module_manager_memory_fault_info_r3; + ULONG txm_module_manager_memory_fault_info_r4; + ULONG txm_module_manager_memory_fault_info_r5; + ULONG txm_module_manager_memory_fault_info_r6; + ULONG txm_module_manager_memory_fault_info_r7; + ULONG txm_module_manager_memory_fault_info_r8; + ULONG txm_module_manager_memory_fault_info_r9; + ULONG txm_module_manager_memory_fault_info_r10; + ULONG txm_module_manager_memory_fault_info_r11; + ULONG txm_module_manager_memory_fault_info_r12; + ULONG txm_module_manager_memory_fault_info_lr; + ULONG txm_module_manager_memory_fault_info_xpsr; +} TXM_MODULE_MANAGER_MEMORY_FAULT_INFO; + + +#define TXM_MODULE_MANAGER_FAULT_INFO \ + TXM_MODULE_MANAGER_MEMORY_FAULT_INFO _txm_module_manager_memory_fault_info; + + +/* Define the macro to check the code alignment. */ + +#define TXM_MODULE_MANAGER_CHECK_CODE_ALIGNMENT(module_location, code_alignment) \ + { \ + ULONG temp; \ + temp = (ULONG) module_location; \ + temp = temp & (code_alignment - 1); \ + if (temp) \ + { \ + _tx_mutex_put(&_txm_module_manager_mutex); \ + return(TXM_MODULE_ALIGNMENT_ERROR); \ + } \ + } + + +/* Define the macro to adjust the alignment and size for code/data areas. */ + +#define TXM_MODULE_MANAGER_ALIGNMENT_ADJUST(module_preamble, code_size, code_alignment, data_size, data_alignment) _txm_module_manager_alignment_adjust(module_preamble, &code_size, &code_alignment, &data_size, &data_alignment); + + +/* Define the macro to adjust the symbols in the module preamble. */ + +#define TXM_MODULE_MANAGER_CALCULATE_ADJUSTMENTS(properties, shell_function_adjust, start_function_adjust, stop_function_adjust, callback_function_adjust) \ + if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_IAR_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_IAR_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_IAR_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_IAR_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_IAR_CALLBACK_ADJUST; \ + } \ + else if ((properties & TXM_MODULE_COMPILER_MASK) == TXM_MODULE_RVDS_COMPILER) \ + { \ + shell_function_adjust = TXM_MODULE_RVDS_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_RVDS_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_RVDS_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_RVDS_CALLBACK_ADJUST; \ + } \ + else \ + { \ + shell_function_adjust = TXM_MODULE_GNU_SHELL_ADJUST; \ + start_function_adjust = TXM_MODULE_GNU_START_ADJUST; \ + stop_function_adjust = TXM_MODULE_GNU_STOP_ADJUST; \ + callback_function_adjust = TXM_MODULE_GNU_CALLBACK_ADJUST; \ + } + + +/* Define the macro to populate the thread control block with module port-specific information. + Check if the module is in user mode and set up txm_module_thread_entry_info_kernel_call_dispatcher accordingly. +*/ + +#define TXM_MODULE_MANAGER_THREAD_SETUP(thread_ptr, module_instance) \ + thread_ptr -> tx_thread_module_current_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + thread_ptr -> tx_thread_module_user_mode = module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE; \ + if (thread_ptr -> tx_thread_module_user_mode) \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_user_mode_entry; \ + } \ + else \ + { \ + thread_entry_info -> txm_module_thread_entry_info_kernel_call_dispatcher = _txm_module_manager_kernel_dispatch; \ + } + + +/* Define the macro to populate the module control block with module port-specific information. + If memory protection is enabled, set up the MPU registers. +*/ +#define TXM_MODULE_MANAGER_MODULE_SETUP(module_instance) \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_USER_MODE) \ + { \ + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) \ + { \ + _txm_module_manager_mm_register_setup(module_instance); \ + } \ + } \ + else \ + { \ + /* Do nothing. */ \ + } + +/* Define the macro to perform port-specific functions when unloading the module. */ +/* Nothing needs to be done for this port. */ +#define TXM_MODULE_MANAGER_MODULE_UNLOAD(module_instance) + + +/* Define the macros to perform port-specific checks when passing pointers to the kernel. */ + +/* Define macro to make sure object is inside the module's data. */ +#define TXM_MODULE_MANAGER_CHECK_INSIDE_DATA(module_instance, obj_ptr, obj_size) \ + _txm_module_manager_inside_data_check(module_instance, obj_ptr, obj_size) + +/* Define some internal prototypes to this module port. */ + +#ifndef TX_SOURCE_CODE +#define txm_module_manager_memory_fault_notify _txm_module_manager_memory_fault_notify +#endif + + +#ifdef TX_SOURCE_CODE + +#endif + +#define TXM_MODULE_MANAGER_ADDITIONAL_PROTOTYPES \ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, ULONG *code_size, ULONG *code_alignment, ULONG *data_size, ULONG *data_alignment); \ +VOID _txm_module_manager_memory_fault_handler(VOID); \ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)); \ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance); \ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size); \ +ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2); + + +#define TXM_MODULE_MANAGER_VERSION_ID \ +CHAR _txm_module_manager_version_id[] = \ + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Module Cortex-M23/IAR Version 6.1.6 *"; + +#endif diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c b/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c new file mode 100644 index 00000000..1df73db5 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_module_thread_shell_entry.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#ifndef TXM_MODULE +#define TXM_MODULE +#endif + +#ifndef TX_SOURCE_CODE +#define TX_SOURCE_CODE +#endif + + +/* Include necessary system files. */ + +#include "txm_module.h" +#include "tx_thread.h" + +/* Define the global module entry pointer from the start thread of the module. */ + +TXM_MODULE_THREAD_ENTRY_INFO *_txm_module_entry_info; + + +/* Define the dispatch function pointer used in the module implementation. */ + +ULONG (*_txm_module_kernel_call_dispatcher)(ULONG kernel_request, ULONG param_1, ULONG param_2, ULONG param3); + + +/* Define the IAR startup code that clears the uninitialized global data and sets up the + preset global variables. */ + +extern VOID __iar_data_init3(VOID); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_thread_shell_entry Cortex-M23/IAR */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calls the specified entry function of the thread. It */ +/* also provides a place for the thread's entry function to return. */ +/* If the thread returns, this function places the thread in a */ +/* "COMPLETED" state. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to current thread */ +/* thread_info Pointer to thread entry info */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __iar_data_init3 IAR global initialization */ +/* thread_entry Thread's entry function */ +/* tx_thread_resume Resume the module callback thread */ +/* _txm_module_thread_system_suspend Module thread suspension routine */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_thread_shell_entry(TX_THREAD *thread_ptr, TXM_MODULE_THREAD_ENTRY_INFO *thread_info) +{ + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + VOID (*entry_exit_notify)(TX_THREAD *, UINT); +#endif + + + /* Determine if this is the start thread. If so, we must prepare the module for + execution. If not, simply skip the C startup code. */ + if (thread_info -> txm_module_thread_entry_info_start_thread) + { + /* Initialize the IAR C environment. */ + __iar_data_init3(); + + /* Save the entry info pointer, for later use. */ + _txm_module_entry_info = thread_info; + + /* Save the kernel function dispatch address. This is used to make all resident calls from + the module. */ + _txm_module_kernel_call_dispatcher = thread_info -> txm_module_thread_entry_info_kernel_call_dispatcher; + + /* Ensure that we have a valid pointer. */ + while (!_txm_module_kernel_call_dispatcher) + { + /* Loop here, if an error is present getting the dispatch function pointer! + An error here typically indicates the resident portion of _tx_thread_schedule + is not supporting the trap to obtain the function pointer. */ + } + + /* Resume the module's callback thread, already created in the manager. */ + _txe_thread_resume(thread_info -> txm_module_thread_entry_info_callback_request_thread); + } + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has been entered! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_ENTRY); + } +#endif + + /* Call current thread's entry function. */ + (thread_info -> txm_module_thread_entry_info_entry) (thread_info -> txm_module_thread_entry_info_parameter); + + /* Suspend thread with a "completed" state. */ + + +#ifndef TX_DISABLE_NOTIFY_CALLBACKS + + /* Pickup the entry/exit application callback routine again. */ + entry_exit_notify = thread_info -> txm_module_thread_entry_info_exit_notify; + + /* Determine if an application callback routine is specified. */ + if (entry_exit_notify != TX_NULL) + { + + /* Yes, notify application that this thread has exited! */ + (entry_exit_notify)(thread_ptr, TX_THREAD_EXIT); + } +#endif + + /* Call actual thread suspension routine. */ + _txm_module_thread_system_suspend(thread_ptr); + +#ifdef TX_SAFETY_CRITICAL + + /* If we ever get here, raise safety critical exception. */ + TX_SAFETY_CRITICAL_EXCEPTION(__FILE__, __LINE__, 0); +#endif +} + diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c new file mode 100644 index 00000000..7a4bdf38 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_allocate.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocate a secure stack for the thread. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of this function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_ALLOCATE_CALL, (ALIGN_TYPE) thread_ptr, (ALIGN_TYPE) stack_size, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c new file mode 100644 index 00000000..83e923fc --- /dev/null +++ b/ports_module/cortex_m23/iar/module_lib/src/txm_thread_secure_stack_free.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TXM_MODULE +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees the thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _txm_module_kernel_call_dispatcher */ +/* */ +/* CALLED BY */ +/* */ +/* Module application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ + +UINT return_value; + + /* Call module manager dispatcher. */ + return_value = (UINT) (_txm_module_kernel_call_dispatcher)(TXM_THREAD_SECURE_STACK_FREE_CALL, (ALIGN_TYPE) thread_ptr, 0, 0); + + /* Return value to the caller. */ + return(return_value); +} diff --git a/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h b/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h new file mode 100644 index 00000000..e612b45c --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/inc/txm_module_manager_dispatch_port.h @@ -0,0 +1,65 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Define port-specific dispatch functions. */ + +/* UINT _txe_thread_secure_stack_allocate( + TX_THREAD *thread_ptr, -> param_0 + ULONG stack_size -> param_1 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_allocate_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0, ALIGN_TYPE param_1) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate( + (TX_THREAD *) param_0, + (ULONG) param_1 + ); + return(return_value); +} + +/* UINT _txe_thread_secure_stack_free( + TX_THREAD *thread_ptr -> param_0 + ); */ +static ALIGN_TYPE _txm_module_manager_tx_thread_secure_stack_free_dispatch(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE param_0) +{ + +ALIGN_TYPE return_value; + + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free( + (TX_THREAD *) param_0 + ); + return(return_value); +} \ No newline at end of file diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s b/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s new file mode 100644 index 00000000..92a5f4d2 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_initialize_low_level.s @@ -0,0 +1,204 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Initialize */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_initialize_unused_memory + EXTERN _tx_timer_interrupt + EXTERN __main + EXTERN __vector_table + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_stack_error_handler +; +; +SYSTEM_CLOCK EQU 96000000 +SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1) +; +; + RSEG FREE_MEM:DATA + PUBLIC __tx_free_memory_start +__tx_free_memory_start + DS32 4 +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB + +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_initialize_low_level Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for any low-level processor */ +;/* initialization, including setting up interrupt vectors, setting */ +;/* up a periodic timer interrupt source, saving the system stack */ +;/* pointer for use in ISR processing later, and finding the first */ +;/* available RAM memory address for tx_application_define. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_initialize_kernel_enter ThreadX entry function */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_initialize_low_level(VOID) +;{ + PUBLIC _tx_initialize_low_level +_tx_initialize_low_level: +; +; /* Disable interrupts during ThreadX initialization. */ +; + CPSID i +; +; /* Set base of available memory to end of non-initialised RAM area. */ +; + LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer + LDR r1, =__tx_free_memory_start ; Build first free address + STR r1, [r0] ; Setup first unused memory pointer +; +; /* Setup Vector Table Offset Register. */ +; + LDR r0, =0xE000ED08 ; Build address of NVIC registers + LDR r1, =__vector_table ; Pickup address of vector table + STR r1, [r0] ; Set vector table address +; +; /* Enable the cycle count register. */ +; +; LDR r0, =0xE0001000 ; Build address of DWT register +; LDR r1, [r0] ; Pickup the current value +; ORR r1, r1, #1 ; Set the CYCCNTENA bit +; STR r1, [r0] ; Enable the cycle count register +; +; /* Set system stack pointer from vector value. */ +; + LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer + LDR r1, =__vector_table ; Pickup address of vector table + LDR r1, [r1] ; Pickup reset stack pointer + STR r1, [r0] ; Save system stack pointer +; +; /* Configure SysTick. */ +; + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r1, =SYSTICK_CYCLES + STR r1, [r0, #0x14] ; Setup SysTick Reload Value + MOV r1, #0x7 ; Build SysTick Control Enable Value + STR r1, [r0, #0x10] ; Setup SysTick Control +; +; /* Configure handler priorities. */ +; + LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD18 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 4-7 Priority Registers + + LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD1C ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 8-11 Priority Registers + ; Note: SVC must be lowest priority, which is 0xFF + + LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM + LDR r0, =0xE000E000 ; Build address of NVIC registers + LDR r2, =0xD20 ; + ADD r0, r0, r2 ; + STR r1, [r0] ; Setup System Handlers 12-15 Priority Registers + ; Note: PnSV must be lowest priority, which is 0xFF +; +; /* Return to caller. */ +; + BX lr +;} +; +; +;/* Define shells for each of the unused vectors. */ +; + PUBLIC __tx_BadHandler +__tx_BadHandler: + B __tx_BadHandler + + + PUBLIC __tx_IntHandler +__tx_IntHandler: +; VOID InterruptHandler (VOID) +; { + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + +; /* Do interrupt handler work here */ +; /* .... */ + + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + + PUBLIC __tx_SysTickHandler + PUBLIC SysTick_Handler +SysTick_Handler: +__tx_SysTickHandler: +; VOID TimerInterruptHandler (VOID) +; { +; + PUSH {r0, lr} ; Save LR (and dummy r0 to maintain stack alignment) + BL _tx_timer_interrupt + POP {r0, r1} + MOV lr, r1 + BX lr +; } + + + PUBLIC HardFault_Handler +HardFault_Handler: + ; A stack overflow will trigger a hardfault. + ; There is no CFSR in M23, so we will not try to + ; determine if the fault is caused by a stack overflow + ; or some other condition. + B HardFault_Handler + + + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s new file mode 100644 index 00000000..48300c4d --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_restore.s @@ -0,0 +1,72 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_restore Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is not needed for Cortex-M. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* None */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_restore(VOID) +;{ + PUBLIC _tx_thread_context_restore +_tx_thread_context_restore: +; +; /* Return to interrupt processing. */ +; + BX lr +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s new file mode 100644 index 00000000..f666d4a4 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_context_save.s @@ -0,0 +1,72 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_context_save Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is not needed for Cortex-M. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* None */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_context_save(VOID) +;{ + PUBLIC _tx_thread_context_save +_tx_thread_context_save: +; +; /* Return to interrupt processing. */ +; + BX lr +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s new file mode 100644 index 00000000..83381d72 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_control.s @@ -0,0 +1,77 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_control Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for changing the interrupt lockout */ +;/* posture of the system. */ +;/* */ +;/* INPUT */ +;/* */ +;/* new_posture New interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_control(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_control +_tx_thread_interrupt_control: +; +; /* Pickup current interrupt lockout posture. */ +; + MRS r1, PRIMASK + MSR PRIMASK, r0 + MOV r0, r1 + BX lr +; +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s new file mode 100644 index 00000000..41ad894f --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_disable.s @@ -0,0 +1,76 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_disable Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for disabling interrupts and returning */ +;/* the previous interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* old_posture Old interrupt lockout posture */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_interrupt_disable(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_disable +_tx_thread_interrupt_disable: +; +; /* Return current interrupt lockout posture. */ +; + MRS r0, PRIMASK + CPSID i + BX lr +; +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s new file mode 100644 index 00000000..dd1c2985 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_interrupt_restore.s @@ -0,0 +1,75 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_interrupt_restore Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is responsible for restoring the previous */ +;/* interrupt lockout posture. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* previous_posture Previous interrupt posture */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_interrupt_restore(UINT new_posture) +;{ + PUBLIC _tx_thread_interrupt_restore +_tx_thread_interrupt_restore: +; +; /* Restore previous interrupt lockout posture. */ +; + MSR PRIMASK, r0 + BX lr +; +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s new file mode 100644 index 00000000..53bda596 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_schedule.s @@ -0,0 +1,640 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_timer_time_slice + EXTERN _tx_thread_system_stack_ptr + EXTERN _tx_thread_preempt_disable + EXTERN _tx_execution_thread_enter + EXTERN _tx_execution_thread_exit + EXTERN _txm_module_manager_memory_fault_handler + EXTERN _txm_module_manager_memory_fault_info + EXTERN _tx_thread_secure_stack_context_restore + EXTERN _tx_thread_secure_stack_context_save + EXTERN _tx_thread_secure_mode_stack_allocate + EXTERN _tx_thread_secure_mode_stack_free + EXTERN _tx_alloc_return + EXTERN _tx_free_return + SECTION `.text`:CODE:NOROOT(2) + THUMB +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_schedule Cortex-M23/IAR */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function waits for a thread control block pointer to appear in */ +/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */ +/* in the variable, the corresponding thread is resumed. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter ThreadX entry function */ +/* _tx_thread_system_return Return to system from thread */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _tx_thread_schedule(VOID) +// { + PUBLIC _tx_thread_schedule +_tx_thread_schedule: + + /* This function should only ever be called on Cortex-M + from the first schedule request. Subsequent scheduling occurs + from the PendSV handling routine below. */ + + /* Clear the preempt-disable flag to enable rescheduling after initialization on Cortex-M targets. */ + + MOVW r0, #0 // Build value for TX_FALSE + LDR r2, =_tx_thread_preempt_disable // Build address of preempt disable flag + STR r0, [r2, #0] // Clear preempt disable flag + + /* Enable memory fault registers. */ + + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, =0x70000 // Enable Usage, Bus, and MemManage faults + STR r1, [r0] // + + /* Enable interrupts */ + + CPSIE i + + /* Enter the scheduler for the first time. */ + + LDR r0, =0x10000000 // Load PENDSVSET bit + LDR r1, =0xE000ED04 // Load ICSR address + STR r0, [r1] // Set PENDSVBIT in ICSR + DSB // Complete all memory accesses + ISB // Flush pipeline + + /* Wait here for the PendSV to take place. */ + +__tx_wait_here: + B __tx_wait_here // Wait for the PendSV to happen +// } + + + /* Memory Exception Handler. */ + + PUBLIC MemManage_Handler + PUBLIC BusFault_Handler +MemManage_Handler: +BusFault_Handler: + + CPSID i // Disable interrupts + + /* Now pickup and store all the fault related information. */ + + LDR r2,=_txm_module_manager_memory_fault_info // Pickup fault info struct + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r1, [r0] // Pickup the current thread pointer + STR r1, [r2, #0] // Save current thread pointer in fault info structure + LDR r0, =0xE000ED24 // Build SHCSR address + LDR r1, [r0] // Pickup SHCSR + STR r1, [r2, #8] // Save SHCSR + LDR r0, =0xE000ED28 // Build CFSR address + LDR r1, [r0] // Pickup CFSR + STR r1, [r2, #12] // Save CFSR + LDR r0, =0xE000ED34 // Build MMFAR address + LDR r1, [r0] // Pickup MMFAR + STR r1, [r2, #16] // Save MMFAR + LDR r0, =0xE000ED38 // Build BFAR address + LDR r1, [r0] // Pickup BFAR + STR r1, [r2, #20] // Save BFAR + MRS r0, CONTROL // Pickup current CONTROL register + STR r0, [r2, #24] // Save CONTROL + MRS r1, PSP // Pickup thread stack pointer + STR r1, [r2, #28] // Save thread stack pointer + LDR r0, [r1] // Pickup saved r0 + STR r0, [r2, #32] // Save r0 + LDR r0, [r1, #4] // Pickup saved r1 + STR r0, [r2, #36] // Save r1 + LDR r0, [r1, #8] // Pickup saved r2 + STR r0, [r2, #40] // Save r2 + STR r3, [r2, #44] // Save r3 + STR r4, [r2, #48] // Save r4 + STR r5, [r2, #52] // Save r5 + STR r6, [r2, #56] // Save r6 + STR r7, [r2, #60] // Save r7 + MOV r0, r8 // Move r8 to moveable register + STR r0, [r2, #64] // Save r8 + MOV r0, r9 // Move r9 to moveable register + STR r0, [r2, #68] // Save r9 + MOV r0, r10 // Move r10 to moveable register + STR r0, [r2, #72] // Save r10 + MOV r0, r11 // Move r11 to moveable register + STR r0, [r2, #76] // Save r11 + LDR r0, [r1, #16] // Pickup saved r12 + STR r0, [r2, #80] // Save r12 + LDR r0, [r1, #20] // Pickup saved lr + STR r0, [r2, #84] // Save lr + LDR r0, [r1, #24] // Pickup instruction address at point of fault + STR r0, [r2, #4] // Save point of fault + LDR r0, [r1, #28] // Pickup xPSR + STR r0, [r2, #88] // Save xPSR + + MRS r0, CONTROL // Pickup current CONTROL register + MOVW r1, #0x1 // + BICS r0, r0, r1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + + LDR r0, =0xE000ED28 // Build the Memory Management Fault Status Register (MMFSR) + LDRB r1, [r0] // Pickup the MMFSR, with the following bit definitions: + // Bit 0 = 1 -> Instruction address violation + // Bit 1 = 1 -> Load/store address violation + // Bit 7 = 1 -> MMFAR is valid + STRB r1, [r0] // Clear the MMFSR + + BL _txm_module_manager_memory_fault_handler // Call memory manager fault handler + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + BL _tx_execution_thread_exit // Call the thread exit function + CPSIE i // Enable interrupts +#endif + + MOVW r1, #0 // Build NULL value + LDR r0, =_tx_thread_current_ptr // Pickup address of current thread pointer + STR r1, [r0] // Clear current thread pointer + + // Return from MemManage_Handler exception + LDR r0, =0xE000ED04 // Load ICSR + LDR r1, =0x10000000 // Set PENDSVSET bit + STR r1, [r0] // Store ICSR + DSB // Wait for memory access to complete + CPSIE i // Enable interrupts +#ifdef TX_SINGLE_MODE_SECURE + LDR r0, =0xFFFFFFFD // Exception return to secure +#else + LDR r0, =0xFFFFFFBC // Exception return to non-secure +#endif + MOV lr, r0 // Move exception return to lr + BX lr // Return from exception + + + /* Generic context switching PendSV handler. */ + + PUBLIC PendSV_Handler +PendSV_Handler: +__tx_ts_handler: + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread exit function to indicate the thread is no longer executing. */ + CPSID i // Disable interrupts + PUSH {r0, lr} // Save LR (and r0 just for alignment) + BL _tx_execution_thread_exit // Call the thread exit function + POP {r0, r1} // Recover LR + MOV lr, r1 + CPSIE i // Enable interrupts +#endif + + LDR r0, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, =_tx_thread_execute_ptr // Build execute thread pointer address + + MOVW r3, #0 // Build NULL value + LDR r1, [r0] // Pickup current thread pointer + + /* Determine if there is a current thread to finish preserving. */ + + CBZ r1, __tx_ts_new // If NULL, skip preservation + + /* Recover PSP and preserve current thread context. */ + + STR r3, [r0] // Set _tx_thread_current_ptr to NULL + MRS r3, PSP // Pickup PSP pointer (thread's stack pointer) + SUBS r3, r3, #16 // Allocate stack space + STM r3!, {r4-r7} // Save its remaining registers (M3 Instruction: STMDB r12!, {r4-r11}) + MOV r4, r8 // + MOV r5, r9 // + MOV r6, r10 // + MOV r7, r11 // + SUBS r3, r3, #32 // Allocate stack space + STM r3!, {r4-r7} // + SUBS r3, r3, #20 // Allocate stack space + MOV r5, lr // + STR r5, [r3] // Save LR on the stack + STR r3, [r1, #8] // Save the thread stack pointer + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Save secure context + LDR r5, =0xC4 // Secure stack index offset + LDR r5, [r1, r5] // Load secure stack index + CBZ r5, _skip_secure_save // Skip save if there is no secure context + PUSH {r0-r3} // Save scratch registers + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_save // Save secure stack + POP {r0-r3} // Restore secure registers +_skip_secure_save: +#endif + + /* Determine if time-slice is active. If it isn't, skip time handling processing. */ + + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r4] // Pickup current time-slice + CBZ r5, __tx_ts_new // If not active, skip processing + + /* Time-slice is active, save the current thread's time-slice and clear the global time-slice variable. */ + + STR r5, [r1, #24] // Save current time-slice + + /* Clear the global time-slice. */ + + MOVW r5, #0 // Build clear value + STR r5, [r4] // Clear time-slice + + /* Executing thread is now completely preserved!!! */ + +__tx_ts_new: + + /* Now we are looking for a new thread to execute! */ + + CPSID i // Disable interrupts + LDR r1, [r2] // Is there another thread ready to execute? + CBNZ r1, __tx_ts_restore // Yes, schedule it + + /* The following is the idle wait processing... in this case, no threads are ready for execution and the + system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts + are disabled to allow use of WFI for waiting for a thread to arrive. */ + +__tx_ts_wait: + CPSID i // Disable interrupts + LDR r1, [r2] // Pickup the next thread to execute pointer + CBNZ r1, __tx_ts_ready // If non-NULL, a new thread is ready! +#ifdef TX_ENABLE_WFI + DSB // Ensure no outstanding memory transactions + WFI // Wait for interrupt + ISB // Ensure pipeline is flushed +#endif + CPSIE i // Enable interrupts + B __tx_ts_wait // Loop to continue waiting + + /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are + already in the handler! */ + +__tx_ts_ready: + LDR r7, =0x08000000 // Build clear PendSV value + LDR r5, =0xE000ED04 // Build base NVIC address + STR r7, [r5] // Clear any PendSV + +__tx_ts_restore: + + /* A thread is ready, make the current thread the new thread + and enable interrupts. */ + + STR r1, [r0] // Setup the current thread pointer to the new thread + CPSIE i // Enable interrupts + + /* Increment the thread run count. */ + + LDR r7, [r1, #4] // Pickup the current thread run count + LDR r4, =_tx_timer_time_slice // Build address of time-slice variable + LDR r5, [r1, #24] // Pickup thread's current time-slice + ADDS r7, r7, #1 // Increment the thread run count + STR r7, [r1, #4] // Store the new run count + + /* Setup global time-slice with thread's current time-slice. */ + + STR r5, [r4] // Setup global time-slice + +#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY + /* Call the thread entry function to indicate the thread is executing. */ + PUSH {r0, r1} // Save r0 and r1 + BL _tx_execution_thread_enter // Call the thread execution enter function + POP {r0, r1} // Recover r0 and r1 +#endif + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + // Restore secure context + LDR r5, =0xC4 // Secure stack index offset + LDR r0, [r1, r5] // Load secure stack index + CBZ r0, _skip_secure_restore // Skip restore if there is no secure context + PUSH {r0, r1} // Save r1 (and dummy r0) + MOV r0, r1 // Move thread ptr to r0 + BL _tx_thread_secure_stack_context_restore // Restore secure stack + POP {r0, r1} // Restore r1 (and dummy r0) +_skip_secure_restore: +#endif + + // Set up CONTROL register based on user mode flag (privileged/unprivileged mode) + MRS r5, CONTROL // Pickup current CONTROL register + MOVS r2, #0x98 // Index of current user mode flag + LDR r4, [r1, r2] // Pickup current user mode flag + MOVW r0, #0x1 + BICS r5, r5, r0 // Clear the UNPRIV bit + ORRS r4, r4, r5 // Build new CONTROL register + MSR CONTROL, r4 // Setup new CONTROL register + + // Determine if MPU needs to be configured + LDR r0, =0xE000ED94 // Build MPU control reg address + MOVW r3, #0 // Build disable value + STR r3, [r0] // Disable MPU + MOVS r2, #0x90 // Index of module instance pointer + LDR r0, [r1, r2] // Pickup the module instance pointer + CBZ r0, skip_mpu_setup // Is this thread owned by a module? No, skip MPU setup + MOV r8, r1 // Copy thread ptr + LDR r1, [r0, #0x64] // Pickup MPU register[0] + CBZ r1, skip_mpu_setup // Is protection required for this module? No, skip MPU setup + + // Initialize loop to configure MPU registers + // Order doesn't matter, so txm_module_instance_mpu_registers[0] + // will be in region 7 and txm_module_instance_mpu_registers[7] will be in region 0. + MOVS r3, #0x64 // Index of MPU register settings in thread control block + ADD r0, r0, r3 // Build address of MPU register start in thread control block + MOVS r5, #0 // Select region 0 + LDR r4, =0xE000ED98 // Region register address + // Loop to load MPU registers +_tx_mpu_loop: + LDR r1, =0xE000ED9C // Build address of MPU base register + STR r5, [r4] // Set region + LDM r0!, {r2-r3} // Get MPU settings from the module + STM r1!, {r2-r3} // Set MPU registers for region + ADDS r5, r5, #1 // Increment to next region + CMP r5, #8 // Check if all regions have been set + BNE _tx_mpu_loop + + LDR r0, =0xE000ED94 // Build MPU control reg address + MOVS r1, #5 // Build enable value with background region enabled + STR r1, [r0] // Enable MPU + MOV r1, r8 // Get copied thread ptr + +skip_mpu_setup: + + // Restore the thread context and PSP + LDR r3, [r1, #8] // Pickup thread's stack pointer + LDR r5, [r3] // Recover saved LR + ADDS r3, r3, #4 // Position past LR + MOV lr, r5 // Restore LR + LDM r3!, {r4-r7} // Recover thread's registers (r8-r11) + MOV r11, r7 + MOV r10, r6 + MOV r9, r5 + MOV r8, r4 + LDM r3!, {r4-r7} // Recover thread's registers (r4-r7) + MSR PSP, r3 // Setup the thread's stack pointer + + BX lr // Return to thread! + + + + /* SVC Handler. */ + PUBLIC SVC_Handler +SVC_Handler: + MOV r0, lr + MOVS r1, #0x04 + TST r1, r0 // Determine return stack from EXC_RETURN bit 2 + BEQ _tx_load_msp + MRS r0, PSP // Get PSP + B _tx_get_svc +_tx_load_msp: + MRS r0, MSP // Get MSP +_tx_get_svc: + LDR r1, [r0,#24] // Load saved PC from stack + LDR r3, =-2 + LDRB r2, [r1,r3] // Load SVC number + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) + CMP r2, #1 // Is it a secure stack allocate request? + BEQ _tx_svc_secure_alloc // Yes, go there + + CMP r2, #2 // Is it a secure stack free request? + BEQ _tx_svc_secure_free // Yes, go there +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + CMP r2, #3 // Is it the entry into ThreadX? + BNE _tx_thread_user_return // No, return to user mode + + /* At this point we have an SVC 3, which means we are entering + the kernel from a module thread with user mode selected. */ + + LDR r2, =_txm_module_priv // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_entry? + BEQ _tx_entry_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_entry_continue: + LDR r3, [r0, #20] // This is the saved LR + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0 // Build clear value + MOVS r0, #0x98 // Index of current user mode + STR r1, [r2, r0] // Clear the current user mode selection for thread + MOVS r0, #0xA0 // Index of saved LR + STR r3, [r2, r0] // Save the original LR in thread control block + + /* If there is memory protection, use kernel stack */ + MOVS r0, #0x90 // Index of module instance ptr + LDR r0, [r2, r0] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + MOVS r1, #2 // MPU protection flag + TST r0, r1 // Check if memory protected + BEQ _tx_skip_kernel_stack_enter + + /* Switch to the module thread's kernel stack */ + MOVS r0, #0xA8 // Index of module kernel stack end + LDR r0, [r2, r0] // Load the module kernel stack end + MOVS r1, #0xA4 // Index of module kernel stack start + LDR r1, [r2, r1] // Load the module kernel stack start + MSR PSPLIM, r1 // Set stack limit +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOVS r3, #0xAC // Index of module kernel stack size + LDR r3, [r2, r3] // Load the module kernel stack size + STR r1, [r2, #12] // Set stack start + STR r0, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + + MRS r3, PSP // Pickup thread stack pointer + MOVS r1, #0xB0 // Index of module stack pointer + STR r3, [r2, r1] // Save thread stack pointer + + /* Build kernel stack by copying thread stack two registers at a time */ + SUBS r0, r0, #32 // Start at top of hardware stack + LDMIA r3!, {r1,r2} // Get r0, r1 from thread stack + STMIA r0!, {r1,r2} // Insert r0, r1 into kernel stack + LDMIA r3!, {r1,r2} // Get r2, r3 from thread stack + STMIA r0!, {r1,r2} // Insert r2, r3 into kernel stack + LDMIA r3!, {r1,r2} // Get r12, lr from thread stack + STMIA r0!, {r1,r2} // Insert r12, lr into kernel stack + LDMIA r3!, {r1,r2} // Get pc, xpsr from thread stack + STMIA r0!, {r1,r2} // Insert pc, xpsr into kernel stack + SUBS r0, r0, #32 // Go back to top of stack + + MSR PSP, r0 // Set kernel stack pointer + +_tx_skip_kernel_stack_enter: + MRS r0, CONTROL // Pickup current CONTROL register + MOVW r1, #0x1 // + BICS r0, r0, r1 // Clear the UNPRIV bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + +_tx_thread_user_return: + LDR r2, =_txm_module_user_mode_exit // Load address of where we should have come from + CMP r1, r2 // Did we come from user_mode_exit? + BEQ _tx_exit_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_exit_continue: + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0x9C // Index of user mode + MOVS r3, #0x98 // Index of current user mode + LDR r1, [r2, r1] // Pick up user mode + STR r1, [r2, r3] // Set the current user mode selection for thread + + /* If there is memory protection, use kernel stack */ + MOVS r0, #0x90 // Index of module instance ptr + LDR r0, [r2, r0] // Load the module instance ptr + LDR r0, [r0, #0x0C] // Load the module property flags + MOVS r1, #2 // MPU protection flag + TST r0, r1 // Check if memory protected + BEQ _tx_skip_kernel_stack_exit + + MOVS r0, #0xB4 // Index of module thread stack start + LDR r0, [r2, r0] // Load the module thread stack start + MSR PSPLIM, r0 // Set stack limit +#ifndef TXM_MODULE_KERNEL_STACK_MAINTENANCE_DISABLE + MOVS r1, #0xB8 // Index of module thread stack end + LDR r1, [r2, r1] // Load the module thread stack end + MOVS r3, #0xBC // Index of module thread stack size + LDR r3, [r2, r3] // Load the module thread stack size + STR r0, [r2, #12] // Set stack start + STR r1, [r2, #16] // Set stack end + STR r3, [r2, #20] // Set stack size +#endif + MOVS r1, #0xB0 // Index of module thread stack pointer + LDR r0, [r2, r1] // Load the module thread stack pointer + MRS r3, PSP // Pickup kernel stack pointer + + /* Copy kernel hardware stack to module thread stack. */ + LDM r3!,{r1-r2} // Get r0, r1 from kernel stack + STM r0!,{r1-r2} // Insert r0, r1 into thread stack + LDM r3!,{r1-r2} // Get r2, r3 from kernel stack + STM r0!,{r1-r2} // Insert r2, r3 into thread stack + LDM r3!,{r1-r2} // Get r12, lr from kernel stack + STM r0!,{r1-r2} // Insert r12, lr into thread stack + LDM r3!,{r1-r2} // Get pc, xpsr from kernel stack + STM r0!,{r1-r2} // Insert pc, xpsr into thread stack + SUBS r0, r0, #32 // Subtract 32 to get back to top of stack + MSR PSP, r0 // Set thread stack pointer + + LDR r1, =_tx_thread_current_ptr // Build current thread pointer address + LDR r2, [r1] // Pickup current thread pointer + MOVS r1, #0x9C // Index of user mode + LDR r1, [r2, r1] // Pick up user mode + +_tx_skip_kernel_stack_exit: + MRS r0, CONTROL // Pickup current CONTROL register + ORRS r0, r0, r1 // OR in the user mode bit + MSR CONTROL, r0 // Setup new CONTROL register + BX lr // Return to thread + + +#if (!defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE)) +_tx_svc_secure_alloc: + LDR r2, =_tx_alloc_return // Load address of where we should have come from + CMP r1, r2 // Did we come from _tx_thread_secure_stack_allocate? + BEQ _tx_alloc_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_alloc_continue: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_allocate + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr + +_tx_svc_secure_free: + LDR r2, =_tx_free_return // Load address of where we should have come from + CMP r1, r2 // Did we come from _tx_thread_secure_stack_free? + BEQ _tx_free_continue // If no (not equal), then... + BX lr // return from where we came. +_tx_free_continue: + PUSH {r0, lr} // Save SP and EXC_RETURN + LDM r0, {r0-r3} // Load function parameters from stack + BL _tx_thread_secure_mode_stack_free + POP {r1, r2} // Restore SP and EXC_RETURN + STR r0, [r1] // Store function return value + MOV lr, r2 + BX lr +#endif // End of ifndef TX_SINGLE_MODE_SECURE, TX_SINGLE_MODE_NON_SECURE + + + + /* Kernel entry function from user mode. */ + + EXTERN _txm_module_manager_kernel_dispatch + SECTION `.text`:CODE:NOROOT(5) + THUMB + ALIGNROM 5 +// VOID _txm_module_manager_user_mode_entry(VOID) +// { + PUBLIC _txm_module_manager_user_mode_entry +_txm_module_manager_user_mode_entry: + SVC 3 // Enter kernel +_txm_module_priv: + /* At this point, we are out of user mode. The original LR has been saved in the + thread control block. Simply call the kernel dispatch function. */ + BL _txm_module_manager_kernel_dispatch + + /* Pickup the original LR value while still in privileged mode */ + LDR r2, =_tx_thread_current_ptr // Build current thread pointer address + LDR r3, [r2] // Pickup current thread pointer + LDR r2, =0xA0 // Index of saved LR + LDR r1, [r3, r2] // Pickup saved LR from original call + MOV lr, r1 + SVC 4 // Exit kernel and return to user mode +_txm_module_user_mode_exit: + BX lr // Return to the caller + NOP + NOP + NOP + NOP +// } + + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c new file mode 100644 index 00000000..b9ba72ff --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack.c @@ -0,0 +1,485 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +#include "tx_api.h" + +/* If TX_SINGLE_MODE_SECURE or TX_SINGLE_MODE_NON_SECURE is defined, + no secure stack functionality is needed. */ +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + +#define TX_SOURCE_CODE + +#include /* For intrinsic functions. */ +#include "tx_secure_interface.h" /* Interface for NS code. */ + +/* Minimum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MINIMUM +#define TX_THREAD_SECURE_STACK_MINIMUM 256 +#endif +/* Maximum size of secure stack. */ +#ifndef TX_THREAD_SECURE_STACK_MAXIMUM +#define TX_THREAD_SECURE_STACK_MAXIMUM 1024 +#endif + +/* 8 bytes added to stack size to "seal" stack. */ +#define TX_THREAD_STACK_SEAL_SIZE 8 +#define TX_THREAD_STACK_SEAL_VALUE 0xFEF5EDA5 + +/* Secure stack info struct to hold stack start, stack limit, + current stack pointer, and pointer to owning thread. + This will be allocated for each thread with a secure stack. */ +typedef struct TX_THREAD_SECURE_STACK_INFO_STRUCT +{ + VOID *tx_thread_secure_stack_ptr; /* Thread's secure stack current pointer */ + VOID *tx_thread_secure_stack_start; /* Thread's secure stack start address */ + VOID *tx_thread_secure_stack_limit; /* Thread's secure stack limit */ + TX_THREAD *tx_thread_ptr; /* Keep track of thread for error handling */ +} TX_THREAD_SECURE_STACK_INFO; + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_initialize Cortex-M23/IAR */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes secure mode to use PSP stack. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_CONTROL Intrinsic to get CONTROL */ +/* __set_CONTROL Intrinsic to set CONTROL */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_initialize_kernel_enter */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_initialize(void) +{ + + /* Set secure mode to use PSP. */ + __set_CONTROL(__get_CONTROL() | 2); + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_allocate Cortex-M23/IAR */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of stack to allocates */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_SIZE_ERROR Invalid stack size */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* calloc Compiler's calloc function */ +/* malloc Compiler's malloc function */ +/* free Compiler's free() function */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* __TZ_get_PSPLIM_NS Intrinsic to get NS PSP */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* added stack sealing, */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; +UCHAR *stack_mem; +ULONG sp; + + status = TX_SUCCESS; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + else if (stack_size < TX_THREAD_SECURE_STACK_MINIMUM || stack_size > TX_THREAD_SECURE_STACK_MAXIMUM) + { + status = TX_SIZE_ERROR; + } + + /* Check if thread already has secure stack allocated. */ + else if (thread_ptr -> tx_thread_secure_stack_context != 0) + { + status = TX_THREAD_ERROR; + } + + else + { + /* Allocate space for secure stack info. */ + info_ptr = calloc(1, sizeof(TX_THREAD_SECURE_STACK_INFO)); + + if(info_ptr != TX_NULL) + { + /* If stack info allocated, allocate a stack & seal. */ + stack_mem = malloc(stack_size + TX_THREAD_STACK_SEAL_SIZE); + + if(stack_mem != TX_NULL) + { + /* Secure stack has been allocated, save in the stack info struct. */ + info_ptr -> tx_thread_secure_stack_limit = stack_mem; + info_ptr -> tx_thread_secure_stack_start = stack_mem + stack_size; + info_ptr -> tx_thread_secure_stack_ptr = info_ptr -> tx_thread_secure_stack_start; + info_ptr -> tx_thread_ptr = thread_ptr; + + /* Seal bottom of stack. */ + *(ULONG*)info_ptr -> tx_thread_secure_stack_start = TX_THREAD_STACK_SEAL_VALUE; + + /* Save info pointer in thread. */ + thread_ptr -> tx_thread_secure_stack_context = info_ptr; + + /* Check if this thread is running by looking at PSP_NS and seeing if it is within + the stack_start and stack_end range. */ + sp = __TZ_get_PSP_NS(); + if(sp > ((ULONG) thread_ptr -> tx_thread_stack_start) && sp < ((ULONG) thread_ptr -> tx_thread_stack_end)) + { + /* If this thread is running, set Secure PSP and PSPLIM. */ + __set_PSPLIM((ULONG)(info_ptr -> tx_thread_secure_stack_limit)); + __set_PSP((ULONG)(info_ptr -> tx_thread_secure_stack_ptr)); + } + } + + else + { + /* Stack not allocated, free the info struct. */ + free(info_ptr); + status = TX_NO_MEMORY; + } + } + + else + { + status = TX_NO_MEMORY; + } + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_mode_stack_free Cortex-M23/IAR */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a thread's secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* free Compiler's free() function */ +/* */ +/* CALLED BY */ +/* */ +/* SVC Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +UINT _tx_thread_secure_mode_stack_free(TX_THREAD *thread_ptr) +{ +UINT status; +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + status = TX_SUCCESS; + + /* Pickup stack info from thread. */ + info_ptr = thread_ptr -> tx_thread_secure_stack_context; + + /* Make sure function is called from interrupt (threads should not call). */ + if (__get_IPSR() == 0) + { + status = TX_CALLER_ERROR; + } + + /* Check that this secure context is for this thread. */ + else if (info_ptr -> tx_thread_ptr != thread_ptr) + { + status = TX_THREAD_ERROR; + } + + else + { + + /* Free secure stack. */ + free(info_ptr -> tx_thread_secure_stack_limit); + + /* Free info struct. */ + free(info_ptr); + + /* Clear secure context from thread. */ + thread_ptr -> tx_thread_secure_stack_context = 0; + } + + return(status); +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_save Cortex-M23/IAR */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __get_PSP Intrinsic to get PSP */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_save(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; +ULONG sp; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Check that stack pointer is in range */ + sp = __get_PSP(); + if ((sp < (ULONG)info_ptr -> tx_thread_secure_stack_limit) || + (sp > (ULONG)info_ptr -> tx_thread_secure_stack_start)) + { + return; + } + + /* Save stack pointer. */ + *(ULONG *) info_ptr -> tx_thread_secure_stack_ptr = sp; + + /* Set process stack pointer and stack limit to 0 to throw exception when a thread + without a secure stack calls a secure function that tries to use secure stack. */ + __set_PSPLIM(0); + __set_PSP(0); + + return; +} + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_secure_stack_context_restore Cortex-M23/IAR */ +/* 6.1.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores context of the secure stack. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* __get_IPSR Intrinsic to get IPSR */ +/* __set_PSPLIM Intrinsic to set PSP limit */ +/* __set_PSP Intrinsic to set PSP */ +/* */ +/* CALLED BY */ +/* */ +/* PendSV Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 10-16-2020 Scott Larson Modified comment(s), */ +/* resulting in version 6.1.1 */ +/* */ +/**************************************************************************/ +__attribute__((cmse_nonsecure_entry)) +void _tx_thread_secure_stack_context_restore(TX_THREAD *thread_ptr) +{ +TX_THREAD_SECURE_STACK_INFO *info_ptr; + + /* This function should be called from scheduler only. */ + if (__get_IPSR() == 0) + { + return; + } + + /* Pickup the secure context pointer. */ + info_ptr = (TX_THREAD_SECURE_STACK_INFO *)(thread_ptr -> tx_thread_secure_stack_context); + + /* Check that this secure context is for this thread. */ + if (info_ptr -> tx_thread_ptr != thread_ptr) + { + return; + } + + /* Set stack pointer and limit. */ + __set_PSPLIM((ULONG)info_ptr -> tx_thread_secure_stack_limit); + __set_PSP ((ULONG)info_ptr -> tx_thread_secure_stack_ptr); + + return; +} + +#endif diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s new file mode 100644 index 00000000..9ae3dcdb --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_allocate.s @@ -0,0 +1,82 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_allocate Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to allocate a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* stack_size Size of secure stack to */ +;/* allocate */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 1 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +;{ + EXPORT _tx_thread_secure_stack_allocate +_tx_thread_secure_stack_allocate: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 1 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _alloc_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts +#else + MOV32 r0, #0xFF ; Feature not enabled +#endif +_alloc_return_interrupt_enabled + BX lr + + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s new file mode 100644 index 00000000..b8e5bef8 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_secure_stack_free.s @@ -0,0 +1,79 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_secure_stack_free Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function enters the SVC handler to free a secure stack. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Thread control block pointer */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* status Actual completion status */ +;/* */ +;/* CALLS */ +;/* */ +;/* SVC 2 */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* Application Code */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;UINT _tx_thread_secure_stack_free(TX_THREAD *thread_ptr) +;{ + EXPORT _tx_thread_secure_stack_free +_tx_thread_secure_stack_free: +#if !defined(TX_SINGLE_MODE_SECURE) && !defined(TX_SINGLE_MODE_NON_SECURE) + MRS r3, PRIMASK ; Save interrupt mask + CPSIE i ; Enable interrupts for SVC call + SVC 2 + CMP r3, #0 ; If interrupts enabled, just return + BEQ _free_return_interrupt_enabled + CPSID i ; Otherwise, disable interrupts +#else + MOV32 r0, #0xFF ; Feature not enabled +#endif +_free_return_interrupt_enabled + BX lr + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s new file mode 100644 index 00000000..6525df4a --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_build.s @@ -0,0 +1,138 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_stack_build Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function builds a stack frame on the supplied thread's stack. */ +;/* The stack frame results in a fake interrupt return to the supplied */ +;/* function pointer. */ +;/* */ +;/* INPUT */ +;/* */ +;/* thread_ptr Pointer to thread control blk */ +;/* function_ptr Pointer to return function */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* None */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* _tx_thread_create Create thread service */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) +;{ + PUBLIC _tx_thread_stack_build +_tx_thread_stack_build: +; +; /* Build a fake interrupt frame. The form of the fake interrupt stack +; on the Cortex-M23 should look like the following after it is built: +; +; Stack Top: +; LR Interrupted LR (LR at time of PENDSV) +; r8 Initial value for r8 +; r9 Initial value for r9 +; r10 Initial value for r10 +; r11 Initial value for r11 +; r4 Initial value for r4 +; r5 Initial value for r5 +; r6 Initial value for r6 +; r7 Initial value for r7 +; r0 Initial value for r0 (Hardware stack starts here!!) +; r1 Initial value for r1 +; r2 Initial value for r2 +; r3 Initial value for r3 +; r12 Initial value for r12 +; lr Initial value for lr +; pc Initial value for pc +; xPSR Initial value for xPSR +; +; Stack Bottom: (higher memory address) */ +; + LDR r2, [r0, #16] ; Pickup end of stack area + MOVS r3, #0x7 ; + BICS r2, r2, r3 ; Align frame for 8-byte alignment + SUBS r2, r2, #68 ; Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD ; Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC ; Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] ; Save on the stack +; +; /* Actually build the stack frame. */ +; + MOV r3, #0 ; Build initial register value + STR r3, [r2, #4] ; Store initial r8 + STR r3, [r2, #8] ; Store initial r9 + STR r3, [r2, #12] ; Store initial r10 + STR r3, [r2, #16] ; Store initial r11 + STR r3, [r2, #20] ; Store initial r4 + STR r3, [r2, #24] ; Store initial r5 + STR r3, [r2, #28] ; Store initial r6 + STR r3, [r2, #32] ; Store initial r7 +; +; /* Hardware stack follows. */ +; + STR r3, [r2, #36] ; Store initial r0 + STR r3, [r2, #40] ; Store initial r1 + STR r3, [r2, #44] ; Store initial r2 + STR r3, [r2, #48] ; Store initial r3 + STR r3, [r2, #52] ; Store initial r12 + LDR r3, =0xFFFFFFFF ; Poison EXC_RETURN value + STR r3, [r2, #56] ; Store initial lr + STR r1, [r2, #60] ; Store initial pc + LDR r3, =0x01000000 ; Only T-bit need be set + STR r3, [r2, #64] ; Store initial xPSR +; +; /* Setup stack pointer. */ +; thread_ptr -> tx_thread_stack_ptr = r2; +; + STR r2, [r0, #8] ; Save stack pointer in thread's + ; control block + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c new file mode 100644 index 00000000..ef98240c --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_handler.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" + +/* Define the global function pointer for stack error handling. If a stack error is + detected and the application has registered a stack error handler, it will be + called via this function pointer. */ + +VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_handler Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function processes stack errors detected during run-time. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate */ +/* _tx_thread_application_stack_error_handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX internal code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +VOID _tx_thread_stack_error_handler(TX_THREAD *thread_ptr) +{ + #ifndef TX_THREAD_NO_TERMINATE_STACK_ERROR + /* Is there a thread? */ + if (thread_ptr) + { + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + #endif + + /* Determine if the application has registered an error handler. */ + if (_tx_thread_application_stack_error_handler != TX_NULL) + { + /* Yes, an error handler is present, simply call the application error handler. */ + (_tx_thread_application_stack_error_handler)(thread_ptr); + } +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c new file mode 100644 index 00000000..ffd78d08 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_stack_error_notify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_thread.h" +#include "tx_trace.h" + +extern VOID (*_tx_thread_application_stack_error_handler)(TX_THREAD *thread_ptr); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _tx_thread_stack_error_notify Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application stack error handler. If */ +/* ThreadX detects a stack error, this application handler is called. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* stack_error_handler Pointer to stack error */ +/* handler, TX_NULL to disable */ +/* */ +/* OUTPUT */ +/* */ +/* status Service return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _tx_thread_stack_error_notify(VOID (*stack_error_handler)(TX_THREAD *thread_ptr)) +{ + +TX_INTERRUPT_SAVE_AREA + + /* Disable interrupts. */ + TX_DISABLE + + /* Make entry in event log. */ + TX_TRACE_IN_LINE_INSERT(TX_TRACE_THREAD_STACK_ERROR_NOTIFY, 0, 0, 0, 0, TX_TRACE_THREAD_EVENTS) + + /* Make entry in event log. */ + TX_EL_THREAD_STACK_ERROR_NOTIFY_INSERT + + /* Setup global thread stack error handler. */ + _tx_thread_application_stack_error_handler = stack_error_handler; + + /* Restore interrupts. */ + TX_RESTORE + + /* Return success to caller. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s new file mode 100644 index 00000000..1afb41f6 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_thread_system_return.s @@ -0,0 +1,87 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Thread */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_thread_system_return Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function is target processor specific. It is used to transfer */ +;/* control from a thread back to the ThreadX system. Only a */ +;/* minimal context is saved since the compiler assumes temp registers */ +;/* are going to get slicked by a function call anyway. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_thread_schedule Thread scheduling loop */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* ThreadX components */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_thread_system_return(VOID) +;{ + PUBLIC _tx_thread_system_return +_tx_thread_system_return??rA: +_tx_thread_system_return: +; +; /* Return to real scheduler via PendSV. Note that this routine is often +; replaced with in-line assembly in tx_port.h to improved performance. */ +; + LDR r0, =0x10000000 ; Load PENDSVSET bit + LDR r1, =0xE000ED04 ; Load ICSR address + STR r0, [r1] ; Set PENDSVBIT in ICSR + MRS r0, IPSR ; Pickup IPSR + CMP r0, #0 ; Is it a thread returning? + BNE _isr_context ; If ISR, skip interrupt enable + MRS r1, PRIMASK ; Thread context returning, pickup PRIMASK + CPSIE i ; Enable interrupts + MSR PRIMASK, r1 ; Restore original interrupt posture +_isr_context: + BX lr ; Return to caller +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s new file mode 100644 index 00000000..89e185b3 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/tx_timer_interrupt.s @@ -0,0 +1,256 @@ +;/**************************************************************************/ +;/* */ +;/* Copyright (c) Microsoft Corporation. All rights reserved. */ +;/* */ +;/* This software is licensed under the Microsoft Software License */ +;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +;/* and in the root directory of this software. */ +;/* */ +;/**************************************************************************/ +; +; +;/**************************************************************************/ +;/**************************************************************************/ +;/** */ +;/** ThreadX Component */ +;/** */ +;/** Timer */ +;/** */ +;/**************************************************************************/ +;/**************************************************************************/ +; +; + EXTERN _tx_timer_time_slice + EXTERN _tx_timer_system_clock + EXTERN _tx_timer_current_ptr + EXTERN _tx_timer_list_start + EXTERN _tx_timer_list_end + EXTERN _tx_timer_expired_time_slice + EXTERN _tx_timer_expired + EXTERN _tx_thread_time_slice + EXTERN _tx_timer_expiration_process + EXTERN _tx_thread_current_ptr + EXTERN _tx_thread_execute_ptr + EXTERN _tx_thread_preempt_disable +; +; + SECTION `.text`:CODE:NOROOT(2) + THUMB +;/**************************************************************************/ +;/* */ +;/* FUNCTION RELEASE */ +;/* */ +;/* _tx_timer_interrupt Cortex-M23/IAR */ +;/* 6.1 */ +;/* AUTHOR */ +;/* */ +;/* Scott Larson, Microsoft Corporation */ +;/* */ +;/* DESCRIPTION */ +;/* */ +;/* This function processes the hardware timer interrupt. This */ +;/* processing includes incrementing the system clock and checking for */ +;/* time slice and/or timer expiration. If either is found, the */ +;/* the expiration functions are called. */ +;/* */ +;/* INPUT */ +;/* */ +;/* None */ +;/* */ +;/* OUTPUT */ +;/* */ +;/* None */ +;/* */ +;/* CALLS */ +;/* */ +;/* _tx_timer_expiration_process Timer expiration processing */ +;/* _tx_thread_time_slice Time slice interrupted thread */ +;/* */ +;/* CALLED BY */ +;/* */ +;/* interrupt vector */ +;/* */ +;/* RELEASE HISTORY */ +;/* */ +;/* DATE NAME DESCRIPTION */ +;/* */ +;/* 09-30-2020 Scott Larson Initial Version 6.1 */ +;/* */ +;/**************************************************************************/ +;VOID _tx_timer_interrupt(VOID) +;{ + PUBLIC _tx_timer_interrupt +_tx_timer_interrupt: +; +; /* Upon entry to this routine, it is assumed that the compiler scratch registers are available +; for use. */ +; +; /* Increment the system clock. */ +; _tx_timer_system_clock++; +; + MOV32 r1, _tx_timer_system_clock ; Pickup address of system clock + LDR r0, [r1, #0] ; Pickup system clock + ADDS r0, r0, #1 ; Increment system clock + STR r0, [r1, #0] ; Store new system clock +; +; /* Test for time-slice expiration. */ +; if (_tx_timer_time_slice) +; { +; + MOV32 r3, _tx_timer_time_slice ; Pickup address of time-slice + LDR r2, [r3, #0] ; Pickup time-slice + CBZ r2, __tx_timer_no_time_slice ; Is it non-active? + ; Yes, skip time-slice processing +; +; /* Decrement the time_slice. */ +; _tx_timer_time_slice--; +; + SUBS r2, r2, #1 ; Decrement the time-slice + STR r2, [r3, #0] ; Store new time-slice value +; +; /* Check for expiration. */ +; if (__tx_timer_time_slice == 0) +; + CBNZ r2, __tx_timer_no_time_slice ; Has it expired? +; +; /* Set the time-slice expired flag. */ +; _tx_timer_expired_time_slice = TX_TRUE; +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup address of expired flag + MOV r0, #1 ; Build expired value + STR r0, [r3, #0] ; Set time-slice expiration flag +; +; } +; +__tx_timer_no_time_slice: +; +; /* Test for timer expiration. */ +; if (*_tx_timer_current_ptr) +; { +; + MOV32 r1, _tx_timer_current_ptr ; Pickup current timer pointer address + LDR r0, [r1, #0] ; Pickup current timer + LDR r2, [r0, #0] ; Pickup timer list entry + CBZ r2, __tx_timer_no_timer ; Is there anything in the list? + ; No, just increment the timer +; +; /* Set expiration flag. */ +; _tx_timer_expired = TX_TRUE; +; + MOV32 r3, _tx_timer_expired ; Pickup expiration flag address + MOV r2, #1 ; Build expired value + STR r2, [r3, #0] ; Set expired flag + B __tx_timer_done ; Finished timer processing +; +; } +; else +; { +__tx_timer_no_timer: +; +; /* No timer expired, increment the timer pointer. */ +; _tx_timer_current_ptr++; +; + ADDS r0, r0, #4 ; Move to next timer +; +; /* Check for wrap-around. */ +; if (_tx_timer_current_ptr == _tx_timer_list_end) +; + MOV32 r3, _tx_timer_list_end ; Pickup addr of timer list end + LDR r2, [r3, #0] ; Pickup list end + CMP r0, r2 ; Are we at list end? + BNE __tx_timer_skip_wrap ; No, skip wrap-around logic +; +; /* Wrap to beginning of list. */ +; _tx_timer_current_ptr = _tx_timer_list_start; +; + MOV32 r3, _tx_timer_list_start ; Pickup addr of timer list start + LDR r0, [r3, #0] ; Set current pointer to list start +; +__tx_timer_skip_wrap: +; + STR r0, [r1, #0] ; Store new current timer pointer +; } +; +__tx_timer_done: +; +; +; /* See if anything has expired. */ +; if ((_tx_timer_expired_time_slice) || (_tx_timer_expired)) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of expired flag + LDR r2, [r3, #0] ; Pickup time-slice expired flag + CBNZ r2, __tx_something_expired ; Did a time-slice expire? + ; If non-zero, time-slice expired + MOV32 r1, _tx_timer_expired ; Pickup addr of other expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_nothing_expired ; Did a timer expire? + ; No, nothing expired +; +__tx_something_expired: +; +; + STMDB sp!, {r0, lr} ; Save the lr register on the stack + ; and save r0 just to keep 8-byte alignment +; +; /* Did a timer expire? */ +; if (_tx_timer_expired) +; { +; + MOV32 r1, _tx_timer_expired ; Pickup addr of expired flag + LDR r0, [r1, #0] ; Pickup timer expired flag + CBZ r0, __tx_timer_dont_activate ; Check for timer expiration + ; If not set, skip timer activation +; +; /* Process timer expiration. */ +; _tx_timer_expiration_process(); +; + BL _tx_timer_expiration_process ; Call the timer expiration handling routine +; +; } +__tx_timer_dont_activate: +; +; /* Did time slice expire? */ +; if (_tx_timer_expired_time_slice) +; { +; + MOV32 r3, _tx_timer_expired_time_slice ; Pickup addr of time-slice expired + LDR r2, [r3, #0] ; Pickup the actual flag + CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set + ; No, skip time-slice processing +; +; /* Time slice interrupted thread. */ +; _tx_thread_time_slice(); + + BL _tx_thread_time_slice ; Call time-slice processing + MOV32 r0, _tx_thread_preempt_disable ; Build address of preempt disable flag + LDR r1, [r0] ; Is the preempt disable flag set? + CBNZ r1, __tx_timer_skip_time_slice ; Yes, skip the PendSV logic + MOV32 r0, _tx_thread_current_ptr ; Build current thread pointer address + LDR r1, [r0] ; Pickup the current thread pointer + MOV32 r2, _tx_thread_execute_ptr ; Build execute thread pointer address + LDR r3, [r2] ; Pickup the execute thread pointer + MOV32 r0, 0xE000ED04 ; Build address of control register + MOV32 r2, 0x10000000 ; Build value for PendSV bit + CMP r1, r3 ; Are they the same? + BEQ __tx_timer_skip_time_slice ; If the same, there was no time-slice performed + STR r2, [r0] ; Not the same, issue the PendSV for preemption +__tx_timer_skip_time_slice: +; +; } +; +__tx_timer_not_ts_expiration: +; + POP {r0, r1} ; Recover lr register (r0 is just there for + MOV lr, r1 ; the 8-byte stack alignment +; +; } +; +__tx_timer_nothing_expired: + + DSB ; Complete all memory access + BX lr ; Return to caller +; +;} + END diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c new file mode 100644 index 00000000..35482b6c --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_allocate.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_allocate Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack allocate */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* stack_size Size of secure stack to */ +/* allocate */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_allocate Actual stack alloc function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_allocate(TX_THREAD *thread_ptr, ULONG stack_size) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_allocate(thread_ptr, stack_size); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c new file mode 100644 index 00000000..950e8ec0 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txe_thread_secure_stack_free.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Thread */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "tx_api.h" +#include "tx_initialize.h" +#include "tx_thread.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txe_thread_secure_stack_free Cortex-M23 */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the secure stack free */ +/* function call. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* TX_THREAD_ERROR Invalid thread pointer */ +/* TX_CALLER_ERROR Invalid caller of function */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_secure_stack_free Actual stack free function */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _txe_thread_secure_stack_free(TX_THREAD *thread_ptr) +{ +#if defined(TX_SINGLE_MODE_SECURE) || defined(TX_SINGLE_MODE_NON_SECURE) + return(TX_FEATURE_NOT_ENABLED); +#else +UINT status; + + /* Default status to success. */ + status = TX_SUCCESS; + + /* Check for an invalid thread pointer. */ + if (thread_ptr == TX_NULL) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Now check for invalid thread ID. */ + else if (thread_ptr -> tx_thread_id != TX_THREAD_ID) + { + + /* Thread pointer is invalid, return appropriate error code. */ + status = TX_THREAD_ERROR; + } + + /* Check for interrupt call. */ + if (TX_THREAD_GET_SYSTEM_STATE() != ((ULONG) 0)) + { + /* Is call from an interrupt and not initialization? */ + if (TX_THREAD_GET_SYSTEM_STATE() < TX_INITIALIZE_IN_PROGRESS) + { + /* Invalid caller of this function, return appropriate error code. */ + status = TX_CALLER_ERROR; + } + } + + /* Determine if everything is okay. */ + if (status == TX_SUCCESS) + { + + /* Call actual secure stack allocate function. */ + status = _tx_thread_secure_stack_free(thread_ptr); + } + + /* Return completion status. */ + return(status); +#endif +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c new file mode 100644 index 00000000..f3a37aa9 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_alignment_adjust.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_alignment_adjust Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function adjusts the alignment and size of the code and data */ +/* section for a given module implementation. */ +/* */ +/* INPUT */ +/* */ +/* module_preamble Pointer to module preamble */ +/* code_size Size of the code area (updated) */ +/* code_alignment Code area alignment (updated) */ +/* data_size Size of data area (updated) */ +/* data_alignment Data area alignment (updated) */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Initial thread stack frame */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_alignment_adjust(TXM_MODULE_PREAMBLE *module_preamble, + ULONG *code_size, + ULONG *code_alignment, + ULONG *data_size, + ULONG *data_alignment) +{ + + /* Round code and data size UP to TXM_MODULE_MPU_ALIGNMENT bytes. */ + *code_size = (*code_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); + *data_size = (*data_size + TXM_MODULE_MPU_ALIGNMENT - 1) & ~(TXM_MODULE_MPU_ALIGNMENT - 1); + + /* Alignment for code and data is TXM_MODULE_MPU_ALIGNMENT bytes. */ + *code_alignment = TXM_MODULE_MPU_ALIGNMENT; + *data_alignment = TXM_MODULE_MPU_ALIGNMENT; +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c new file mode 100644 index 00000000..4869407c --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_external_memory_enable.c @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_mutex.h" +#include "tx_queue.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_external_memory_enable Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates an entry in the MPU table for a shared */ +/* memory space. The start_address must be 32-byte aligned. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module instance pointer */ +/* start_address Start address of memory */ +/* length Length of external memory */ +/* attributes Memory attributes (r/w) */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* _tx_mutex_get Get protection mutex */ +/* _tx_mutex_put Release protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_external_memory_enable(TXM_MODULE_INSTANCE *module_instance, + VOID *start_address, + ULONG length, + UINT attributes) +{ + +ULONG address; +ULONG shared_index; + + /* Determine if the module manager has not been initialized yet. */ + if (_txm_module_manager_ready != TX_TRUE) + { + /* Module manager has not been initialized. */ + return(TX_NOT_AVAILABLE); + } + + /* Determine if the module is valid. */ + if (module_instance == TX_NULL) + { + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Get module manager protection mutex. */ + _tx_mutex_get(&_txm_module_manager_mutex, TX_WAIT_FOREVER); + + /* Determine if the module instance is valid. */ + if (module_instance -> txm_module_instance_id != TXM_MODULE_ID) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Invalid module pointer. */ + return(TX_PTR_ERROR); + } + + /* Determine if the module instance is in the loaded state. */ + if (module_instance -> txm_module_instance_state != TXM_MODULE_LOADED) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return error if the module is not ready. */ + return(TX_START_ERROR); + } + + /* Determine if there are shared memory entries available. */ + if(module_instance -> txm_module_instance_shared_memory_count >= TXM_MODULE_MPU_SHARED_ENTRIES) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* No more entries available. */ + return(TX_NO_MEMORY); + } + + /* Start address must adhere to Cortex-M23 MPU alignment. */ + address = (ULONG) start_address; + if(address != (address & ~(TXM_MODULE_MPU_ALIGNMENT - 1))) + { + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return alignment error. */ + return(TXM_MODULE_ALIGNMENT_ERROR); + } + + /* At this point, we have a valid address. Set up MPU registers. */ + + /* Pick up index into shared memory entries. */ + shared_index = TXM_MODULE_MPU_SHARED_INDEX + module_instance -> txm_module_instance_shared_memory_count; + + /* Set base address register with start address, sanitized attributes and execute never. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_base_address = address | (attributes & TXM_MODULE_ATTRIBUTE_MASK) | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; + + /* Set the limit address (data start + length-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[shared_index].txm_module_mpu_region_limit_address = (address + length-1) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + + /* Keep track of shared memory address and length in module instance. */ + module_instance -> txm_module_instance_shared_memory_address[module_instance -> txm_module_instance_shared_memory_count] = address; + module_instance -> txm_module_instance_shared_memory_length[module_instance -> txm_module_instance_shared_memory_count] = length; + + /* Increment counter. */ + module_instance -> txm_module_instance_shared_memory_count++; + + /* Release the protection mutex. */ + _tx_mutex_put(&_txm_module_manager_mutex); + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c new file mode 100644 index 00000000..974ffebe --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_handler.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + +/* Define a macro that can be used to allocate global variables useful to + store information about the last fault. This macro is defined in + txm_module_port.h and is usually populated in the assembly language + fault handling prior to the code calling _txm_module_manager_memory_fault_handler. */ + +TXM_MODULE_MANAGER_FAULT_INFO + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_handler Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a fault associated with a memory protected */ +/* module. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _tx_thread_terminate Terminate thread */ +/* */ +/* CALLED BY */ +/* */ +/* Fault handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_memory_fault_handler(VOID) +{ + +TXM_MODULE_INSTANCE *module_instance_ptr; +TX_THREAD *thread_ptr; + + /* Pickup the current thread. */ + thread_ptr = _tx_thread_current_ptr; + + /* Initialize the module instance pointer to NULL. */ + module_instance_ptr = TX_NULL; + + /* Is there a thread? */ + if (thread_ptr) + { + /* Pickup the module instance. */ + module_instance_ptr = thread_ptr -> tx_thread_module_instance_ptr; + + /* Terminate the current thread. */ + _tx_thread_terminate(_tx_thread_current_ptr); + } + + /* Determine if there is a user memory fault notification callback. */ + if (_txm_module_manager_fault_notify) + { + /* Yes, call the user's notification memory fault callback. */ + (_txm_module_manager_fault_notify)(thread_ptr, module_instance_ptr); + } +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c new file mode 100644 index 00000000..938e484c --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_memory_fault_notify.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "tx_thread.h" +#include "txm_module.h" + + +/* Define the external user's fault notification callback function pointer. This is + setup via the txm_module_manager_memory_fault_notify API. */ + +extern VOID (*_txm_module_manager_fault_notify)(TX_THREAD *, TXM_MODULE_INSTANCE *); + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_memory_fault_notify Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers an application callback when/if a memory */ +/* fault occurs. The supplied thread is automatically terminated, but */ +/* any other threads in the same module may still execute. */ +/* */ +/* INPUT */ +/* */ +/* notify_function Memory fault notification */ +/* function, NULL disables. */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_memory_fault_notify(VOID (*notify_function)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +{ + /* Setup notification function. */ + _txm_module_manager_fault_notify = notify_function; + + /* Return success. */ + return(TX_SUCCESS); +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c new file mode 100644 index 00000000..faa7551f --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_mm_register_setup Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets up the Cortex-M23 MPU register definitions based */ +/* on the module's memory characteristics. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* */ +/* OUTPUT */ +/* */ +/* MPU settings for the module in module_instance */ +/* */ +/* CALLS */ +/* */ +/* none */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_thread_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) +{ + +ULONG data_size; +ULONG start_stop_stack_size; +ULONG callback_stack_size; + + /* Setup MPU region for kernel mode entry. */ + /* Set base address register to user mode entry function address, which is guaranteed to be at least 32-byte aligned. + Mask address to proper range, inner shareable, read only. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_base_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY; + /* Set the limit address, attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_KERNEL_ENTRY_INDEX].txm_module_mpu_region_limit_address = ((ULONG) _txm_module_manager_user_mode_entry & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of kernel mode entry setup. */ + + + /* Setup MPU region for module code protection. */ + /* Set base address register to module code address, which should be at least 32-byte aligned. + Mask address to proper range, inner shareable, read only. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_code_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_ONLY; + /* Set the limit address (code start + code size-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_CODE_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_code_start + module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_code_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of module code protection. */ + + + /* Setup MPU region for module data protection. */ + /* Set base address register to module data address, which should be at least 32-byte aligned. + Mask address to proper range, inner shareable, read write, execute never. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_base_address = ((ULONG) module_instance -> txm_module_instance_data_start & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INNER_SHAREABLE | TXM_MODULE_ATTRIBUTE_READ_WRITE | TXM_MODULE_ATTRIBUTE_EXECUTE_NEVER; + + /* Adjust the size of the module elements to be aligned to the default alignment. We do this + so that when we partition the allocated memory, we can simply place these regions right beside + each other without having to align their pointers. Note this only works when they all have + the same alignment. */ + + data_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_data_size; + start_stop_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_start_stop_stack_size; + callback_stack_size = module_instance -> txm_module_instance_preamble_ptr -> txm_module_preamble_callback_stack_size; + + data_size = ((data_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + start_stop_stack_size = ((start_stop_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + callback_stack_size = ((callback_stack_size + TXM_MODULE_DATA_ALIGNMENT - 1)/TXM_MODULE_DATA_ALIGNMENT) * TXM_MODULE_DATA_ALIGNMENT; + + /* Update the data size to include thread stacks. */ + data_size = data_size + start_stop_stack_size + callback_stack_size; + + /* Set the limit address (data start + data size-1), attribute index, and enable bit. */ + module_instance -> txm_module_instance_mpu_registers[TXM_MODULE_MPU_DATA_INDEX].txm_module_mpu_region_limit_address = (((ULONG) module_instance -> txm_module_instance_data_start + data_size - 1) & 0xFFFFFFE0) | TXM_MODULE_ATTRIBUTE_INDEX | TXM_MODULE_ATTRIBUTE_REGION_ENABLE; + /* End of module data protection. */ + + /* Remaining MPU entries are disabled for now and can be used for shared memory. */ +} + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_inside_data_check Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the specified object is inside shared */ +/* memory. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Pointer to module instance */ +/* obj_ptr Pointer to the object */ +/* obj_size Size of the object */ +/* */ +/* OUTPUT */ +/* */ +/* Whether the object is inside the shared memory region. */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Module dispatch check functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) +{ + +UINT shared_memory_index; +UINT num_shared_memory_mpu_entries; +ALIGN_TYPE shared_memory_address_start; +ALIGN_TYPE shared_memory_address_end; + + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + + /* Check if the object is inside the module data. */ + if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && + ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) + { + return(TX_TRUE); + } + + /* Check if the object is inside the shared memory. */ + num_shared_memory_mpu_entries = module_instance -> txm_module_instance_shared_memory_count; + for (shared_memory_index = 0; shared_memory_index < num_shared_memory_mpu_entries; shared_memory_index++) + { + + shared_memory_address_start = (ALIGN_TYPE) module_instance -> txm_module_instance_shared_memory_address[shared_memory_index]; + shared_memory_address_end = shared_memory_address_start + module_instance -> txm_module_instance_shared_memory_length[shared_memory_index]; + + if ((obj_ptr >= (ALIGN_TYPE) shared_memory_address_start) && + ((obj_ptr + obj_size) <= (ALIGN_TYPE) shared_memory_address_end)) + { + return(TX_TRUE); + } + } + + return(TX_FALSE); +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c new file mode 100644 index 00000000..ed9f0ea4 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_port_dispatch.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define TX_SOURCE_CODE + +#include "tx_api.h" +#include "txm_module.h" +#include "txm_module_manager_util.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_port_dispatch Cortex-M23 */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function dispatches the module's kernel request based upon the */ +/* ID and parameters specified in the request. */ +/* */ +/* INPUT */ +/* */ +/* module_instance Module pointer */ +/* kernel_request Module's kernel request */ +/* param_0 First parameter */ +/* param_1 Second parameter */ +/* param_2 Third parameter */ +/* */ +/* OUTPUT */ +/* */ +/* status Completion status */ +/* */ +/* CALLS */ +/* */ +/* Port-specific ThreadX API Calls */ +/* */ +/* CALLED BY */ +/* */ +/* _txm_module_manager_kernel_dispatch */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +ALIGN_TYPE _txm_module_manager_port_dispatch(TXM_MODULE_INSTANCE *module_instance, ULONG kernel_request, ALIGN_TYPE param_0, ALIGN_TYPE param_1, ALIGN_TYPE param_2) +{ + +ALIGN_TYPE return_value = TX_NOT_AVAILABLE; + + switch(kernel_request) + { + case TXM_THREAD_SECURE_STACK_ALLOCATE_CALL: + { + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_allocate( + (TX_THREAD *) param_0, + (ULONG) param_1 + ); + break; + } + + case TXM_THREAD_SECURE_STACK_FREE_CALL: + { + if (module_instance -> txm_module_instance_property_flags & TXM_MODULE_MEMORY_PROTECTION) + { + if (!TXM_MODULE_MANAGER_PARAM_CHECK_OBJECT_FOR_USE(module_instance, param_0, sizeof(TX_THREAD))) + return(TXM_MODULE_INVALID_MEMORY); + } + + return_value = (ALIGN_TYPE) _txe_thread_secure_stack_free( + (TX_THREAD *) param_0 + ); + break; + } + + default: + { + /* Unhandled kernel request, return an error! */ + break; + } + } + + return(return_value); +} diff --git a/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s new file mode 100644 index 00000000..4eca3c57 --- /dev/null +++ b/ports_module/cortex_m23/iar/module_manager/src/txm_module_manager_thread_stack_build.s @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** ThreadX Component */ +/** */ +/** Module Manager */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + SECTION `.text`:CODE:NOROOT(2) + THUMB +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _txm_module_manager_thread_stack_build Cortex-M23/IAR */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Scott Larson, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function builds a stack frame on the supplied thread's stack. */ +/* The stack frame results in a fake interrupt return to the supplied */ +/* function pointer. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Pointer to thread */ +/* function_ptr Pointer to shell function */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _tx_thread_create Create thread service */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 04-02-2021 Scott Larson Initial Version 6.1.6 */ +/* */ +/**************************************************************************/ +// VOID _txm_module_manager_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(TX_THREAD *, TXM_MODULE_INSTANCE *)) +// { + PUBLIC _txm_module_manager_thread_stack_build +_txm_module_manager_thread_stack_build: + + /* Build a fake interrupt frame. The form of the fake interrupt stack + on the Cortex-M should look like the following after it is built: + + Stack Top: + LR Interrupted LR (LR at time of PENDSV) + r8 Initial value for r8 + r9 Initial value for r9 + r10 Initial value for r10 + r11 Initial value for r11 + r4 Initial value for r4 + r5 Initial value for r5 + r6 Initial value for r6 + r7 Initial value for r7 + r0 Initial value for r0 (Hardware stack starts here!!) + r1 Initial value for r1 + r2 Initial value for r2 + r3 Initial value for r3 + r12 Initial value for r12 + lr Initial value for lr + pc Initial value for pc + xPSR Initial value for xPSR + + Stack Bottom: (higher memory address) */ + + LDR r2, [r0, #16] // Pickup end of stack area + MOVW r3, #0x7 // + BICS r2, r2, r3 // Align frame for 8-byte alignment + SUBS r2, r2, #68 // Subtract frame size +#ifdef TX_SINGLE_MODE_SECURE + LDR r3, =0xFFFFFFFD // Build initial LR value for secure mode +#else + LDR r3, =0xFFFFFFBC // Build initial LR value to return to non-secure PSP +#endif + STR r3, [r2, #0] // Save on the stack + + /* Actually build the stack frame. */ + + MOVW r3, #0 // Build initial register value + STR r3, [r2, #4] // Store initial r8 + STR r3, [r2, #12] // Store initial r10 + STR r3, [r2, #16] // Store initial r11 + STR r3, [r2, #20] // Store initial r4 + STR r3, [r2, #24] // Store initial r5 + STR r3, [r2, #28] // Store initial r6 + STR r3, [r2, #32] // Store initial r7 + + /* Hardware stack follows. */ + + STR r0, [r2, #36] // Store initial r0, which is the thread control block + + LDR r3, [r0, #8] // Pickup thread entry info pointer,which is in the stack pointer position of the thread control block. + // It was setup in the txm_module_manager_thread_create function. It will be overwritten later in this + // function with the actual, initial stack pointer. + STR r3, [r2, #40] // Store initial r1, which is the module entry information. + LDR r3, [r3, #8] // Pickup data base register from the module information + STR r3, [r2, #8] // Store initial r9 (data base register) + MOVW r3, #0 // Clear r3 again + + STR r3, [r2, #44] // Store initial r2 + STR r3, [r2, #48] // Store initial r3 + STR r3, [r2, #52] // Store initial r12 + LDR r3, =0xFFFFFFFF // Poison EXC_RETURN value + STR r3, [r2, #56] // Store initial lr + STR r1, [r2, #60] // Store initial pc + LDR r3, =0x01000000 // Only T-bit need be set + STR r3, [r2, #64] // Store initial xPSR + + /* Setup stack pointer. */ + // thread_ptr -> tx_thread_stack_ptr = r2; + + STR r2, [r0, #8] // Save stack pointer in thread's control block + BX lr // Return to caller +// } + END diff --git a/ports_module/cortex_m33/ac6/inc/tx_port.h b/ports_module/cortex_m33/ac6/inc/tx_port.h index c0b14d97..c084ba00 100644 --- a/ports_module/cortex_m33/ac6/inc/tx_port.h +++ b/ports_module/cortex_m33/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-M33/AC6 */ -/* 6.1.3 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -47,7 +47,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 09-30-2020 Scott Larson Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -538,7 +541,7 @@ VOID _tx_thread_interrupt_restore(UIN #else -#define TX_INTERRUPT_SAVE_AREA unsigned int was_masked; +#define TX_INTERRUPT_SAVE_AREA UINT was_masked; #define TX_DISABLE was_masked = __disable_irq(); #define TX_RESTORE if (was_masked == 0) __enable_irq(); @@ -567,7 +570,7 @@ unsigned int was_masked; #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M33/AC6 Version 6.1.6 *"; #else #ifdef TX_MISRA_ENABLE extern CHAR _tx_version_id[100]; diff --git a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S index 97c313b4..9a65319b 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/ac6/module_manager/src/tx_thread_schedule.S @@ -26,7 +26,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/MPU/AC6 */ -/* 6.1.3 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -59,6 +59,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments and fixed */ +/* MPU region configuration, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -379,6 +382,8 @@ _skip_secure_restore: LDR r1, =0xE000ED9C // Build address of MPU base register // Use alias registers to quickly load MPU + LDR r2, =0xE000ED98 // Get region register + STR r3, [r2] // Set region to 0 ADD r0, r0, #0x64 // Build address of MPU register start in thread control block LDM r0!, {r2-r9} // Load first four MPU regions STM r1, {r2-r9} // Store first four MPU regions diff --git a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c index a38602d9..4bd99c30 100644 --- a/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/ac6/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,8 +29,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/MPU */ -/* 6.1.3 */ +/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments and check */ +/* for overflow, */ +/* resulting 6.1.6 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -120,8 +123,8 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/MPU/AC6 */ -/* 6.1.3 */ +/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -153,7 +156,9 @@ ULONG callback_stack_size; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -164,6 +169,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/gnu/inc/tx_port.h b/ports_module/cortex_m33/gnu/inc/tx_port.h index 54b785b9..3b336daa 100644 --- a/ports_module/cortex_m33/gnu/inc/tx_port.h +++ b/ports_module/cortex_m33/gnu/inc/tx_port.h @@ -648,7 +648,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupt(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S index 179c80b8..f5c6224f 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S +++ b/ports_module/cortex_m33/gnu/module_manager/src/tx_thread_schedule.S @@ -29,7 +29,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/MPU/GNU */ -/* 6.1.5 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -62,6 +62,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 04-02-2021 Scott Larson Modified comments and fixed */ +/* MPU region configuration, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -382,6 +385,8 @@ _skip_secure_restore: LDR r1, =0xE000ED9C // Build address of MPU base register // Use alias registers to quickly load MPU + LDR r2, =0xE000ED98 // Get region register + STR r3, [r2] // Set region to 0 ADD r0, r0, #0x64 // Build address of MPU register start in thread control block LDM r0!, {r2-r9} // Load first four MPU regions STM r1, {r2-r9} // Store first four MPU regions diff --git a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c index 3670dabb..4bd99c30 100644 --- a/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/gnu/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,8 +29,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/MPU */ -/* 6.1.5 */ +/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments and check */ +/* for overflow, */ +/* resulting 6.1.6 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -120,8 +123,8 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/MPU */ -/* 6.1.5 */ +/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -153,7 +156,9 @@ ULONG callback_stack_size; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -164,6 +169,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_module/cortex_m33/iar/inc/tx_port.h b/ports_module/cortex_m33/iar/inc/tx_port.h index 1a2730d2..5f592d5b 100644 --- a/ports_module/cortex_m33/iar/inc/tx_port.h +++ b/ports_module/cortex_m33/iar/inc/tx_port.h @@ -648,7 +648,7 @@ unsigned int interrupt_save; } -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = __disable_interrupt(); #define TX_RESTORE __restore_interrupt(interrupt_save); diff --git a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s index dc41aca1..09419cf0 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s +++ b/ports_module/cortex_m33/iar/module_manager/src/tx_thread_schedule.s @@ -42,7 +42,7 @@ /* FUNCTION RELEASE */ /* */ /* _tx_thread_schedule Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -75,6 +75,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 04-02-2021 Scott Larson Modified comments and fixed */ +/* MPU region configuration, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ // VOID _tx_thread_schedule(VOID) @@ -383,6 +386,8 @@ _skip_secure_restore: LDR r1, =0xE000ED9C // Build address of MPU base register // Use alias registers to quickly load MPU + LDR r2, =0xE000ED98 // Get region register + STR r3, [r2] // Set region to 0 ADD r0, r0, #0x64 // Build address of MPU register start in thread control block LDM r0!, {r2-r9} // Load first four MPU regions STM r1, {r2-r9} // Store first four MPU regions diff --git a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c index 0e844131..4bd99c30 100644 --- a/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c +++ b/ports_module/cortex_m33/iar/module_manager/src/txm_module_manager_mm_register_setup.c @@ -29,8 +29,8 @@ /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_mm_register_setup Cortex-M33/MPU */ -/* 6.1.5 */ +/* _txm_module_manager_mm_register_setup Cortex-M33/Generic */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -60,7 +60,10 @@ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments and check */ +/* for overflow, */ +/* resulting 6.1.6 */ /* */ /**************************************************************************/ VOID _txm_module_manager_mm_register_setup(TXM_MODULE_INSTANCE *module_instance) @@ -120,8 +123,8 @@ ULONG callback_stack_size; /* */ /* FUNCTION RELEASE */ /* */ -/* _txm_module_manager_inside_data_check Cortex-M33/MPU/IAR */ -/* 6.1.5 */ +/* _txm_module_manager_inside_data_check Cortex-M33/Generic */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* Scott Larson, Microsoft Corporation */ @@ -153,7 +156,9 @@ ULONG callback_stack_size; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 Scott Larson Initial Version 6.1.5 */ +/* 12-31-2020 Scott Larson Initial Version 6.1.3 */ +/* 04-02-2021 Scott Larson Modified comments, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ UINT _txm_module_manager_inside_data_check(TXM_MODULE_INSTANCE *module_instance, ALIGN_TYPE obj_ptr, UINT obj_size) @@ -164,6 +169,12 @@ UINT num_shared_memory_mpu_entries; ALIGN_TYPE shared_memory_address_start; ALIGN_TYPE shared_memory_address_end; + /* Check for overflow. */ + if ((obj_ptr) > ((obj_ptr) + (obj_size))) + { + return(TX_FALSE); + } + /* Check if the object is inside the module data. */ if ((obj_ptr >= (ALIGN_TYPE) module_instance -> txm_module_instance_data_start) && ((obj_ptr + obj_size) <= ((ALIGN_TYPE) module_instance -> txm_module_instance_data_end + 1))) diff --git a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h index 8b60f7e7..09bca6e7 100644 --- a/ports_smp/arc_hs_smp/metaware/inc/tx_port.h +++ b/ports_smp/arc_hs_smp/metaware/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/ARC_HS/MetaWare */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -378,7 +381,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -401,7 +404,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/ARC_HS/MetaWare Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt index 60271d41..23d477fa 100644 --- a/ports_smp/arc_hs_smp/metaware/readme_threadx.txt +++ b/ports_smp/arc_hs_smp/metaware/readme_threadx.txt @@ -195,6 +195,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 for ARC HS using MetaWare tools. diff --git a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h index ea59fe6c..e9061587 100644 --- a/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A35-SMP/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -384,7 +387,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -418,7 +421,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/AC6 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt index a865af42..8c35001b 100644 --- a/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt +++ b/ports_smp/cortex_a35_smp/ac6/readme_threadx.txt @@ -244,6 +244,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using AC6 tools. diff --git a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h index e9a401d9..8b902175 100644 --- a/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a35_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A35-SMP/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -384,7 +387,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -418,7 +421,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt index f1842fc7..63010670 100644 --- a/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a35_smp/gnu/readme_threadx.txt @@ -244,6 +244,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX SMP: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A35 using ARM GCC and DS tools. diff --git a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h index d3881298..870accaa 100644 --- a/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A5/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -364,7 +367,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -394,7 +397,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt index 91cb43f4..4b11e210 100644 --- a/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a5_smp/ac5/readme_threadx.txt @@ -351,6 +351,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using AC5 tools. diff --git a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h index f5324045..879775d2 100644 --- a/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A5/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -367,7 +370,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -397,7 +400,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A5/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt index 4495a618..a4f0e412 100644 --- a/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a5_smp/gnu/readme_threadx.txt @@ -332,7 +332,10 @@ before their use and restored after. For generic code revision information, please refer to the readme_threadx_generic.txt file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: - + +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5 using GNU tools. diff --git a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h index 33e78618..a2191562 100644 --- a/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/ac6/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x-SMP/AC6 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -384,7 +387,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -418,7 +421,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.1 *"; + "Copyright (c) 1996-2019 Express Logic Inc. * ThreadX Cortex-A5x-SMP/AC6 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt index e41ff303..baec207f 100644 --- a/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/ac6/readme_threadx.txt @@ -247,6 +247,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09/30/2020 Initial ThreadX 6.1 version for Cortex-A5x using AC6 tools. diff --git a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h index 0860e74a..ecf55fac 100644 --- a/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x-SMP/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -384,7 +387,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -418,7 +421,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt index 9dbdcb9e..69fa3be4 100644 --- a/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/gnu/readme_threadx.txt @@ -247,6 +247,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX SMP: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A5x using ARM GCC and DS-5 tools. diff --git a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h index f13360ac..50896e69 100644 --- a/ports_smp/cortex_a5x_smp/green/inc/tx_port.h +++ b/ports_smp/cortex_a5x_smp/green/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h Cortex-A5x-SMP/GHS */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -404,7 +407,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -438,7 +441,7 @@ VOID tx_thread_fp_disable(VOID); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GHS Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A5x-SMP/GHS Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a5x_smp/green/readme_threadx.txt b/ports_smp/cortex_a5x_smp/green/readme_threadx.txt index be70d786..e2cb3b78 100644 --- a/ports_smp/cortex_a5x_smp/green/readme_threadx.txt +++ b/ports_smp/cortex_a5x_smp/green/readme_threadx.txt @@ -254,6 +254,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX SMP: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09/30/2020 Initial ThreadX SMP version 6.1 of Cortex-A5x/Green Hills port. diff --git a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h index 57109ab0..6e01395c 100644 --- a/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A7/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -364,7 +367,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -394,7 +397,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/AC5 Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt index 3dcb6dca..fb2a0b26 100644 --- a/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a7_smp/ac5/readme_threadx.txt @@ -351,6 +351,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using AC5 tools. diff --git a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h index 2498cdd3..27bcbc38 100644 --- a/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a7_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A7/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -362,7 +365,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -392,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A7/GNU Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt index ad198141..265a3735 100644 --- a/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a7_smp/gnu/readme_threadx.txt @@ -333,6 +333,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A7 using GNU tools. diff --git a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h index b6c26093..69d12cd5 100644 --- a/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/ac5/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A9/AC5 */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -369,7 +372,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -399,7 +402,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/AC5 Version Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt index 06b2e4e6..1c3bfe86 100644 --- a/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt +++ b/ports_smp/cortex_a9_smp/ac5/readme_threadx.txt @@ -224,7 +224,10 @@ void tx_thread_vfp_disable(void); For generic code revision information, please refer to the readme_threadx_generic.txt file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: - + +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using AC5 tools. diff --git a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h index ab3f9cf9..10846ab1 100644 --- a/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h +++ b/ports_smp/cortex_a9_smp/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Cortex-A9/GNU */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -362,7 +365,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT interrupt_save; #define TX_DISABLE interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(interrupt_save); @@ -392,7 +395,7 @@ void tx_thread_vfp_disable(void); #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/GNU Version Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Cortex-A9/GNU Version Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt b/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt index 26131c9b..d385d559 100644 --- a/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt +++ b/ports_smp/cortex_a9_smp/gnu/readme_threadx.txt @@ -227,7 +227,10 @@ void tx_thread_vfp_disable(void); For generic code revision information, please refer to the readme_threadx_generic.txt file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: - + +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX 6.1 version for Cortex-A9 using GNU tools. diff --git a/ports_smp/linux/gnu/inc/tx_port.h b/ports_smp/linux/gnu/inc/tx_port.h index 7db203d9..37535d9e 100644 --- a/ports_smp/linux/gnu/inc/tx_port.h +++ b/ports_smp/linux/gnu/inc/tx_port.h @@ -26,7 +26,7 @@ /* PORT SPECIFIC C INFORMATION RELEASE */ /* */ /* tx_port.h SMP/Linux/GCC */ -/* 6.1 */ +/* 6.1.6 */ /* */ /* AUTHOR */ /* */ @@ -48,6 +48,9 @@ /* DATE NAME DESCRIPTION */ /* */ /* 09-30-2020 William E. Lamie Initial Version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* macro definition, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ @@ -600,7 +603,7 @@ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG su is used to define a local function save area for the disable and restore macros. */ -#define TX_INTERRUPT_SAVE_AREA unsigned int tx_interrupt_save; +#define TX_INTERRUPT_SAVE_AREA UINT tx_interrupt_save; #define TX_DISABLE tx_interrupt_save = _tx_thread_smp_protect(); #define TX_RESTORE _tx_thread_smp_unprotect(tx_interrupt_save); @@ -628,7 +631,7 @@ void _tx_thread_smp_debug_entry_insert(ULONG id, ULONG su #ifdef TX_THREAD_INIT CHAR _tx_version_id[] = - "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Linux/gcc Version 6.1 *"; + "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX SMP/Linux/gcc Version 6.1.6 *"; #else extern CHAR _tx_version_id[]; #endif diff --git a/ports_smp/linux/gnu/readme_threadx.txt b/ports_smp/linux/gnu/readme_threadx.txt index 646b8714..6f41a356 100644 --- a/ports_smp/linux/gnu/readme_threadx.txt +++ b/ports_smp/linux/gnu/readme_threadx.txt @@ -145,6 +145,9 @@ For generic code revision information, please refer to the readme_threadx_generi file, which is included in your distribution. The following details the revision information associated with this specific port of ThreadX: +04-02-2021 Release 6.1.6 changes: + tx_port.h Updated macro definition + 09-30-2020 Initial ThreadX SMP 6.1 version for Linux using GNU GCC tools. diff --git a/utility/low_power/tx_low_power.c b/utility/low_power/tx_low_power.c index 18f2d08b..8c9c95bd 100644 --- a/utility/low_power/tx_low_power.c +++ b/utility/low_power/tx_low_power.c @@ -41,7 +41,7 @@ UINT tx_low_power_entered; /* FUNCTION RELEASE */ /* */ /* tx_low_power_enter PORTABLE C */ -/* 6.1.5 */ +/* 6.1.6 */ /* AUTHOR */ /* */ /* William E. Lamie, Microsoft Corporation */ @@ -76,16 +76,21 @@ UINT tx_low_power_entered; /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 03-02-2021 William E. Lamie Initial Version 6.1.5 */ +/* 03-02-2021 William E. Lamie Initial Version 6.1.5 */ +/* 04-02-2021 Scott Larson Modified comments and fixed */ +/* compiler warning, */ +/* resulting in version 6.1.6 */ /* */ /**************************************************************************/ VOID tx_low_power_enter(VOID) { TX_INTERRUPT_SAVE_AREA + +#ifdef TX_LOW_POWER_TIMER_SETUP ULONG tx_low_power_next_expiration; /* The next timer experation (units of ThreadX timer ticks). */ ULONG timers_active; - +#endif /* Disable interrupts while we prepare for low power mode. */ TX_DISABLE