forked from Imagelibrary/seL4
d82b9f0434
This is a shortcut for dealing with the inline assembly inside to prevent the modifies analysis from picking up every part of the state. For any future binary correctness analysis, this will need to be removed, and instead an appeal made to inline assembly being unable to modify the heap. Signed-off-by: Rafal Kolanski <rafal.kolanski@data61.csiro.au>
305 lines
9.6 KiB
C
305 lines
9.6 KiB
C
/*
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* Copyright 2019, DornerWorks
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* Copyright 2019, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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* ABN 41 687 119 230.
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*
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* This software may be distributed and modified according to the terms of
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* the BSD 2-Clause license. Note that NO WARRANTY is provided.
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* See "LICENSE_BSD2.txt" for details.
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*
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* @TAG(DATA61_DORNERWORKS_BSD)
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*/
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/*
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* Arm Generic Interrupt Controller v3
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*/
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#ifndef ARCH_MACHINE_GIC_3_H
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#define ARCH_MACHINE_GIC_3_H
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/* tell the kernel we have the set trigger feature */
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#define HAVE_SET_TRIGGER 1
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#include <stdint.h>
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#include <util.h>
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#include <linker.h>
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#include <mode/smp/smp.h>
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#include <model/statedata.h>
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#include <armv/machine.h>
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#include "gic_common.h"
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#define GIC_PRI_LOWEST 0xf0
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#define GIC_PRI_IRQ 0xa0
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#define GIC_PRI_HIGHEST 0x80 /* Higher priorities belong to Secure-World */
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#define IRQ_MASK MASK(16u)
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/* Register bits */
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#define GICD_CTL_ENABLE 0x1
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#define GICD_CTLR_RWP BIT(31)
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#define GICD_CTLR_ARE_NS BIT(4)
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#define GICD_CTLR_ENABLE_G1NS BIT(1)
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#define GICD_CTLR_ENABLE_G0 BIT(0)
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#define GICD_IROUTER_SPI_MODE_ANY BIT(31)
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#define GICD_TYPE_LINESNR 0x01f
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#define GICC_SRE_EL1_SRE BIT(0)
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#define GICR_WAKER_ProcessorSleep BIT(1)
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#define GICR_WAKER_ChildrenAsleep BIT(2)
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#define GICC_CTLR_EL1_EOImode_drop BIT(1)
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#define DEFAULT_PMR_VALUE 0xff
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/* System registers for GIC CPU interface */
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#ifdef CONFIG_ARCH_AARCH64
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#define ICC_IAR1_EL1 "S3_0_C12_C12_0"
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#define ICC_EOIR1_EL1 "S3_0_C12_C12_1"
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#define ICC_HPPIR1_EL1 "S3_0_C12_C12_2"
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#define ICC_BPR1_EL1 "S3_0_C12_C12_3"
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#define ICC_DIR_EL1 "S3_0_C12_C11_1"
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#define ICC_PMR_EL1 "S3_0_C4_C6_0"
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#define ICC_CTLR_EL1 "S3_0_C12_C12_4"
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#define ICC_IGRPEN1_EL1 "S3_0_C12_C12_7"
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#define ICC_SRE_EL1 "S3_0_C12_C12_5"
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#define MPIDR "mpidr_el1"
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#else
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#define ICC_IAR1_EL1 " p15, 0, %0, c12, c12, 0"
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#define ICC_EOIR1_EL1 " p15, 0, %0, c12, c12, 1"
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#define ICC_HPPIR1_EL1 " p15, 0, %0, c12, c12, 2"
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#define ICC_BPR1_EL1 " p15, 0, %0, c12, c12, 3"
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#define ICC_DIR_EL1 " p15, 0, %0, c12, c11, 1"
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#define ICC_PMR_EL1 " p15, 0, %0, c4, c6, 0"
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#define ICC_CTLR_EL1 " p15, 0, %0, c12, c12, 4"
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#define ICC_IGRPEN1_EL1 " p15, 0, %0, c12, c12, 7"
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#define ICC_SRE_EL1 " p15, 0, %0, c12, c12, 5"
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#define MPIDR " p15, 0, %0, c0, c0, 5"
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#endif
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/* Memory map for GIC distributor */
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struct gic_dist_map {
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uint32_t ctlr; /* 0x0000 */
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uint32_t typer; /* 0x0004 */
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uint32_t iidr; /* 0x0008 */
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uint32_t res0; /* 0x000C */
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uint32_t statusr; /* 0x0010 */
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uint32_t res1[11]; /* [0x0014, 0x0040) */
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uint32_t setspi_nsr; /* 0x0040 */
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uint32_t res2; /* 0x0044 */
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uint32_t clrspi_nsr; /* 0x0048 */
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uint32_t res3; /* 0x004C */
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uint32_t setspi_sr; /* 0x0050 */
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uint32_t res4; /* 0x0054 */
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uint32_t clrspi_sr; /* 0x0058 */
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uint32_t res5[9]; /* [0x005C, 0x0080) */
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uint32_t igrouprn[32]; /* [0x0080, 0x0100) */
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uint32_t isenablern[32]; /* [0x100, 0x180) */
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uint32_t icenablern[32]; /* [0x180, 0x200) */
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uint32_t ispendrn[32]; /* [0x200, 0x280) */
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uint32_t icpendrn[32]; /* [0x280, 0x300) */
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uint32_t isactivern[32]; /* [0x300, 0x380) */
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uint32_t icactivern[32]; /* [0x380, 0x400) */
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uint32_t ipriorityrn[255]; /* [0x400, 0x7FC) */
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uint32_t res6; /* 0x7FC */
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uint32_t itargetsrn[254]; /* [0x800, 0xBF8) */
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uint32_t res7[2]; /* 0xBF8 */
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uint32_t icfgrn[64]; /* [0xC00, 0xD00) */
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uint32_t igrpmodrn[64]; /* [0xD00, 0xE00) */
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uint32_t nsacrn[64]; /* [0xE00, 0xF00) */
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uint32_t sgir; /* 0xF00 */
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uint32_t res8[3]; /* [0xF04, 0xF10) */
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uint32_t cpendsgirn[4]; /* [0xF10, 0xF20) */
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uint32_t spendsgirn[4]; /* [0xF20, 0xF30) */
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uint32_t res9[5235]; /* [0x0F30, 0x6100) */
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uint64_t iroutern[960]; /* [0x6100, 0x7F00) */
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};
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/* Memory map for GIC Redistributor Registers for control and physical LPI's */
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struct gic_rdist_map { /* Starting */
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uint32_t ctlr; /* 0x0000 */
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uint32_t iidr; /* 0x0004 */
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uint64_t typer; /* 0x0008 */
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uint32_t statusr; /* 0x0010 */
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uint32_t waker; /* 0x0014 */
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uint32_t res0[10]; /* 0x0018 */
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uint64_t setlpir; /* 0x0040 */
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uint64_t clrlpir; /* 0x0048 */
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uint32_t res1[8]; /* 0x0050 */
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uint64_t propbaser; /* 0x0070 */
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uint64_t pendbaser; /* 0x0078 */
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uint32_t res2[8]; /* 0x0080 */
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uint64_t invlpir; /* 0x00a0 */
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uint32_t res3[2]; /* 0x00a8 */
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uint64_t invallr; /* 0x00b0 */
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uint32_t res4[2]; /* 0x00b8 */
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uint32_t syncr; /* 0x00c0 */
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};
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/* Memory map for the GIC Redistributor Registers for the SGI and PPI's */
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struct gic_rdist_sgi_ppi_map { /* Starting */
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uint32_t res0[32]; /* 0x0000 */
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uint32_t igroupr0; /* 0x0080 */
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uint32_t res1[31]; /* 0x0084 */
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uint32_t isenabler0; /* 0x0100 */
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uint32_t res2[31]; /* 0x0104 */
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uint32_t icenabler0; /* 0x0180 */
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uint32_t res3[31]; /* 0x0184 */
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uint32_t ispendr0; /* 0x0200 */
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uint32_t res4[31]; /* 0x0204 */
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uint32_t icpendr0; /* 0x0280 */
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uint32_t res5[31]; /* 0x0284 */
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uint32_t isactiver0; /* 0x0300 */
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uint32_t res6[31]; /* 0x0304 */
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uint32_t icactiver0; /* 0x0380 */
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uint32_t res7[31]; /* 0x0384 */
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uint32_t ipriorityrn[8]; /* 0x0400 */
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uint32_t res8[504]; /* 0x0420 */
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uint32_t icfgr0; /* 0x0C00 */
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uint32_t icfgr1; /* 0x0C04 */
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uint32_t res9[62]; /* 0x0C08 */
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uint32_t igrpmodr0; /* 0x0D00*/
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uint32_t res10[63]; /* 0x0D04 */
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uint32_t nsacr; /* 0x0E00 */
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};
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extern volatile struct gic_dist_map *const gic_dist;
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extern volatile struct gic_rdist_map *gic_rdist_map[CONFIG_MAX_NUM_NODES];
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extern volatile struct gic_rdist_sgi_ppi_map *gic_rdist_sgi_ppi_map[CONFIG_MAX_NUM_NODES];
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/* Helpers */
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static inline int is_irq_edge_triggered(irq_t irq)
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{
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uint32_t icfgr = 0;
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int word = irq >> 4;
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int bit = ((irq & 0xf) * 2);
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if (HW_IRQ_IS_SGI(irq)) {
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return 0;
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}
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if (HW_IRQ_IS_PPI(irq)) {
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icfgr = gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icfgr1;
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} else {
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icfgr = gic_dist->icfgrn[word];
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}
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return !!(icfgr & BIT(bit + 1));
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}
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static inline void gic_pending_clr(irq_t irq)
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{
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int word = IRQ_REG(irq);
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int bit = IRQ_BIT(irq);
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/* Using |= here is detrimental to your health */
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/* Applicable for SPI and PPIs */
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if (irq < SPI_START) {
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gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icpendr0 = BIT(bit);
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} else {
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gic_dist->icpendrn[word] = BIT(bit);
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}
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}
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static inline void gic_enable_clr(irq_t irq)
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{
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int word = IRQ_REG(irq);
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int bit = IRQ_BIT(irq);
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/* Using |= here is detrimental to your health */
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if (irq < SPI_START) {
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gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->icenabler0 = BIT(bit);
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} else {
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gic_dist->icenablern[word] = BIT(bit);
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}
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}
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static inline void gic_enable_set(irq_t irq)
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{
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int word = IRQ_REG(irq);
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int bit = IRQ_BIT(irq);
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if (irq < SPI_START) {
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gic_rdist_sgi_ppi_map[CURRENT_CPU_INDEX()]->isenabler0 = BIT(bit);
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} else {
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gic_dist->isenablern[word] = BIT(bit);
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}
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}
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static inline interrupt_t getActiveIRQ(void)
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{
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uint32_t irq;
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if (!IS_IRQ_VALID(active_irq[CURRENT_CPU_INDEX()])) {
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uint32_t val = 0;
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SYSTEM_READ_WORD(ICC_IAR1_EL1, val);
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active_irq[CURRENT_CPU_INDEX()] = val;
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}
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if (IS_IRQ_VALID(active_irq[CURRENT_CPU_INDEX()])) {
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irq = CORE_IRQ_TO_IDX(CURRENT_CPU_INDEX(), active_irq[CURRENT_CPU_INDEX()] & IRQ_MASK);
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} else {
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irq = irqInvalid;
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}
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return irq;
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}
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/*
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* GIC has 4 states:
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* seL4 expects two states: active->inactive.
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* We ignore the active state in GIC to conform
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*/
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/** MODIFIES: phantom_machine_state */
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/** DONT_TRANSLATE */
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static inline bool_t isIRQPending(void)
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{
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uint32_t val = 0;
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/* Check for pending IRQs in group 1: ICC_HPPIR1_EL1 */
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SYSTEM_READ_WORD(ICC_HPPIR1_EL1, val);
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return IS_IRQ_VALID(val);
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}
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static inline void maskInterrupt(bool_t disable, interrupt_t irq)
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{
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#if defined ENABLE_SMP_SUPPORT
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assert(!(IRQ_IS_PPI(irq)) || (IDX_TO_CORE(irq) == getCurrentCPUIndex()));
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#endif
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if (disable) {
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gic_enable_clr(IDX_TO_IRQ(irq));
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} else {
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gic_enable_set(IDX_TO_IRQ(irq));
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}
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}
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static inline void ackInterrupt(irq_t irq)
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{
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irq_t hw_irq = IDX_TO_IRQ(irq);
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assert(IS_IRQ_VALID(active_irq[CURRENT_CPU_INDEX()]) && (active_irq[CURRENT_CPU_INDEX()] & IRQ_MASK) == hw_irq);
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if (is_irq_edge_triggered(hw_irq)) {
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gic_pending_clr(hw_irq);
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}
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/* Set End of Interrupt for active IRQ: ICC_EOIR1_EL1 */
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SYSTEM_WRITE_WORD(ICC_EOIR1_EL1, active_irq[CURRENT_CPU_INDEX()]);
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active_irq[CURRENT_CPU_INDEX()] = IRQ_NONE;
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}
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#ifdef ENABLE_SMP_SUPPORT
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void ipiBroadcast(irq_t irq, bool_t includeSelfCPU);
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void ipi_send_target(irq_t irq, word_t cpuTargetList);
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void setIRQTarget(irq_t irq, seL4_Word target);
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#endif /* ENABLE_SMP_SUPPORT */
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#endif /* ARCH_MACHINE_GIC_3_H */
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