forked from Imagelibrary/seL4
119 lines
3.3 KiB
Plaintext
119 lines
3.3 KiB
Plaintext
// Copyright 2022 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Nicole Narr <narrn@student.ethz.ch>
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// Christopher Reinwardt <creinwar@student.ethz.ch>
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// Axel Vanoni <axvanoni@student.ethz.ch>
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "eth,cheshire-dev";
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model = "eth,cheshire";
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chosen {
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console = "/soc/serial@3002000";
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stdout-path = "/soc/serial@3002000:115200";
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linux,initrd-start = <0x84000000>;
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linux,initrd-end = <0x85600000>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>; // 1 MHz
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CPU0: cpu@0 {
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device_type = "cpu";
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status = "okay";
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compatible = "eth,cheshire", "riscv";
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clock-frequency = <50000000>; // 50 MHz
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riscv,isa = "rv64imafdch";
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mmu-type = "riscv,sv39";
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tlb-split;
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reg = <0>;
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CPU0_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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soc: soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "eth,cheshire-bare-soc", "simple-bus";
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ranges;
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debug@0 {
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compatible = "riscv,debug-013";
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reg-names = "control";
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reg = <0x0 0x0 0x0 0x1000>;
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};
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axi_llc@3001000 {
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compatible = "eth,axi-llc";
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reg = <0x0 0x3001000 0x0 0x5000>;
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};
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ddr_link: memory-controller@3006000 {
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compatible = "eth,ddr-link";
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reg = <0x0 0x3006000 0x0 0x1000>;
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};
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serial@3002000 {
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compatible = "ns16550a";
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clock-frequency = <50000000>; // 50 MHz
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current-speed = <115200>;
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interrupt-parent = <&PLIC0>;
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interrupts = <1>;
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reg = <0x0 0x3002000 0x0 0x1000>;
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reg-shift = <2>; // regs are spaced on 32 bit boundary
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reg-io-width = <4>; // only 32-bit access are supported
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};
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i2c@3003000 {
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compatible = "eth,i2c";
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interrupt-parent = <&PLIC0>;
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interrupts = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 16>;
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reg = <0x0 0x3003000 0x0 0x1000>;
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};
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spi@3004000 {
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compatible = "opentitan,spi-host", "lowrisc,spi";
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interrupt-parent = <&PLIC0>;
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interrupts = <17 18>;
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reg = <0x0 0x3004000 0x0 0x1000>;
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clock-frequency = <50000000>;
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max-frequency = <25000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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mmc@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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spi-max-frequency = <25000000>;
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voltage-ranges = <3300 3300>;
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disable-wp;
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};
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};
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vga@3007000 {
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compatible = "eth,axi-vga";
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reg = <0x0 0x3007000 0x0 0x1000>;
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};
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clint@2040000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7>;
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reg-names = "control";
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reg = <0x0 0x2040000 0x0 0x040000>;
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};
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PLIC0: interrupt-controller@4000000 {
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compatible = "riscv,plic0";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
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riscv,max-priority = <7>;
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riscv,ndev = <51>;
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reg = <0x0 0x4000000 0x0 0x4000000>;
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};
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};
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};
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