forked from Imagelibrary/seL4
79da079239
This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
127 lines
3.7 KiB
Plaintext
127 lines
3.7 KiB
Plaintext
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2012-2014, The Regents of the University of California
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* (Regents). All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Regents nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
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* SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
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* OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED
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* HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE
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* MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-dev";
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model = "freechips,rocketchip-unknown";
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chosen {
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};
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L13: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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L5: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <16384>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <16384>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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next-level-cache = <&L6>;
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reg = <0>;
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riscv,isa = "rv64imafdc";
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status = "okay";
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timebase-frequency = <1000000>;
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tlb-split;
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L3: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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L6: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>;
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};
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L12: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
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ranges;
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L10: blkdev-controller@10015000 {
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compatible = "ucbbar,blkdev";
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interrupt-parent = <&L0>;
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interrupts = <3>;
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reg = <0x10015000 0x1000>;
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reg-names = "control";
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};
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L1: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&L3 3 &L3 7>;
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reg = <0x2000000 0x10000>;
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reg-names = "control";
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};
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L2: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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interrupts-extended = <&L3 65535>;
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reg = <0x0 0x1000>;
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reg-names = "control";
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};
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L7: error-device@3000 {
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compatible = "sifive,error0";
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reg = <0x3000 0x1000>;
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reg-names = "mem";
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};
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L9: external-interrupts {
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interrupt-parent = <&L0>;
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interrupts = <1 2>;
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};
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L0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&L3 11 &L3 9>;
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reg = <0xc000000 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev = <3>;
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};
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L8: rom@10000 {
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compatible = "sifive,rom0";
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reg = <0x10000 0x10000>;
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reg-names = "mem";
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};
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};
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htif {
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compatible = "ucb,htif0";
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};
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};
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