Commit Graph

78 Commits

Author SHA1 Message Date
Saer Debel
a221ee1ca8 Enabled IPC debug features under new config
Introduced a new config flag to enable
userError format strings to be written to the IPC buffer.
Another config bool has been introduced to toggle
printing the error out and this can also be set at runtime.

Signed-off-by: Saer Debel <saer.debel@data61.csiro.au>
2020-04-06 14:21:46 +10:00
Stephen Sherratt
39dd11b113 Fix python warning in syscall stub generator
The "is" keyword compares addresses. "==" compares values.
2020-03-11 14:55:40 +11:00
Gerwin Klein
79da079239 Convert license tags to SPDX identifiers
This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.
2020-03-09 13:21:49 +08:00
Kent McLeod
8234026c1f aarch64: Move tpidrro_el0 from vcpu to tcb context
This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.

This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.
2019-09-19 11:39:14 +10:00
Anna Lyons
554f812da3 mcs: scheduling context donation over ipc
After this commit, threads blocked on an endpoint can recieve a
scheduling context from the thread that wakes the blocked thread.
2019-08-22 11:22:37 +10:00
Anna Lyons
952134d1b8 mcs: Add a scheduling context object
This is the first part of the seL4 MCS. This commit:

    * adds a scheduling context object. Threads without scheduling
      context objects cannot be scheduled.
    * replaces tcbTimeSlice with the scheduling context object
    * adds seL4_SchedControl caps for each core
    * adds seL4_SchedControl_Configure which allows users to configure
      amount of ticks a scheduling context has, and set a core for the
      scheduling context.
    * adds seL4_SchedContext_Bind, Unbind and UnbindObject, which allows
      a tcb to be bound to a scheduling context.
2019-08-22 11:22:34 +10:00
Anna Lyons
bc61a7f3bd python2 --> python3
Update all scripts and build system to call python3, given python2's
upcoming doom. Use sys.maxsize instead of sys.maxint in one script
(maxint does not exist in python3).
2019-08-08 10:19:24 +10:00
Anna Lyons
d1153fbed8 aarch64: abstract vspace in libsel4
Depending on the physical address range the top level translation table
may be a page upper directory or a page global directory. Rename in
libsel4 the invocations on top level structures to be on an
seL4_ARM_VSpace rather than an seL4_ARM_PageGlobalDirectory.
2019-07-25 09:59:17 +10:00
Curtis Millar
5646f77463 RFC-3: Update user context for ARM with thread IDs
Switched appropriate naming conventions.
Was using the aarch64, have switched to aarch64 names.

TIPDRURW -> tpidr_el0
TPIDRURO -> tpidrro_el0
TPIDRPRW -> tpidr_el1

Switch TLS register on aarch32 from TPIDURO (tpidrro_el0) to tpidr_ro so
that it can be written to from user-land.

Thread ID registers tpidr_el0 have been added to the user context for
aarch32 and aarch64.

Only the thread ID that is writeable from EL0 is saved in the TCB and
saved/restored on context switch.

Thread IDs that are only changed within a VM (the read-only thread ID
for exception level 0 and the thread ID for exception level 1) are
stored in the VCPU and saved and stored as part of VM enable/disable.

Thread IDs that are only changed with VMs have been separated out into
hypervisor code.
2019-07-01 11:00:37 +10:00
Curtis Millar
3207abeeb7 RFC-3: Update context for x86 to use FS and GS.
TLS_BASE virtual register is replaced with FS_BASE and GS_BASE virtual
registers.

The FS_BASE and GS_BASE virtual registers are moved to the end of the
context so they need not be considered in the kernel exit and entry
implementation.

Removed tracking of ES, DS, FS, and GS segment selectors on kernel entry
and exit.

ES and DS are clobbered on kernel entry with the RPL 3 selector for a
DPL 3 linear data segment.

FS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with FS_BASE as the base. This is done on exit to reload the value from
the GDT.

GS is clobbered on exit with the RPL 3 selector for the DPL 3 segment
with GS_BASE as the base. This is done on exit to reload the value from
the GDT.

Kernel entry and exit code is refactored, simplified, and improved in
light of the above changes.

x64: update verified config to use fsgsbase instr

The verification platform for x64 relies on the fsgsbase instruction.
2019-07-01 10:46:46 +10:00
Anna Lyons
cf57914c7f style: run autopep8 on python files 2019-03-27 10:43:58 +11:00
Edward Pierzchalski
4ea62e5158 riscv: add remaining registers to user context.
The registers a7, s2-11, and t3-6 were missing from seL4_UserContext.
We also add these to frameRegisters and gpRegisters, which are used
to implement the TCB invocations for reading and writing these
registers.

Zero-length arrays aren't valid expressions or types in ISO C, so
to keep the c parser happy we need to either remove gpRegisters or
provide some contents for it.

In the past, frameRegisters and gpRegisters distinguished between
those registers preserved across a syscall and those that weren't.
TCB_CopyRegisters allows the caller to choose which set to copy.

Since we preserve all non-return registers, this distinction isn't
relevant anymore and there's no easy way to justify the members of
frameRegisters and gpRegisters.

We arbitrarily choose to put the 'last' register t6 in gpRegisters,
for consistency with the register list in registerset.h and with the
order that registers are restored.
2018-12-06 15:04:41 +11:00
Anna Lyons
b5ee12f00c manual: group generated API methods by object type
This change generates doxygen groups for each object type, which allows us to create sections in
output documents for each object. This has the advantage that we can later label those sections and
link to them from the main document. Additionally, it improves nagivation of the API docs.
2018-05-10 11:36:01 +10:00
Adrian Danis
de42f82691 x86: Introduce IO port control caps
Changes the way IO ports work such that instead of 'minting' IO port caps down into new
IO port caps with smaller ranges new IO port ranges must be allocated centrally from
an IO port control cap. This mechanism acts in a very similar fashion as IRQ handler/control
capabilities and ensures that allocated IO ports do not overlap. Disallowing overlapping
IO ports is necessary to ensure the CDT remains valid as capabilities are deleted.
2018-04-24 14:04:46 +10:00
Hesham Almatary
83ba084713 [SELFOUR-1156] RISC-V Port
Experimental release that supports both RV32 and RV64
2018-04-18 10:10:14 +10:00
Yanyan Shen
6bfc46311c libsel4/armv8: Add seL4_ARM_VCPU for aarch64 2018-03-28 12:15:09 +11:00
Anna Lyons
05b83acd95 SELFOUR-1016: Require auth cap to set prio/mcp
This fixes confused deputy problem when setting priorities/mcps.
2018-02-26 11:24:22 +11:00
Adrian Danis
8108c811ed libsel4: Remove bitfield type unifying Guard and Badge construction
Using the bitfield generator to treat guards and badges as a union type can be convenient,
but it requires reserving a bit in the data for the bitfield run time type information.
This type information is not needed by the kernel as it knows implicitly whether the passed
data is a badge or a guard based on the kind of cap being operated on. However, with the
type information present we cannot pass a word sized piece of data to the kernel.

The solution here is to go back to using a plain seL4_Word as the type for invocations
that want a capdata and let the user either construct a badge as a plain word, or use
the seL4_CNode_CapData bitfield for constructing a guard, although they have to manually extract
the word representation out of it.
2017-10-27 12:15:09 +11:00
Anna Lyons
8fb06eecff libsel4: Return seL4_Error in invocation stubs
Some stubs return structs, which will not change, however instead of
long for those that don't return structs they now return a seL4_Error.
2017-08-22 07:57:54 +10:00
Anna Lyons
64cf2308ac tools: fix licenses 2017-06-22 15:27:30 +10:00
Anna Lyons
07f948331f libsel4: fix licenses
- some were incorrectly marked GPL (libsel4 is BSD)
- update NICTA --> DATA61 etc
- fix tags D61 --> DATA61
- update year to 2017
2017-06-22 15:27:29 +10:00
Stephen Sherratt
f39f925612 manual: Better inference of method manual labels
Manual labels for methods are inferred unless specified in the api
description. This change extends this inference to prevent slashes
appearing in method labels. It also refactors the logic for label
inference to be more readable.
2017-06-02 16:34:49 +10:00
Stephen Sherratt
d8e6a00115 manual: Improve handling of return type docs
If no documentation is provided for the return value of a function, the
documentation generator will attempt to infer the documentation based on
the return type.
2017-06-02 15:34:45 +10:00
Stephen Sherratt
447e924337 manual: Undocumented return defaults to error enum 2017-06-02 15:34:45 +10:00
Stephen Sherratt
c662c2effe manual: Tweak manual label inference 2017-06-02 15:34:45 +10:00
Stephen Sherratt
ec3b640248 manual: Add label_prefix to method names 2017-06-02 15:34:45 +10:00
Stephen Sherratt
cb952a2be4 Replace division with int division in py scripts 2017-02-22 12:20:15 +11:00
Stephen Sherratt
8c93b71c1c Import reduce from functools in python scripts 2017-02-22 12:19:58 +11:00
Stephen Sherratt
7337f9e8df Parens around print args in python scripts 2017-02-22 12:19:24 +11:00
amrzar
6428e959b4 aarch64: Add aarch64 libsel4 implementation 2017-02-10 16:43:46 +11:00
Stephen Sherratt
1f1a5ad4dc manual: Removed default cap description 2016-12-16 15:57:57 +11:00
Adrian Danis
78009dd245 SELFOUR-675: x64: Increase message registers from 2 to 4 2016-11-30 12:04:54 +11:00
Stephen Sherratt
08bca15c5f manual: Obj inv stub gen generates doxy comments
This modifies the object invocations stub generator to generate doxygen
comments based on documentation in the xml files it parses.

JIRA: SELFOUR-606
2016-11-29 14:30:36 +11:00
Anna Lyons
2fea9a0fe2 SELFOUR-567: use seL4_CapRights_t from libsel4
This change

* changes seL4_CapRights from the kernel to be seL4_CapRights_t in
libsel4
* deprecates the duplicated seL4_CapRights in libsel4, which is
  now the bitfield generated type seL4_CapRights_t.
* fixes all usages in kernel and libsel4

Impact: for verification, this will require the type to change name
from cap_rights to seL4_CapRights_t.
This is a breaking libsel4 API change, although most code uses
seL4_AllRights or similar constants, which will not break
at a source level as these constants have been updated.
2016-11-25 12:29:07 +11:00
Adrian Danis
8a49b94893 Merge pull request #446 in SEL4/sel4 from ~ADANIS/sel4:withmrs to master
* commit 'be68b0c0bde5bfa439376fac4c8be255dacaa958':
  libsel4: Allow invocations to not use IPC buffer
  Retain in-register error descriptions when not using IPC buffer
2016-10-28 04:35:09 +00:00
Jeff Waugh
dc3d53417e Retain in-register error descriptions when not using IPC buffer
- Fixes "lost" error descriptions when using *WithMRs system call
  variants [1].
- Only stores real registers to IPC buffer if there's an error.
- If there's an error in a struct-returning function, return
  early without setting any struct members.
- Passes the sabre/qemu test suite... with and without --buffer!

[1] https://sel4.systems/pipermail/devel/2016-October/001079.html
2016-10-28 14:57:39 +11:00
Adrian Danis
48f99701c3 libsel4: Move vt-x definitions into common x86 2016-10-28 12:16:41 +11:00
Adrian Danis
7fbde1bbcb SELFOUR-287: 32-bit vt-x implementation
This is an implementation of vt-x for x86 kernels running in
ia32 mode.
2016-10-27 16:20:30 +11:00
Jeff Waugh
59d48b778b Let x86_64 CallWithMRs
* `syscall_stub_gen.py` now works on x86_64 without passing `--buffer`
2016-10-27 12:09:00 +11:00
amrzar
ee75f086f3 update #ifdef to #if in auto generated files 2016-10-17 12:18:58 +11:00
Adrian Danis
067b71cad4 x64/libsel4: Add x64 libsel4 implementation 2016-10-12 12:22:32 +11:00
Anna Lyons
7336303b7f SELFOUR-276: Add MCP field to threads.
Where MCP = Maximum Controlled Priority

This commit adds:

* seL4_TCB_SetMCPriority

and changes the arguments to

* seL4_TCB_Configure

As of this commit, a thread cannot create or set a threads
priority (including itself) above its mcp. Previously the kernel
did this check against a threads priority, which prevented a thread
from setting it's own priority down and then up again.
2016-10-05 11:11:19 +11:00
Alexander Boettcher
9fc8194b1f fix "syscall_stub_gen.py --word-size" invocation
Fixes #29
2016-07-06 16:03:58 +02:00
Adrian Danis
cd96226421 Merge branch master into arm_hyp
Conflicts:
	include/arch/arm/arch/32/mode/object/structures.h
2016-06-21 14:39:32 +10:00
Adrian Danis
ce8dfb1590 tools: Further support for conditional invocation labels
Condition invocation labels where added in commit 73837c8ace
This commit guards usage of conditionally generated labels during generation
of the syscall stubs.
2016-06-21 09:20:26 +10:00
Adrian Danis
6d6b047b2d Minor fixes for other ARM platforms 2016-06-07 13:35:55 +10:00
Adrian Danis
41603a26ca Correct merge of master 2016-06-02 12:15:46 +10:00
Adrian Danis
b001bc4489 Merge branch 'master' into 'arm_hyp'
Conflicts:
	Kconfig
	libsel4/tools/syscall_stub_gen.py
	src/plat/exynos5/machine/hardware.c
	src/plat/tk1/machine/Makefile
	src/plat/tk1/machine/hardware.c
2016-06-02 10:57:12 +10:00
Yanyan Shen
879d9724c1 arm/tk1: a checkpoint for SMMU implementation 2016-05-13 16:42:53 +10:00
Anna Lyons
12efee6a76 SELFOUR-404: fix bug related to double words
They would get shifted by the size of the type rather than the
size of the word. This wasn't detected initially as the master
branch of the kernel does not have any double word types in the API.
2016-04-28 10:56:19 +10:00