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riscv: Add SMP code for ifence/sfence/hwASIDFlush

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If SMP is enabled, sfence/ifence/hwASIDFlush also IPI other
cores.
This commit is contained in:
Yanyan Shen
2019-08-06 17:05:51 +10:00
committed by Yanyan Shen
parent 07a5a3f5d9
commit e1c529caa5
1 changed files with 49 additions and 1 deletions
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50
include/arch/riscv/arch/machine.h
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@@ -47,11 +47,59 @@ static inline void sfence_local(void)
asm volatile("sfence.vma" ::: "memory"); asm volatile("sfence.vma" ::: "memory");
} }
static inline void hwASIDFlush(asid_t asid) static inline void ifence(void)
{
ifence_local();
#ifdef ENABLE_SMP_SUPPORT
unsigned long mask = 0;
for (int i = 0; i < CONFIG_MAX_NUM_NODES; i++) {
if (i != getCurrentCPUIndex()) {
mask |= BIT(cpuIndexToID(i));
}
}
sbi_remote_fence_i(&mask);
#endif
}
static inline void sfence(void)
{
#ifdef ENABLE_SMP_SUPPORT
fence_w_rw();
#endif
sfence_local();
#ifdef ENABLE_SMP_SUPPORT
unsigned long mask = 0;
for (int i = 0; i < CONFIG_MAX_NUM_NODES; i++) {
if (i != getCurrentCPUIndex()) {
mask |= BIT(cpuIndexToID(i));
}
}
sbi_remote_sfence_vma(&mask, 0, 0);
#endif
}
static inline void hwASIDFlushLocal(asid_t asid)
{ {
asm volatile("sfence.vma x0, %0" :: "r"(asid): "memory"); asm volatile("sfence.vma x0, %0" :: "r"(asid): "memory");
} }
static inline void hwASIDFlush(asid_t asid)
{
hwASIDFlushLocal(asid);
#ifdef ENABLE_SMP_SUPPORT
unsigned long mask = 0;
for (int i = 0; i < CONFIG_MAX_NUM_NODES; i++) {
if (i != getCurrentCPUIndex()) {
mask |= BIT(cpuIndexToID(i));
}
}
sbi_remote_sfence_vma_asid(&mask, 0, 0, asid);
#endif
}
word_t PURE getRestartPC(tcb_t *thread); word_t PURE getRestartPC(tcb_t *thread);
void setNextPC(tcb_t *thread, word_t v); void setNextPC(tcb_t *thread, word_t v);