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riscv: Fix MAX_IRQ for QEMU platform

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A better solution would be to parse the DTS; however QEMU
hasn't changed this in 6 years.

Signed-off-by: julia <git.ts@trainwit.ch>
This commit is contained in:
julia
2024-11-11 15:32:29 +11:00
committed by Indan Zupancic
parent 640643954c
commit d6b4e774ca
1 changed files with 3 additions and 2 deletions
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5
src/plat/qemu-riscv-virt/config.cmake
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@@ -190,12 +190,13 @@ if(KernelPlatformQEMURiscVVirt)
list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-qemu-riscv-virt32.dts") list(APPEND KernelDTSList "${CMAKE_CURRENT_LIST_DIR}/overlay-qemu-riscv-virt32.dts")
endif() endif()
# QEMU emulates a SiFive PLIC/CLINT with 127 interrupt sources by default. # QEMU emulates a SiFive PLIC/CLINT with 96 interrupt sources by default.
# https://github.com/qemu/qemu/blob/stable-9.1/include/hw/riscv/virt.h#L102
# The CLINT timer pretends to run at 10 MHz, but this speed may not hold in # The CLINT timer pretends to run at 10 MHz, but this speed may not hold in
# practical measurements. # practical measurements.
declare_default_headers( declare_default_headers(
TIMER_FREQUENCY 10000000 TIMER_FREQUENCY 10000000
MAX_IRQ 128 MAX_IRQ 95
INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h INTERRUPT_CONTROLLER drivers/irq/riscv_plic0.h
) )