From 8f7b168a53eed37f548168934319cbe8f9296ea3 Mon Sep 17 00:00:00 2001
From: Yanyan Shen <yanyan.shen@data61.csiro.au>
Date: Tue, 6 Aug 2019 16:58:06 +1000
Subject: [PATCH] riscv: Add SMP data

Add data for converting logical core ID to hart ID and vice verse.
---
 src/arch/riscv/model/statedata.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/riscv/model/statedata.c b/src/arch/riscv/model/statedata.c
index e9c6630dc..fedbf0ef6 100644
--- a/src/arch/riscv/model/statedata.c
+++ b/src/arch/riscv/model/statedata.c
@@ -35,3 +35,5 @@ pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits
 #if __riscv_xlen != 32
 pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
 #endif
+
+SMP_STATE_DEFINE(core_map_t, coreMap);