forked from Imagelibrary/seL4
RISCV: Add Hifive unleashed platform
This change adds support for Hifive unleashed board. It also removes the outdated hifive suport from the spike platform.
This commit is contained in:
Siwei Zhuang
@@ -71,7 +71,8 @@ function(declare_default_headers)
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)
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# calculate the irq cnode size based on MAX_IRQ
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if("${KernelArch}" STREQUAL "riscv")
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set(MAX_IRQ "${CONFIGURE_PLIC_MAX_NUM_INT} + 2")
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set(MAX_IRQ "${CONFIGURE_PLIC_MAX_NUM_INT}")
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math(EXPR MAX_IRQ "${MAX_IRQ} + 2")
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else()
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set(MAX_IRQ "${CONFIGURE_MAX_IRQ}")
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endif()
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@@ -89,8 +90,8 @@ function(declare_default_headers)
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# variables parsed by the above will be prepended with CONFIGURE_, so pipe them
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# straight to configure_file
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configure_file(
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src/arch/${KernelArch}/platform_gen.h.in ${CMAKE_CURRENT_BINARY_DIR}/gen_headers/plat/platform_gen.h
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@ONLY
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src/arch/${KernelArch}/platform_gen.h.in
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${CMAKE_CURRENT_BINARY_DIR}/gen_headers/plat/platform_gen.h @ONLY
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)
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include_directories(include/plat/default)
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endfunction()
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@@ -22,17 +22,17 @@
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#define STORE sw
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/* Contain the typical location of memory */
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#define PADDR_BASE 0x80000000lu
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#define PADDR_BASE physBase
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/* This represents the physical address that the kernel image will be linked to. This needs to
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* be on a 1gb boundary as we currently require being able to creating a mapping to this address
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* as the largest frame size */
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#define PADDR_LOAD 0x84000000
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#define PADDR_LOAD UL_CONST(0x84000000)
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/* This is the base of the kernel window, which is directly mapped to PADDR_BASE */
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#define PPTR_BASE seL4_UserTop
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/* This is the mapping of the kernel (mapped above the kernel window currently) */
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#define KERNEL_BASE 0xFF800000
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#define KERNEL_BASE UL_CONST(0xFF800000)
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#define KERNEL_ELF_BASE KERNEL_BASE
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/* Start of kernel device mapping region in highest 4MiB of memory. */
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#define KDEV_PPTR 0xFFC00000
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#define KDEV_PPTR UL_CONST(0xFFC00000)
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#endif /* __ARCH_MODE_HARDWARE_H */
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@@ -91,12 +91,12 @@
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/* This represents the physical address that the kernel image will be linked to. This needs to
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* be on a 1gb boundary as we currently require being able to creating a mapping to this address
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* as the largest frame size */
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#define PADDR_LOAD 0x84000000
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#define PADDR_LOAD UL_CONST(physBase + 0x4000000)
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/* This is the base of the kernel window, which is directly mapped to PADDR_BASE */
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#define PPTR_BASE 0xFFFFFFC000000000lu
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/* This is the mapping of the kernel (mapped above the kernel window currently) */
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#define KERNEL_BASE 0xFFFFFFFF80000000lu
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#define KERNEL_ELF_BASE 0xFFFFFFFF84000000
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#define KERNEL_ELF_BASE UL_CONST(0xFFFFFFFF84000000)
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/* Start of kernel device mapping region in highest 1GiB of memory. */
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#define KDEV_PPTR 0xFFFFFFFFC0000000lu
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#else
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@@ -10,6 +10,9 @@
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* @TAG(DATA61_GPL)
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*/
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#ifndef __ARCH_MACHINE_PLIC_H
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#define __ARCH_MACHINE_PLIC_H
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/*
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* RISC-V defines a Platform-level interrupt controller (PLIC) (priv-1.10).
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* It is responsible for managing global interrupts in a RISC-V system.
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@@ -63,3 +66,4 @@ static inline void plic_init_controller(void)
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{
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}
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#endif /* __ARCH_MACHINE_PLIC_H */
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@@ -10,16 +10,14 @@
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* @TAG(DATA61_GPL)
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*/
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#ifndef __PLAT_INSTANCE_HARDWARE_H
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#define __PLAT_INSTANCE_HARDWARE_H
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#ifndef __DRIVER_IRQ_HIFIVE_H
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#define __DRIVER_IRQ_HIFIVE_H
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#define PLIC_MAX_NUM_INT 53
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#define IRQ_CNODE_SLOT_BITS 6
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#include <plat/machine/devices_gen.h>
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#define PLIC_BASE 0x0C000000
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#define PLIC_PPTR_BASE 0xFFFFFFFFCC000000
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#define PLIC_PPTR_BASE PLIC_PPTR + 0x0C000000
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#define PLIC_HARTID 2
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#define PLIC_HARTID (CONFIG_FIRST_HART_ID * 2)
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#define PLIC_PRIO 0x0
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#define PLIC_PRIO_PER_ID 0x4
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@@ -31,6 +29,7 @@
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#define PLIC_THRES_PER_HART 0x1000
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#define PLIC_THRES_CLAIM 0x4
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typedef uint32_t interrupt_t;
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static inline uint32_t readl(const volatile uint64_t addr)
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{
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uint32_t val;
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@@ -116,36 +115,10 @@ static inline void plic_init_controller(void)
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writel(1, (PLIC_PPTR_BASE + PLIC_THRES + PLIC_THRES_PER_HART * PLIC_HARTID));
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/* Set the priorities of all interrupts to 1 */
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for (int i = 1; i <= PLIC_MAX_NUM_INT + 1; i++) {
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for (int i = 1; i <= PLIC_MAX_IRQ + 1; i++) {
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writel(2, PLIC_PPTR_BASE + PLIC_PRIO + PLIC_PRIO_PER_ID * i);
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}
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}
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/* Available physical memory regions on platform (RAM minus kernel image). */
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/* NOTE: Regions are not allowed to be adjacent! */
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static p_region_t BOOT_DATA avail_p_regs[] = {
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/* The first 2MB are reserved for the SBI in the BBL */
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#if defined(CONFIG_ARCH_RISCV64)
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{ /*.start = */ 0x80200000, /* .end = */ 0x17FF00000}
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#elif defined(CONFIG_ARCH_RISCV32)
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{ /*.start = */ 0x80200000, /* .end = */ 0xFD000000}
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#endif
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};
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static const paddr_t BOOT_RODATA kernel_devices[] = {
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/* Plic0 */
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0x00000000,
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};
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static const p_region_t BOOT_RODATA dev_p_regs[] = {
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{ 0x10010000, 0x10011000 }, /* UART0 */
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{ 0x10011000, 0x10012000 }, /* UART1 */
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{ 0x10020000, 0x10021000 }, /* PWM0 */
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{ 0x10021000, 0x10022000 }, /* PWM1 */
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{ 0x10060000, 0x10061000 }, /* GPIO */
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{ 0x10090000, 0x10091000 }, /* ETH */
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};
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#endif
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#endif /* __DRIVER_IRQ_HIFIVE_H */
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20
libsel4/sel4_plat_include/hifive/sel4/plat/api/constants.h
Normal file
20
libsel4/sel4_plat_include/hifive/sel4/plat/api/constants.h
Normal file
@@ -0,0 +1,20 @@
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/*
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* Copyright 2018, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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* ABN 41 687 119 230.
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*
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* This software may be distributed and modified according to the terms of
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* the BSD 2-Clause license. Note that NO WARRANTY is provided.
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* See "LICENSE_BSD2.txt" for details.
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*
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* @TAG(DATA61_BSD)
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*/
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#ifndef __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_
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#define __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_
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#ifdef HAVE_AUTOCONF
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#include <autoconf.h>
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#endif
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#endif /* __LIBSEL4_SEL4_PLAT_API_CONSTANTS_H_ */
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@@ -25,8 +25,13 @@ config_choice(
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RISCV_PLAT
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"Select the platform for the architecture"
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"spike;KernelPlatformSpike;PLAT_SPIKE;KernelArchRiscV"
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"hifive;KernelPlatformHifive;PLAT_HIFIVE;KernelSel4ArchRiscV64"
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)
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# Include all the platforms.
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include(src/plat/spike/config.cmake)
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include(src/plat/hifive/config.cmake)
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if(KernelArchRiscV)
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config_set(KernelSel4Arch SEL4_ARCH "${KernelRiscVSel4Arch}")
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endif()
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@@ -37,9 +42,6 @@ elseif(KernelSel4ArchRiscV64)
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set_kernel_64()
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endif()
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# Include all the platforms.
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include(src/plat/spike/config.cmake)
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config_string(
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KernelPTLevels PT_LEVELS "Number of page \
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table levels for RISC-V depends on the mode. For example there are: \
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@@ -99,6 +99,7 @@ static pte_t pte_next(word_t phys_addr, bool_t is_leaf)
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BOOT_CODE void map_kernel_frame(paddr_t paddr, pptr_t vaddr, vm_rights_t vm_rights)
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{
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paddr = ROUND_DOWN(paddr, RISCV_GET_LVL_PGSIZE_BITS(1));
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assert((paddr % RISCV_GET_LVL_PGSIZE(1)) == 0);
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kernel_root_pageTable[RISCV_GET_PT_INDEX(vaddr, 1)] = pte_next(paddr, true);
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}
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@@ -27,7 +27,7 @@
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#define SEXTERNAL_IE 9
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#define SEXTERNAL_CAUSE 9
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#define RESET_CYCLES ((CONFIG_SPIKE_CLOCK_FREQ / MS_IN_S) * CONFIG_TIMER_TICK_MS)
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#define RESET_CYCLES ((TIMER_CLOCK_HZ / MS_IN_S) * CONFIG_TIMER_TICK_MS)
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#define IS_IRQ_VALID(X) (((X)) <= maxIRQ && (X)!= irqInvalid)
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@@ -80,7 +80,7 @@ BOOT_CODE void map_kernel_devices(void)
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return;
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}
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for (int i = 0; i < (sizeof(kernel_devices) / sizeof(paddr_t)); i++) {
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for (int i = 0; i < (sizeof(kernel_devices) / sizeof(kernel_frame_t)); i++) {
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map_kernel_frame(kernel_devices[i].paddr, KDEV_PPTR,
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VMKernelOnly);
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}
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25
src/plat/hifive/config.cmake
Normal file
25
src/plat/hifive/config.cmake
Normal file
@@ -0,0 +1,25 @@
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#
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# Copyright 2019, Data61
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# Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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# ABN 41 687 119 230.
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#
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# Copyright 2019, DornerWorks
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#
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# This software may be distributed and modified according to the terms of
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# the GNU General Public License version 2. Note that NO WARRANTY is provided.
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# See "LICENSE_GPLv2.txt" for details.
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#
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# @TAG(DATA61_DORNERWORKS_GPL)
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#
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cmake_minimum_required(VERSION 3.7.2)
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if(KernelPlatformHifive)
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config_set(KernelPlatform PLAT "hifive")
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config_set(KernelPlatformFirstHartID FIRST_HART_ID 1)
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list(APPEND KernelDTSList "tools/dts/hifive.dts")
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declare_default_headers(
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TIMER_FREQUENCY 10000000llu PLIC_MAX_NUM_INT 53
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INTERRUPT_CONTROLLER drivers/irq/hifive.h
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)
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endif()
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@@ -16,38 +16,14 @@ cmake_minimum_required(VERSION 3.7.2)
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if(KernelPlatformSpike)
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config_set(KernelPlatform PLAT "spike")
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config_set(KernelPlatformFirstHartID FIRST_HART_ID 0)
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if(Kernel32)
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list(APPEND KernelDTSList "tools/dts/spike32.dts")
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else()
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list(APPEND KernelDTSList "tools/dts/spike.dts")
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endif()
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declare_default_headers(TIMER_FREQUENCY 10000000llu PLIC_MAX_NUM_INT 2
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INTERRUPT_CONTROLLER arch/machine/plic.h)
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declare_default_headers(
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TIMER_FREQUENCY 10000000llu PLIC_MAX_NUM_INT 0
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INTERRUPT_CONTROLLER arch/machine/plic.h
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)
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endif()
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config_choice(
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KernelSpikeInstance
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RISCV_SPIKE_INSTANCE
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"Select the instance for Spike to run on"
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"qemu;KernelPlatformSpikeQemu;BUILD_SPIKE_QEMU;KernelArchRiscV"
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"rocket-chip-zedboard;KernelPlatformSpikeRocketChip;BUILD_ROCKET_CHIP_ZEDBOARD;KernelSel4ArchRiscV64"
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"hi-five-unleashed;KernelPlatformSpikeSiFiveFreedom;BUILD_HI_FIVE_UNLEASHED;KernelSel4ArchRiscV64"
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)
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config_string(
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KernelPlatformSpikeClockFrequency SPIKE_CLOCK_FREQ "Frequency of Clock used for Scheduler"
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DEFAULT 10000000
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UNQUOTE
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)
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set(DefaultFirstHartID 0)
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# Include all of the different instances of the Spike platform
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include(src/plat/spike/instance/rocket-chip/config.cmake)
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include(src/plat/spike/instance/freedom/config.cmake)
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config_string(
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KernelPlatformSpikeFirstHartID FIRST_HART_ID "HART ID of the first kernel HART "
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DEFAULT ${DefaultFirstHartID}
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UNQUOTE
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)
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@@ -1,14 +0,0 @@
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#
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# Copyright 2018, DornerWorks
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#
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# This software may be distributed and modified according to the terms of
|
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# the GNU General Public License version 2. Note that NO WARRANTY is provided.
|
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# See "LICENSE_GPLv2.txt" for details.
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#
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# @TAG(DORNERWORKS_GPL)
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#
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if(KernelPlatformSpikeSiFiveFreedom)
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set(KernelPlatformSpikeClockFrequency 1000000)
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set(DefaultFirstHartID 1)
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endif()
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@@ -1,13 +0,0 @@
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#
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# Copyright 2018, DornerWorks
|
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#
|
||||
# This software may be distributed and modified according to the terms of
|
||||
# the GNU General Public License version 2. Note that NO WARRANTY is provided.
|
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# See "LICENSE_GPLv2.txt" for details.
|
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#
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# @TAG(DORNERWORKS_GPL)
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#
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if(KernelPlatformSpikeQemu)
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set(KernelPlatformSpikeClockFrequency 10000000)
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endif()
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527
tools/dts/hifive.dts
Normal file
527
tools/dts/hifive.dts
Normal file
@@ -0,0 +1,527 @@
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/* Copyright (c) 2018 SiFive, Inc */
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/* SPDX-License-Identifier: Apache-2.0 */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
|
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/* See the file LICENSE for further information */
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/* @TAG(OTHER_GPL) */
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/dts-v1/;
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/ {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "sifive,fu540g", "sifive,fu500";
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model = "sifive,hifive-unleashed-a00";
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aliases {
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serial0 = <0x2f736f63 0x2f736572 0x69616c40 0x31303031 0x30303030>;
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serial1 = <0x2f736f63 0x2f736572 0x69616c40 0x31303031 0x31303030>;
|
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};
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chosen {
|
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};
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firmware {
|
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sifive,fsbl = "2018-03-20";
|
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};
|
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cpus {
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#address-cells = <0x00000001>;
|
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#size-cells = <0x00000000>;
|
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timebase-frequency = <0x000f4240>;
|
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cpu@0 {
|
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clock-frequency = <0x00000000>;
|
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compatible = "sifive,rocket0", "riscv";
|
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device_type = "cpu";
|
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i-cache-block-size = <0x00000040>;
|
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i-cache-sets = <0x00000080>;
|
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i-cache-size = <0x00004000>;
|
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next-level-cache = <0x00000001 0x00000002>;
|
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reg = <0x00000000>;
|
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riscv,isa = "rv64imac";
|
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sifive,dtim = <0x00000003>;
|
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sifive,itim = <0x00000004>;
|
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status = "masked";
|
||||
interrupt-controller {
|
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#interrupt-cells = <0x00000001>;
|
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compatible = "riscv,cpu-intc";
|
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interrupt-controller;
|
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linux,phandle = <0x0000000f>;
|
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phandle = <0x0000000f>;
|
||||
};
|
||||
};
|
||||
cpu@1 {
|
||||
clock-frequency = <0x00000000>;
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x00000040>;
|
||||
d-cache-sets = <0x00000040>;
|
||||
d-cache-size = <0x00008000>;
|
||||
d-tlb-sets = <0x00000001>;
|
||||
d-tlb-size = <0x00000020>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x00000040>;
|
||||
i-cache-sets = <0x00000040>;
|
||||
i-cache-size = <0x00008000>;
|
||||
i-tlb-sets = <0x00000001>;
|
||||
i-tlb-size = <0x00000020>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <0x00000001 0x00000002>;
|
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reg = <0x00000001>;
|
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riscv,isa = "rv64imafdc";
|
||||
sifive,itim = <0x00000005>;
|
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status = "okay";
|
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tlb-split;
|
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interrupt-controller {
|
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#interrupt-cells = <0x00000001>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
linux,phandle = <0x00000010>;
|
||||
phandle = <0x00000010>;
|
||||
};
|
||||
};
|
||||
cpu@2 {
|
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clock-frequency = <0x00000000>;
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x00000040>;
|
||||
d-cache-sets = <0x00000040>;
|
||||
d-cache-size = <0x00008000>;
|
||||
d-tlb-sets = <0x00000001>;
|
||||
d-tlb-size = <0x00000020>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x00000040>;
|
||||
i-cache-sets = <0x00000040>;
|
||||
i-cache-size = <0x00008000>;
|
||||
i-tlb-sets = <0x00000001>;
|
||||
i-tlb-size = <0x00000020>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <0x00000001 0x00000002>;
|
||||
reg = <0x00000002>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
sifive,itim = <0x00000006>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
interrupt-controller {
|
||||
#interrupt-cells = <0x00000001>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
linux,phandle = <0x00000011>;
|
||||
phandle = <0x00000011>;
|
||||
};
|
||||
};
|
||||
cpu@3 {
|
||||
clock-frequency = <0x00000000>;
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x00000040>;
|
||||
d-cache-sets = <0x00000040>;
|
||||
d-cache-size = <0x00008000>;
|
||||
d-tlb-sets = <0x00000001>;
|
||||
d-tlb-size = <0x00000020>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x00000040>;
|
||||
i-cache-sets = <0x00000040>;
|
||||
i-cache-size = <0x00008000>;
|
||||
i-tlb-sets = <0x00000001>;
|
||||
i-tlb-size = <0x00000020>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <0x00000001 0x00000002>;
|
||||
reg = <0x00000003>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
sifive,itim = <0x00000007>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
interrupt-controller {
|
||||
#interrupt-cells = <0x00000001>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
linux,phandle = <0x00000012>;
|
||||
phandle = <0x00000012>;
|
||||
};
|
||||
};
|
||||
cpu@4 {
|
||||
clock-frequency = <0x00000000>;
|
||||
compatible = "sifive,rocket0", "riscv";
|
||||
d-cache-block-size = <0x00000040>;
|
||||
d-cache-sets = <0x00000040>;
|
||||
d-cache-size = <0x00008000>;
|
||||
d-tlb-sets = <0x00000001>;
|
||||
d-tlb-size = <0x00000020>;
|
||||
device_type = "cpu";
|
||||
i-cache-block-size = <0x00000040>;
|
||||
i-cache-sets = <0x00000040>;
|
||||
i-cache-size = <0x00008000>;
|
||||
i-tlb-sets = <0x00000001>;
|
||||
i-tlb-size = <0x00000020>;
|
||||
mmu-type = "riscv,sv39";
|
||||
next-level-cache = <0x00000001 0x00000002>;
|
||||
reg = <0x00000004>;
|
||||
riscv,isa = "rv64imafdc";
|
||||
sifive,itim = <0x00000008>;
|
||||
status = "okay";
|
||||
tlb-split;
|
||||
interrupt-controller {
|
||||
#interrupt-cells = <0x00000001>;
|
||||
compatible = "riscv,cpu-intc";
|
||||
interrupt-controller;
|
||||
linux,phandle = <0x00000013>;
|
||||
phandle = <0x00000013>;
|
||||
};
|
||||
};
|
||||
};
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0x00000002 0x00000000>;
|
||||
linux,phandle = <0x0000000e>;
|
||||
phandle = <0x0000000e>;
|
||||
};
|
||||
soc {
|
||||
#address-cells = <0x00000002>;
|
||||
#size-cells = <0x00000002>;
|
||||
compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus";
|
||||
ranges;
|
||||
refclk {
|
||||
#clock-cells = <0x00000000>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0x01fca055>;
|
||||
clock-output-names = "xtal";
|
||||
linux,phandle = <0x00000009>;
|
||||
phandle = <0x00000009>;
|
||||
};
|
||||
prci@10000000 {
|
||||
compatible = "sifive,aloeprci0";
|
||||
reg = <0x00000000 0x10000000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000009>;
|
||||
#clock-cells = <0x00000001>;
|
||||
linux,phandle = <0x0000000a>;
|
||||
phandle = <0x0000000a>;
|
||||
};
|
||||
tlclk {
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <0x0000000a 0x00000000>;
|
||||
#clock-cells = <0x00000000>;
|
||||
clock-div = <0x00000002>;
|
||||
clock-mult = <0x00000001>;
|
||||
linux,phandle = <0x00000016>;
|
||||
phandle = <0x00000016>;
|
||||
};
|
||||
cadence-gemgxl-mgmt@100a0000 {
|
||||
compatible = "sifive,cadencegemgxlmgmt0";
|
||||
reg = <0x00000000 0x100a0000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
#clock-cells = <0x00000000>;
|
||||
linux,phandle = <0x00000014>;
|
||||
phandle = <0x00000014>;
|
||||
};
|
||||
bus-blocker@100b8000 {
|
||||
compatible = "sifive,bus-blocker0";
|
||||
reg = <0x00000000 0x100b8000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
cache-controller@2010000 {
|
||||
cache-block-size = <0x00000040>;
|
||||
cache-level = <0x00000002>;
|
||||
cache-sets = <0x00000800>;
|
||||
cache-size = <0x00200000>;
|
||||
cache-unified;
|
||||
compatible = "sifive,ccache0", "cache";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000001 0x00000002 0x00000003>;
|
||||
next-level-cache = <0x0000000c 0x0000000d 0x0000000e>;
|
||||
reg = <0x00000000 0x02010000 0x00000000 0x00001000 0x00000000 0x08000000 0x00000000 0x02000000>;
|
||||
reg-names = "control", "sideband";
|
||||
linux,phandle = <0x00000002>;
|
||||
phandle = <0x00000002>;
|
||||
};
|
||||
cadence-ddr-mgmt@100c0000 {
|
||||
compatible = "sifive,cadenceddrmgmt0";
|
||||
reg = <0x00000000 0x100c0000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
chiplink@40000000 {
|
||||
#address-cells = <0x00000002>;
|
||||
#size-cells = <0x00000002>;
|
||||
compatible = "sifive,chiplink", "simple-bus";
|
||||
ranges = <0x00000000 0x60000000 0x00000000 0x60000000 0x00000000 0x20000000 0x00000030 0x00000000 0x00000030 0x00000000 0x00000010 0x00000000 0x00000000 0x40000000 0x00000000 0x40000000 0x00000000 0x20000000 0x00000020 0x00000000 0x00000020 0x00000000 0x00000010 0x00000000>;
|
||||
linux,phandle = <0x0000000d>;
|
||||
phandle = <0x0000000d>;
|
||||
};
|
||||
dma@3000000 {
|
||||
#dma-cells = <0x00000001>;
|
||||
compatible = "riscv,dma0";
|
||||
dma-channels = <0x00000004>;
|
||||
dma-requests = <0x00000000>;
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000017 0x00000018 0x00000019 0x0000001a 0x0000001b 0x0000001c 0x0000001d 0x0000001e>;
|
||||
reg = <0x00000000 0x03000000 0x00000000 0x00100000>;
|
||||
reg-names = "control";
|
||||
riscv,dma-pools = <0x00000001>;
|
||||
};
|
||||
dtim@1000000 {
|
||||
compatible = "sifive,dtim0";
|
||||
reg = <0x00000000 0x01000000 0x00000000 0x00002000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000003>;
|
||||
phandle = <0x00000003>;
|
||||
};
|
||||
ememoryotp@10070000 {
|
||||
compatible = "sifive,ememoryotp0";
|
||||
reg = <0x00000000 0x10070000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
error-device@18000000 {
|
||||
compatible = "sifive,error0";
|
||||
reg = <0x00000000 0x18000000 0x00000000 0x08000000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000001>;
|
||||
phandle = <0x00000001>;
|
||||
};
|
||||
ethernet@10090000 {
|
||||
compatible = "cdns,macb";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000035>;
|
||||
reg = <0x00000000 0x10090000 0x00000000 0x00002000>;
|
||||
reg-names = "control";
|
||||
local-mac-address = <0x70b3d592>;
|
||||
phy-mode = "gmii";
|
||||
clock-names = <0x70636c6b 0x0068636c 0x6b007478 0x5f636c6b>;
|
||||
clocks = <0x0000000a 0x00000001 0x0000000a 0x00000001 0x00000014>;
|
||||
#address-cells = <0x00000001>;
|
||||
#size-cells = <0x00000000>;
|
||||
ethernet-phy@0 {
|
||||
reg = <0x00000000>;
|
||||
reset-gpios = <0x00000015 0x0000000c 0x00000001>;
|
||||
};
|
||||
};
|
||||
gpio@10060000 {
|
||||
compatible = "sifive,gpio0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000007 0x00000008 0x00000009 0x0000000a 0x0000000b 0x0000000c 0x0000000d 0x0000000e 0x0000000f 0x00000010 0x00000011 0x00000012 0x00000013 0x00000014 0x00000015 0x00000016>;
|
||||
reg = <0x00000000 0x10060000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x00000002>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x00000002>;
|
||||
linux,phandle = <0x00000015>;
|
||||
phandle = <0x00000015>;
|
||||
};
|
||||
gpio-restart {
|
||||
compatible = "gpio-restart";
|
||||
gpios = <0x00000015 0x0000000a 0x00000001>;
|
||||
};
|
||||
i2c@10030000 {
|
||||
compatible = "sifive,i2c0", "opencores,i2c-ocores";
|
||||
reg = <0x00000000 0x10030000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000016>;
|
||||
reg-shift = <0x00000002>;
|
||||
reg-io-width = <0x00000001>;
|
||||
#address-cells = <0x00000001>;
|
||||
#size-cells = <0x00000000>;
|
||||
};
|
||||
interrupt-controller@c000000 {
|
||||
#interrupt-cells = <0x00000001>;
|
||||
compatible = "riscv,plic0";
|
||||
interrupt-controller;
|
||||
interrupts-extended = <0x0000000f 0xffffffff 0x00000010 0xffffffff 0x00000010 0x00000009 0x00000011 0xffffffff 0x00000011 0x00000009 0x00000012 0xffffffff 0x00000012 0x00000009 0x00000013 0xffffffff 0x00000013 0x00000009>;
|
||||
reg = <0x00000000 0x0c000000 0x00000000 0x04000000>;
|
||||
reg-names = "control";
|
||||
riscv,max-priority = <0x00000007>;
|
||||
riscv,ndev = <0x00000035>;
|
||||
linux,phandle = <0x0000000b>;
|
||||
phandle = <0x0000000b>;
|
||||
};
|
||||
itim@1800000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x00000000 0x01800000 0x00000000 0x00004000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000004>;
|
||||
phandle = <0x00000004>;
|
||||
};
|
||||
itim@1808000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x00000000 0x01808000 0x00000000 0x00008000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000005>;
|
||||
phandle = <0x00000005>;
|
||||
};
|
||||
itim@1810000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x00000000 0x01810000 0x00000000 0x00008000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000006>;
|
||||
phandle = <0x00000006>;
|
||||
};
|
||||
itim@1818000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x00000000 0x01818000 0x00000000 0x00008000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000007>;
|
||||
phandle = <0x00000007>;
|
||||
};
|
||||
itim@1820000 {
|
||||
compatible = "sifive,itim0";
|
||||
reg = <0x00000000 0x01820000 0x00000000 0x00008000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x00000008>;
|
||||
phandle = <0x00000008>;
|
||||
};
|
||||
memory-controller@100b0000 {
|
||||
compatible = "sifive,aloeddr0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x0000001f>;
|
||||
reg = <0x00000000 0x100b0000 0x00000000 0x00004000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
pci@2000000000 {
|
||||
#address-cells = <0x00000003>;
|
||||
#interrupt-cells = <0x00000001>;
|
||||
#size-cells = <0x00000002>;
|
||||
compatible = "ms-pf,axi-pcie-host";
|
||||
device_type = "pci";
|
||||
interrupt-map = <0x00000000 0x00000000 0x00000000 0x00000001 0x00000017 0x00000001 0x00000000 0x00000000 0x00000000 0x00000002 0x00000017 0x00000002 0x00000000 0x00000000 0x00000000 0x00000003 0x00000017 0x00000003 0x00000000 0x00000000 0x00000000 0x00000004 0x00000017 0x00000004>;
|
||||
interrupt-map-mask = <0x00000000 0x00000000 0x00000000 0x00000007>;
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000020>;
|
||||
ranges = <0x02000000 0x00000000 0x40000000 0x00000000 0x40000000 0x00000000 0x20000000>;
|
||||
reg = <0x00000020 0x00000000 0x00000000 0x04000000>;
|
||||
reg-names = "control";
|
||||
interrupt-controller {
|
||||
#address-cells = <0x00000000>;
|
||||
#interrupt-cells = <0x00000001>;
|
||||
interrupt-controller;
|
||||
linux,phandle = <0x00000017>;
|
||||
phandle = <0x00000017>;
|
||||
};
|
||||
};
|
||||
pinctrl@10080000 {
|
||||
compatible = "sifive,pinctrl0";
|
||||
reg = <0x00000000 0x10080000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
pwm@10020000 {
|
||||
compatible = "sifive,pwm0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x0000002a 0x0000002b 0x0000002c 0x0000002d>;
|
||||
reg = <0x00000000 0x10020000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000016>;
|
||||
sifive,approx-period = <0x000f4240>;
|
||||
#pwm-cells = <0x00000002>;
|
||||
linux,phandle = <0x00000018>;
|
||||
phandle = <0x00000018>;
|
||||
};
|
||||
pwm@10021000 {
|
||||
compatible = "sifive,pwm0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x0000002e 0x0000002f 0x00000030 0x00000031>;
|
||||
reg = <0x00000000 0x10021000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000016>;
|
||||
sifive,approx-period = <0x000f4240>;
|
||||
#pwm-cells = <0x00000002>;
|
||||
};
|
||||
pwmleds {
|
||||
compatible = "pwm-leds";
|
||||
heartbeat {
|
||||
pwms = <0x00000018 0x00000000 0x00000000>;
|
||||
max-brightness = <0x000000ff>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
mtd {
|
||||
pwms = <0x00000018 0x00000001 0x00000000>;
|
||||
max-brightness = <0x000000ff>;
|
||||
linux,default-trigger = "mtd";
|
||||
};
|
||||
netdev {
|
||||
pwms = <0x00000018 0x00000002 0x00000000>;
|
||||
max-brightness = <0x000000ff>;
|
||||
linux,default-trigger = "netdev";
|
||||
};
|
||||
panic {
|
||||
pwms = <0x00000018 0x00000003 0x00000000>;
|
||||
max-brightness = <0x000000ff>;
|
||||
linux,default-trigger = "panic";
|
||||
};
|
||||
};
|
||||
rom@1000 {
|
||||
compatible = "sifive,modeselect0";
|
||||
reg = <0x00000000 0x00001000 0x00000000 0x00001000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
rom@10000 {
|
||||
compatible = "sifive,maskrom0";
|
||||
reg = <0x00000000 0x00010000 0x00000000 0x00008000>;
|
||||
reg-names = "mem";
|
||||
};
|
||||
rom@a000000 {
|
||||
compatible = "ucbbar,cacheable-zero0";
|
||||
reg = <0x00000000 0x0a000000 0x00000000 0x02000000>;
|
||||
reg-names = "mem";
|
||||
linux,phandle = <0x0000000c>;
|
||||
phandle = <0x0000000c>;
|
||||
};
|
||||
serial@10010000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000004>;
|
||||
reg = <0x00000000 0x10010000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000016>;
|
||||
};
|
||||
serial@10011000 {
|
||||
compatible = "sifive,uart0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000005>;
|
||||
reg = <0x00000000 0x10011000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000016>;
|
||||
};
|
||||
spi@10040000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000033>;
|
||||
reg = <0x00000000 0x10040000 0x00000000 0x00001000 0x00000000 0x20000000 0x00000000 0x10000000>;
|
||||
reg-names = "control", "mem";
|
||||
clocks = <0x00000016>;
|
||||
#address-cells = <0x00000001>;
|
||||
#size-cells = <0x00000000>;
|
||||
flash@0 {
|
||||
compatible = "issi,is25wp256d", "jedec,spi-nor";
|
||||
reg = <0x00000000>;
|
||||
spi-max-frequency = <0x02faf080>;
|
||||
m25p,fast-read;
|
||||
spi-tx-bus-width = <0x00000004>;
|
||||
spi-rx-bus-width = <0x00000004>;
|
||||
};
|
||||
};
|
||||
spi@10041000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000034>;
|
||||
reg = <0x00000000 0x10041000 0x00000000 0x00001000 0x00000000 0x30000000 0x00000000 0x10000000>;
|
||||
reg-names = "control", "mem";
|
||||
clocks = <0x00000016>;
|
||||
#address-cells = <0x00000001>;
|
||||
#size-cells = <0x00000000>;
|
||||
};
|
||||
spi@10050000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0x0000000b>;
|
||||
interrupts = <0x00000006>;
|
||||
reg = <0x00000000 0x10050000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
clocks = <0x00000016>;
|
||||
#address-cells = <0x00000001>;
|
||||
#size-cells = <0x00000000>;
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0x00000000>;
|
||||
spi-max-frequency = <0x01312d00>;
|
||||
voltage-ranges = <0x00000ce4 0x00000ce4>;
|
||||
disable-wp;
|
||||
gpios = <0x00000015 0x0000000b 0x00000001>;
|
||||
};
|
||||
};
|
||||
teststatus@4000 {
|
||||
compatible = "sifive,test0";
|
||||
reg = <0x00000000 0x00004000 0x00000000 0x00001000>;
|
||||
reg-names = "control";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -906,8 +906,10 @@ def add_build_rules(devices, output):
|
||||
# print result to cmake variable
|
||||
print(';'.join(devices), file=output)
|
||||
|
||||
|
||||
MEGA_PAGE_SIZE = 0x200000
|
||||
|
||||
|
||||
def output_regions(args, devices, memory, kernel, irqs, fp):
|
||||
""" generate the device list for the C header file """
|
||||
memory = sorted(memory, key=lambda a: a.start)
|
||||
|
||||
Reference in New Issue
Block a user