diff --git a/libsel4/sel4_plat_include/rk3568/sel4/plat/api/constants.h b/libsel4/sel4_plat_include/rk3568/sel4/plat/api/constants.h
new file mode 100644
index 000000000..645547857
--- /dev/null
+++ b/libsel4/sel4_plat_include/rk3568/sel4/plat/api/constants.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025, UNSW
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <sel4/config.h>
+
+#if defined(CONFIG_ARM_CORTEX_A55)
+#include <sel4/arch/constants_cortex_a55.h>
+#else
+#error "unsupported core"
+#endif
+
diff --git a/src/plat/rk3568/config.cmake b/src/plat/rk3568/config.cmake
new file mode 100644
index 000000000..8e2b24541
--- /dev/null
+++ b/src/plat/rk3568/config.cmake
@@ -0,0 +1,31 @@
+#
+# Copyright 2025, UNSW
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+declare_platform(rk3568 KernelPlatformRock3b PLAT_rk3568 KernelArchARM)
+
+if(KernelPlatformRock3b)
+    declare_seL4_arch(aarch64)
+    set(KernelArmCortexA55 ON)
+    set(KernelArchArmV8a ON)
+    set(KernelArmGicV3 ON)
+    config_set(KernelARMPlatform ARM_PLAT rock3b)
+    list(APPEND KernelDTSList "tools/dts/rock3b.dts")
+    list(APPEND KernelDTSList "src/plat/rk3568/overlay-rock3b.dts")
+
+    declare_default_headers(
+        TIMER_FREQUENCY 24000000
+        MAX_IRQ 283
+        NUM_PPI 32
+        TIMER drivers/timer/arm_generic.h
+        INTERRUPT_CONTROLLER arch/machine/gic_v3.h
+        KERNEL_WCET 10u
+    )
+endif()
+
+add_sources(
+    DEP "KernelPlatformRock3b"
+    CFILES src/arch/arm/machine/gic_v3.c src/arch/arm/machine/l2c_nop.c
+)
diff --git a/src/plat/rk3568/overlay-rock3b.dts b/src/plat/rk3568/overlay-rock3b.dts
new file mode 100644
index 000000000..9a9110229
--- /dev/null
+++ b/src/plat/rk3568/overlay-rock3b.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025, UNSW
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+	chosen {
+		seL4,elfloader-devices =
+		    "serial2",
+		    &{/psci},
+		    &{/timer};
+
+		seL4,kernel-devices =
+		    "serial2",
+		    &{/interrupt-controller@fd400000},
+		    &{/timer};
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+        reg = <0x00 0x200000 0x00 0xecc9c000>;
+	};
+};
diff --git a/tools/dts/rock3b.dts b/tools/dts/rock3b.dts
new file mode 100644
index 000000000..ce8dd8234
--- /dev/null
+++ b/tools/dts/rock3b.dts
@@ -0,0 +1,3614 @@
+/*
+ * Copyright Linux Kernel Team
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * This file is derived from an intermediate build stage of the
+ * Linux kernel. The licenses of all input files to this process
+ * are compatible with GPL-2.0-only.
+ */
+
+/dts-v1/;
+
+/ {
+	interrupt-parent = <0x01>;
+	#address-cells = <0x02>;
+	#size-cells = <0x02>;
+	compatible = "radxa,rock-3b", "rockchip,rk3568";
+	model = "Radxa ROCK 3B";
+
+	aliases {
+		gpio0 = "/pinctrl/gpio@fdd60000";
+		gpio1 = "/pinctrl/gpio@fe740000";
+		gpio2 = "/pinctrl/gpio@fe750000";
+		gpio3 = "/pinctrl/gpio@fe760000";
+		gpio4 = "/pinctrl/gpio@fe770000";
+		i2c0 = "/i2c@fdd40000";
+		i2c1 = "/i2c@fe5a0000";
+		i2c2 = "/i2c@fe5b0000";
+		i2c3 = "/i2c@fe5c0000";
+		i2c4 = "/i2c@fe5d0000";
+		i2c5 = "/i2c@fe5e0000";
+		serial0 = "/serial@fdd50000";
+		serial1 = "/serial@fe650000";
+		serial2 = "/serial@fe660000";
+		serial3 = "/serial@fe670000";
+		serial4 = "/serial@fe680000";
+		serial5 = "/serial@fe690000";
+		serial6 = "/serial@fe6a0000";
+		serial7 = "/serial@fe6b0000";
+		serial8 = "/serial@fe6c0000";
+		serial9 = "/serial@fe6d0000";
+		spi0 = "/spi@fe610000";
+		spi1 = "/spi@fe620000";
+		spi2 = "/spi@fe630000";
+		spi3 = "/spi@fe640000";
+		ethernet0 = "/ethernet@fe2a0000";
+		ethernet1 = "/ethernet@fe010000";
+		mmc0 = "/mmc@fe310000";
+		mmc1 = "/mmc@fe2b0000";
+		mmc2 = "/mmc@fe000000";
+	};
+
+	memory@00000000 {
+		device_type = "memory";
+        reg = <0x00 0x200000 0x00 0xecc9c000>;
+	};
+
+	cpus {
+		#address-cells = <0x02>;
+		#size-cells = <0x00>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x00 0x00>;
+			clocks = <0x02 0x00>;
+			#cooling-cells = <0x02>;
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x03>;
+			operating-points-v2 = <0x04>;
+			cpu-supply = <0x05>;
+			phandle = <0x0a>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x00 0x100>;
+			#cooling-cells = <0x02>;
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x03>;
+			operating-points-v2 = <0x04>;
+			cpu-supply = <0x05>;
+			phandle = <0x0b>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x00 0x200>;
+			#cooling-cells = <0x02>;
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x03>;
+			operating-points-v2 = <0x04>;
+			cpu-supply = <0x05>;
+			phandle = <0x0c>;
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x00 0x300>;
+			#cooling-cells = <0x02>;
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x40>;
+			i-cache-sets = <0x80>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x40>;
+			d-cache-sets = <0x80>;
+			next-level-cache = <0x03>;
+			operating-points-v2 = <0x04>;
+			cpu-supply = <0x05>;
+			phandle = <0x0d>;
+		};
+	};
+
+	l3-cache {
+		compatible = "cache";
+		cache-level = <0x02>;
+		cache-unified;
+		cache-size = <0x80000>;
+		cache-line-size = <0x40>;
+		cache-sets = <0x200>;
+		phandle = <0x03>;
+	};
+
+	display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <0x06>;
+	};
+
+	firmware {
+
+		scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x82000010>;
+			shmem = <0x07>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <0x01>;
+				phandle = <0x02>;
+			};
+		};
+	};
+
+	hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "HDMI";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <0x100>;
+		status = "okay";
+
+		simple-audio-card,codec {
+			sound-dai = <0x08>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <0x09>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a55-pmu";
+		interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>;
+		interrupt-affinity = <0x0a 0x0b 0x0c 0x0d>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+
+		shmem@10f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x00 0x10f000 0x00 0x100>;
+			no-map;
+			phandle = <0x07>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
+		arm,no-tick-in-suspend;
+	};
+
+	xin24m {
+		compatible = "fixed-clock";
+		clock-frequency = <0x16e3600>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0x00>;
+		phandle = <0x1e>;
+	};
+
+	xin32k {
+		compatible = "fixed-clock";
+		clock-frequency = <0x8000>;
+		clock-output-names = "xin32k";
+		pinctrl-0 = <0x0e>;
+		pinctrl-names = "default";
+		#clock-cells = <0x00>;
+	};
+
+	sata@fc400000 {
+		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+		reg = <0x00 0xfc400000 0x00 0x1000>;
+		clocks = <0x0f 0x9b 0x0f 0x9c 0x0f 0x9d>;
+		clock-names = "sata", "pmalive", "rxoob";
+		interrupts = <0x00 0x5f 0x04>;
+		phys = <0x10 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		power-domains = <0x11 0x0f>;
+		status = "disabled";
+	};
+
+	sata@fc800000 {
+		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+		reg = <0x00 0xfc800000 0x00 0x1000>;
+		clocks = <0x0f 0xa0 0x0f 0xa1 0x0f 0xa2>;
+		clock-names = "sata", "pmalive", "rxoob";
+		interrupts = <0x00 0x60 0x04>;
+		phys = <0x12 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		power-domains = <0x11 0x0f>;
+		status = "disabled";
+	};
+
+	usb@fcc00000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x00 0xfcc00000 0x00 0x400000>;
+		interrupts = <0x00 0xa9 0x04>;
+		clocks = <0x0f 0xa6 0x0f 0xa7 0x0f 0xa5>;
+		clock-names = "ref_clk", "suspend_clk", "bus_clk";
+		dr_mode = "otg";
+		phy_type = "utmi_wide";
+		power-domains = <0x11 0x0f>;
+		resets = <0x0f 0x94>;
+		snps,dis_u2_susphy_quirk;
+		status = "okay";
+		phys = <0x13 0x14 0x04>;
+		phy-names = "usb2-phy", "usb3-phy";
+		extcon = <0x15>;
+	};
+
+	usb@fd000000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x00 0xfd000000 0x00 0x400000>;
+		interrupts = <0x00 0xaa 0x04>;
+		clocks = <0x0f 0xa9 0x0f 0xaa 0x0f 0xa8>;
+		clock-names = "ref_clk", "suspend_clk", "bus_clk";
+		dr_mode = "host";
+		phys = <0x16 0x10 0x04>;
+		phy-names = "usb2-phy", "usb3-phy";
+		phy_type = "utmi_wide";
+		power-domains = <0x11 0x0f>;
+		resets = <0x0f 0x95>;
+		snps,dis_u2_susphy_quirk;
+		status = "okay";
+	};
+
+	interrupt-controller@fd400000 {
+		compatible = "arm,gic-v3";
+		reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0x80000>;
+		interrupts = <0x01 0x09 0x04>;
+		interrupt-controller;
+		#interrupt-cells = <0x03>;
+		mbi-alias = <0x00 0xfd410000>;
+		mbi-ranges = <0x128 0x18>;
+		msi-controller;
+		ranges;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		dma-noncoherent;
+		phandle = <0x01>;
+
+		msi-controller@fd440000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x00 0xfd440000 0x00 0x20000>;
+			dma-noncoherent;
+			msi-controller;
+			#msi-cells = <0x01>;
+			phandle = <0x68>;
+		};
+	};
+
+	usb@fd800000 {
+		compatible = "generic-ehci";
+		reg = <0x00 0xfd800000 0x00 0x40000>;
+		interrupts = <0x00 0x82 0x04>;
+		clocks = <0x0f 0xbd 0x0f 0xbe 0x0f 0xbc>;
+		phys = <0x17>;
+		phy-names = "usb";
+		status = "okay";
+	};
+
+	usb@fd840000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfd840000 0x00 0x40000>;
+		interrupts = <0x00 0x83 0x04>;
+		clocks = <0x0f 0xbd 0x0f 0xbe 0x0f 0xbc>;
+		phys = <0x17>;
+		phy-names = "usb";
+		status = "okay";
+	};
+
+	usb@fd880000 {
+		compatible = "generic-ehci";
+		reg = <0x00 0xfd880000 0x00 0x40000>;
+		interrupts = <0x00 0x85 0x04>;
+		clocks = <0x0f 0xbf 0x0f 0xc0 0x0f 0xbc>;
+		phys = <0x18>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	usb@fd8c0000 {
+		compatible = "generic-ohci";
+		reg = <0x00 0xfd8c0000 0x00 0x40000>;
+		interrupts = <0x00 0x86 0x04>;
+		clocks = <0x0f 0xbf 0x0f 0xc0 0x0f 0xbc>;
+		phys = <0x18>;
+		phy-names = "usb";
+		status = "disabled";
+	};
+
+	syscon@fdc20000 {
+		compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
+		reg = <0x00 0xfdc20000 0x00 0x10000>;
+		phandle = <0x66>;
+
+		io-domains {
+			compatible = "rockchip,rk3568-pmu-io-voltage-domain";
+			status = "okay";
+			pmuio1-supply = <0x19>;
+			pmuio2-supply = <0x19>;
+			vccio1-supply = <0x1a>;
+			vccio2-supply = <0x1b>;
+			vccio3-supply = <0x1c>;
+			vccio4-supply = <0x1b>;
+			vccio5-supply = <0x1d>;
+			vccio6-supply = <0x1b>;
+			vccio7-supply = <0x1d>;
+		};
+	};
+
+	syscon@fdc50000 {
+		reg = <0x00 0xfdc50000 0x00 0x1000>;
+		compatible = "rockchip,rk3568-pipe-grf", "syscon";
+		phandle = <0xb4>;
+	};
+
+	syscon@fdc60000 {
+		compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
+		reg = <0x00 0xfdc60000 0x00 0x10000>;
+		phandle = <0x20>;
+	};
+
+	syscon@fdc80000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x00 0xfdc80000 0x00 0x1000>;
+		phandle = <0xb5>;
+	};
+
+	syscon@fdc90000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x00 0xfdc90000 0x00 0x1000>;
+		phandle = <0xb6>;
+	};
+
+	syscon@fdca0000 {
+		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
+		reg = <0x00 0xfdca0000 0x00 0x8000>;
+		phandle = <0xb7>;
+	};
+
+	syscon@fdca8000 {
+		compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
+		reg = <0x00 0xfdca8000 0x00 0x8000>;
+		phandle = <0xba>;
+	};
+
+	clock-controller@fdd00000 {
+		compatible = "rockchip,rk3568-pmucru";
+		reg = <0x00 0xfdd00000 0x00 0x1000>;
+		#clock-cells = <0x01>;
+		#reset-cells = <0x01>;
+		phandle = <0x1f>;
+	};
+
+	clock-controller@fdd20000 {
+		compatible = "rockchip,rk3568-cru";
+		reg = <0x00 0xfdd20000 0x00 0x1000>;
+		clocks = <0x1e>;
+		clock-names = "xin24m";
+		#clock-cells = <0x01>;
+		#reset-cells = <0x01>;
+		assigned-clocks = <0x1f 0x05 0x0f 0x04 0x1f 0x01>;
+		assigned-clock-rates = <0x8000 0x47868c00 0xbebc200>;
+		assigned-clock-parents = <0x1f 0x08>;
+		rockchip,grf = <0x20>;
+		phandle = <0x0f>;
+	};
+
+	i2c@fdd40000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x00 0xfdd40000 0x00 0x1000>;
+		interrupts = <0x00 0x2e 0x04>;
+		clocks = <0x1f 0x07 0x1f 0x2d>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <0x21>;
+		pinctrl-names = "default";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+
+		regulator@1c {
+			compatible = "tcs,tcs4525";
+			reg = <0x1c>;
+			fcs,suspend-voltage-selector = <0x01>;
+			regulator-name = "vdd_cpu";
+			regulator-always-on;
+			regulator-boot-on;
+			regulator-min-microvolt = "", "\f5";
+			regulator-max-microvolt = <0x118c30>;
+			regulator-ramp-delay = <0x8fc>;
+			vin-supply = <0x22>;
+			phandle = <0x05>;
+
+			regulator-state-mem {
+				regulator-off-in-suspend;
+			};
+		};
+
+		pmic@20 {
+			compatible = "rockchip,rk809";
+			reg = <0x20>;
+			assigned-clocks = <0x0f 0x48>;
+			assigned-clock-parents = <0x0f 0x196>;
+			#clock-cells = <0x01>;
+			clocks = <0x0f 0x48>;
+			clock-names = "mclk";
+			clock-output-names = "rk809-clkout1", "rk809-clkout2";
+			interrupt-parent = <0x23>;
+			interrupts = <0x03 0x08>;
+			pinctrl-names = "default";
+			pinctrl-0 = <0x24 0x25>;
+			#sound-dai-cells = <0x00>;
+			system-power-controller;
+			wakeup-source;
+			vcc1-supply = <0x26>;
+			vcc2-supply = <0x26>;
+			vcc3-supply = <0x26>;
+			vcc4-supply = <0x26>;
+			vcc5-supply = <0x26>;
+			vcc6-supply = <0x26>;
+			vcc7-supply = <0x26>;
+			vcc8-supply = <0x26>;
+			vcc9-supply = <0x26>;
+			phandle = <0xde>;
+
+			regulators {
+
+				DCDC_REG1 {
+					regulator-name = "vdd_logic";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-initial-mode = <0x02>;
+					regulator-min-microvolt = <0x7a120>;
+					regulator-max-microvolt = <0x149970>;
+					regulator-ramp-delay = <0x1771>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG2 {
+					regulator-name = "vdd_gpu";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-initial-mode = <0x02>;
+					regulator-min-microvolt = <0x7a120>;
+					regulator-max-microvolt = <0x149970>;
+					regulator-ramp-delay = <0x1771>;
+					phandle = <0x48>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG3 {
+					regulator-name = "vcc_ddr";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-initial-mode = <0x02>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+					};
+				};
+
+				DCDC_REG4 {
+					regulator-name = "vdd_npu";
+					regulator-initial-mode = <0x02>;
+					regulator-min-microvolt = <0x7a120>;
+					regulator-max-microvolt = <0x149970>;
+					regulator-ramp-delay = <0x1771>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				DCDC_REG5 {
+					regulator-name = "vcc_1v8";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0x1b>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG1 {
+					regulator-name = "vdda0v9_image";
+					regulator-min-microvolt = <0xdbba0>;
+					regulator-max-microvolt = <0xdbba0>;
+					phandle = <0x62>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG2 {
+					regulator-name = "vdda_0v9";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xdbba0>;
+					regulator-max-microvolt = <0xdbba0>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG3 {
+					regulator-name = "vdda0v9_pmu";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0xdbba0>;
+					regulator-max-microvolt = <0xdbba0>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0xdbba0>;
+					};
+				};
+
+				LDO_REG4 {
+					regulator-name = "vccio_acodec";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x325aa0>;
+					regulator-max-microvolt = <0x325aa0>;
+					phandle = <0x1a>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG5 {
+					regulator-name = "vccio_sd";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x325aa0>;
+					phandle = <0x1c>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG6 {
+					regulator-name = "vcc3v3_pmu";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x325aa0>;
+					regulator-max-microvolt = <0x325aa0>;
+					phandle = <0x19>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x325aa0>;
+					};
+				};
+
+				LDO_REG7 {
+					regulator-name = "vcca_1v8";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0xa7>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				LDO_REG8 {
+					regulator-name = "vcca1v8_pmu";
+					regulator-always-on;
+					regulator-boot-on;
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+
+					regulator-state-mem {
+						regulator-on-in-suspend;
+						regulator-suspend-microvolt = <0x1b7740>;
+					};
+				};
+
+				LDO_REG9 {
+					regulator-name = "vcca1v8_image";
+					regulator-min-microvolt = <0x1b7740>;
+					regulator-max-microvolt = <0x1b7740>;
+					phandle = <0x63>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				SWITCH_REG1 {
+					regulator-name = "vcc_3v3";
+					regulator-always-on;
+					regulator-boot-on;
+					phandle = <0x1d>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+
+				SWITCH_REG2 {
+					regulator-name = "vcc3v3_sd";
+					regulator-always-on;
+					regulator-boot-on;
+					phandle = <0x6e>;
+
+					regulator-state-mem {
+						regulator-off-in-suspend;
+					};
+				};
+			};
+		};
+	};
+
+	serial@fdd50000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfdd50000 0x00 0x100>;
+		interrupts = <0x00 0x74 0x04>;
+		clocks = <0x1f 0x0b 0x1f 0x2c>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x00 0x27 0x01>;
+		pinctrl-0 = <0x28>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	pwm@fdd70000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfdd70000 0x00 0x10>;
+		clocks = <0x1f 0x0d 0x1f 0x30>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0x29>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fdd70010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfdd70010 0x00 0x10>;
+		clocks = <0x1f 0x0d 0x1f 0x30>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0x2a>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fdd70020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfdd70020 0x00 0x10>;
+		clocks = <0x1f 0x0d 0x1f 0x30>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0x2b>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fdd70030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfdd70030 0x00 0x10>;
+		clocks = <0x1f 0x0d 0x1f 0x30>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0x2c>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	power-management@fdd90000 {
+		compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
+		reg = <0x00 0xfdd90000 0x00 0x1000>;
+
+		power-controller {
+			compatible = "rockchip,rk3568-power-controller";
+			#power-domain-cells = <0x01>;
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x11>;
+
+			power-domain@7 {
+				reg = <0x07>;
+				clocks = <0x0f 0x19 0x0f 0x1a>;
+				pm_qos = <0x2d>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@8 {
+				reg = <0x08>;
+				clocks = <0x0f 0xcc 0x0f 0xcd>;
+				pm_qos = <0x2e 0x2f 0x30>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@9 {
+				reg = <0x09>;
+				clocks = <0x0f 0xda 0x0f 0xdb 0x0f 0xdc>;
+				pm_qos = <0x31 0x32 0x33>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@10 {
+				reg = <0x0a>;
+				clocks = <0x0f 0xf1 0x0f 0xf2>;
+				pm_qos = <0x34 0x35 0x36 0x37 0x38 0x39>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@11 {
+				reg = <0x0b>;
+				clocks = <0x0f 0xed>;
+				pm_qos = <0x3a>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@13 {
+				clocks = <0x0f 0x107>;
+				reg = <0x0d>;
+				pm_qos = <0x3b>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@14 {
+				reg = <0x0e>;
+				clocks = <0x0f 0x102>;
+				pm_qos = <0x3c 0x3d 0x3e>;
+				#power-domain-cells = <0x00>;
+			};
+
+			power-domain@15 {
+				reg = <0x0f>;
+				clocks = <0x0f 0x7f>;
+				pm_qos = <0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46>;
+				#power-domain-cells = <0x00>;
+			};
+		};
+	};
+
+	gpu@fde60000 {
+		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
+		reg = <0x00 0xfde60000 0x00 0x4000>;
+		interrupts = <0x00 0x28 0x04 0x00 0x29 0x04 0x00 0x27 0x04>;
+		interrupt-names = "job", "mmu", "gpu";
+		clocks = <0x02 0x01 0x0f 0x1b>;
+		clock-names = "gpu", "bus";
+		#cooling-cells = <0x02>;
+		power-domains = <0x11 0x07>;
+		status = "okay";
+		operating-points-v2 = <0x47>;
+		mali-supply = <0x48>;
+		phandle = <0xa4>;
+	};
+
+	video-codec@fdea0400 {
+		compatible = "rockchip,rk3568-vpu";
+		reg = <0x00 0xfdea0000 0x00 0x800>;
+		interrupts = <0x00 0x8b 0x04>;
+		interrupt-names = "vdpu";
+		clocks = <0x0f 0xee 0x0f 0xef>;
+		clock-names = "aclk", "hclk";
+		iommus = <0x49>;
+		power-domains = <0x11 0x0b>;
+	};
+
+	iommu@fdea0800 {
+		compatible = "rockchip,rk3568-iommu";
+		reg = <0x00 0xfdea0800 0x00 0x40>;
+		interrupts = <0x00 0x8a 0x04>;
+		clock-names = "aclk", "iface";
+		clocks = <0x0f 0xee 0x0f 0xef>;
+		power-domains = <0x11 0x0b>;
+		#iommu-cells = <0x00>;
+		phandle = <0x49>;
+	};
+
+	rga@fdeb0000 {
+		compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
+		reg = <0x00 0xfdeb0000 0x00 0x180>;
+		interrupts = <0x00 0x5a 0x04>;
+		clocks = <0x0f 0xf3 0x0f 0xf4 0x0f 0xf5>;
+		clock-names = "aclk", "hclk", "sclk";
+		resets = <0x0f 0x126 0x0f 0x124 0x0f 0x125>;
+		reset-names = "core", "axi", "ahb";
+		power-domains = <0x11 0x0a>;
+	};
+
+	video-codec@fdee0000 {
+		compatible = "rockchip,rk3568-vepu";
+		reg = <0x00 0xfdee0000 0x00 0x800>;
+		interrupts = <0x00 0x40 0x04>;
+		clocks = <0x0f 0xfd 0x0f 0xfe>;
+		clock-names = "aclk", "hclk";
+		iommus = <0x4a>;
+		power-domains = <0x11 0x0a>;
+	};
+
+	iommu@fdee0800 {
+		compatible = "rockchip,rk3568-iommu";
+		reg = <0x00 0xfdee0800 0x00 0x40>;
+		interrupts = <0x00 0x3f 0x04>;
+		clocks = <0x0f 0xfd 0x0f 0xfe>;
+		clock-names = "aclk", "iface";
+		power-domains = <0x11 0x0a>;
+		#iommu-cells = <0x00>;
+		phandle = <0x4a>;
+	};
+
+	mmc@fe000000 {
+		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe000000 0x00 0x4000>;
+		interrupts = <0x00 0x64 0x04>;
+		clocks = <0x0f 0xc1 0x0f 0xc2 0x0f 0x18e 0x0f 0x18f>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0x8f0d180>;
+		resets = <0x0f 0xeb>;
+		reset-names = "reset";
+		status = "disabled";
+		bus-width = <0x04>;
+		cap-sd-highspeed;
+		cap-sdio-irq;
+		keep-power-in-suspend;
+		mmc-pwrseq = <0x4b>;
+		non-removable;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x4c 0x4d 0x4e>;
+		sd-uhs-sdr104;
+		vmmc-supply = <0x4f>;
+		vqmmc-supply = <0x1b>;
+	};
+
+	ethernet@fe010000 {
+		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+		reg = <0x00 0xfe010000 0x00 0x10000>;
+		interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		clocks = <0x0f 0x186 0x0f 0x189 0x0f 0x189 0x0f 0xc7 0x0f 0xc3 0x0f 0xc4 0x0f 0x189 0x0f 0xc8>;
+		clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref";
+		resets = <0x0f 0xec>;
+		reset-names = "stmmaceth";
+		rockchip,grf = <0x20>;
+		snps,axi-config = <0x50>;
+		snps,mixed-burst;
+		snps,mtl-rx-config = <0x51>;
+		snps,mtl-tx-config = <0x52>;
+		snps,tso;
+		status = "okay";
+		assigned-clocks = <0x0f 0x189 0x0f 0x186>;
+		assigned-clock-parents = <0x0f 0x187 0x0f 0xc5>;
+		clock_in_out = "input";
+		phy-handle = <0x53>;
+		phy-mode = "rgmii-id";
+		phy-supply = <0x1d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x54 0x55 0x56 0x57 0x58 0x59>;
+
+		mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			ethernet-phy@1 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <0x01>;
+				reset-assert-us = <0x4e20>;
+				reset-deassert-us = <0xc350>;
+				reset-gpios = <0x5a 0x08 0x01>;
+				phandle = <0x53>;
+			};
+		};
+
+		stmmac-axi-config {
+			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+			snps,rd_osr_lmt = <0x08>;
+			snps,wr_osr_lmt = <0x04>;
+			phandle = <0x50>;
+		};
+
+		rx-queues-config {
+			snps,rx-queues-to-use = <0x01>;
+			phandle = <0x51>;
+
+			queue0 {
+			};
+		};
+
+		tx-queues-config {
+			snps,tx-queues-to-use = <0x01>;
+			phandle = <0x52>;
+
+			queue0 {
+			};
+		};
+	};
+
+	vop@fe040000 {
+		reg = <0x00 0xfe040000 0x00 0x3000 0x00 0xfe044000 0x00 0x1000>;
+		reg-names = "vop", "gamma-lut";
+		interrupts = <0x00 0x94 0x04>;
+		clocks = <0x0f 0xdd 0x0f 0xde 0x0f 0xdf 0x0f 0xe0 0x0f 0xe1>;
+		clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
+		iommus = <0x5b>;
+		power-domains = <0x11 0x09>;
+		rockchip,grf = <0x20>;
+		status = "okay";
+		compatible = "rockchip,rk3568-vop";
+		assigned-clocks = <0x0f 0xdf 0x0f 0xe0>;
+		assigned-clock-parents = <0x1f 0x02 0x0f 0x05>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+			phandle = <0x06>;
+
+			port@0 {
+				reg = <0x00>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+
+				endpoint@2 {
+					reg = <0x02>;
+					remote-endpoint = <0x5c>;
+					phandle = <0x64>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+			};
+
+			port@2 {
+				reg = <0x02>;
+				#address-cells = <0x01>;
+				#size-cells = <0x00>;
+			};
+		};
+	};
+
+	iommu@fe043e00 {
+		compatible = "rockchip,rk3568-iommu";
+		reg = <0x00 0xfe043e00 0x00 0x100 0x00 0xfe043f00 0x00 0x100>;
+		interrupts = <0x00 0x94 0x04>;
+		clocks = <0x0f 0xdd 0x0f 0xde>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0x00>;
+		power-domains = <0x11 0x09>;
+		status = "okay";
+		phandle = <0x5b>;
+	};
+
+	dsi@fe060000 {
+		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x00 0xfe060000 0x00 0x10000>;
+		interrupts = <0x00 0x44 0x04>;
+		clock-names = "pclk";
+		clocks = <0x0f 0xe8>;
+		phy-names = "dphy";
+		phys = <0x5d>;
+		power-domains = <0x11 0x09>;
+		reset-names = "apb";
+		resets = <0x0f 0x110>;
+		rockchip,grf = <0x20>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+			};
+
+			port@1 {
+				reg = <0x01>;
+			};
+		};
+	};
+
+	dsi@fe070000 {
+		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x00 0xfe070000 0x00 0x10000>;
+		interrupts = <0x00 0x45 0x04>;
+		clock-names = "pclk";
+		clocks = <0x0f 0xe9>;
+		phy-names = "dphy";
+		phys = <0x5e>;
+		power-domains = <0x11 0x09>;
+		reset-names = "apb";
+		resets = <0x0f 0x111>;
+		rockchip,grf = <0x20>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+			};
+
+			port@1 {
+				reg = <0x01>;
+			};
+		};
+	};
+
+	hdmi@fe0a0000 {
+		compatible = "rockchip,rk3568-dw-hdmi";
+		reg = <0x00 0xfe0a0000 0x00 0x20000>;
+		interrupts = <0x00 0x2d 0x04>;
+		clocks = <0x0f 0xe6 0x0f 0xe7 0x0f 0x193 0x1f 0x28 0x0f 0xda>;
+		clock-names = "iahb", "isfr", "cec", "ref";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x5f 0x60 0x61>;
+		power-domains = <0x11 0x09>;
+		reg-io-width = <0x04>;
+		rockchip,grf = <0x20>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		avdd-0v9-supply = <0x62>;
+		avdd-1v8-supply = <0x63>;
+		phandle = <0x08>;
+
+		ports {
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			port@0 {
+				reg = <0x00>;
+
+				endpoint {
+					remote-endpoint = <0x64>;
+					phandle = <0x5c>;
+				};
+			};
+
+			port@1 {
+				reg = <0x01>;
+
+				endpoint {
+					remote-endpoint = <0x65>;
+					phandle = <0xd8>;
+				};
+			};
+		};
+	};
+
+	qos@fe128000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe128000 0x00 0x20>;
+		phandle = <0x2d>;
+	};
+
+	qos@fe138080 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe138080 0x00 0x20>;
+		phandle = <0x3c>;
+	};
+
+	qos@fe138100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe138100 0x00 0x20>;
+		phandle = <0x3d>;
+	};
+
+	qos@fe138180 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe138180 0x00 0x20>;
+		phandle = <0x3e>;
+	};
+
+	qos@fe148000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe148000 0x00 0x20>;
+		phandle = <0x2e>;
+	};
+
+	qos@fe148080 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe148080 0x00 0x20>;
+		phandle = <0x2f>;
+	};
+
+	qos@fe148100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe148100 0x00 0x20>;
+		phandle = <0x30>;
+	};
+
+	qos@fe150000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe150000 0x00 0x20>;
+		phandle = <0x3a>;
+	};
+
+	qos@fe158000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe158000 0x00 0x20>;
+		phandle = <0x34>;
+	};
+
+	qos@fe158100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe158100 0x00 0x20>;
+		phandle = <0x35>;
+	};
+
+	qos@fe158180 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe158180 0x00 0x20>;
+		phandle = <0x36>;
+	};
+
+	qos@fe158200 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe158200 0x00 0x20>;
+		phandle = <0x37>;
+	};
+
+	qos@fe158280 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe158280 0x00 0x20>;
+		phandle = <0x38>;
+	};
+
+	qos@fe158300 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe158300 0x00 0x20>;
+		phandle = <0x39>;
+	};
+
+	qos@fe180000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe180000 0x00 0x20>;
+	};
+
+	qos@fe190000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190000 0x00 0x20>;
+		phandle = <0x3f>;
+	};
+
+	qos@fe190280 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190280 0x00 0x20>;
+		phandle = <0x43>;
+	};
+
+	qos@fe190300 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190300 0x00 0x20>;
+		phandle = <0x44>;
+	};
+
+	qos@fe190380 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190380 0x00 0x20>;
+		phandle = <0x45>;
+	};
+
+	qos@fe190400 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190400 0x00 0x20>;
+		phandle = <0x46>;
+	};
+
+	qos@fe198000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe198000 0x00 0x20>;
+		phandle = <0x3b>;
+	};
+
+	qos@fe1a8000 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe1a8000 0x00 0x20>;
+		phandle = <0x31>;
+	};
+
+	qos@fe1a8080 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe1a8080 0x00 0x20>;
+		phandle = <0x32>;
+	};
+
+	qos@fe1a8100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe1a8100 0x00 0x20>;
+		phandle = <0x33>;
+	};
+
+	dfi@fe230000 {
+		compatible = "rockchip,rk3568-dfi";
+		reg = <0x00 0xfe230000 0x00 0x400>;
+		interrupts = <0x00 0x0b 0x04>;
+		rockchip,pmu = <0x66>;
+	};
+
+	pcie@fe260000 {
+		compatible = "rockchip,rk3568-pcie";
+		reg = <0x03 0xc0000000 0x00 0x400000 0x00 0xfe260000 0x00 0x10000 0x00 0xf4000000 0x00 0x100000>;
+		reg-names = "dbi", "apb", "config";
+		interrupts = <0x00 0x4b 0x04 0x00 0x4a 0x04 0x00 0x49 0x04 0x00 0x48 0x04 0x00 0x47 0x04>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		bus-range = <0x00 0x0f>;
+		clocks = <0x0f 0x81 0x0f 0x82 0x0f 0x83 0x0f 0x84 0x0f 0x85>;
+		clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
+		device_type = "pci";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0x67 0x00 0x00 0x00 0x00 0x02 0x67 0x01 0x00 0x00 0x00 0x03 0x67 0x02 0x00 0x00 0x00 0x04 0x67 0x03>;
+		linux,pci-domain = <0x00>;
+		num-ib-windows = <0x06>;
+		num-ob-windows = <0x02>;
+		max-link-speed = <0x02>;
+		msi-map = <0x00 0x68 0x00 0x1000>;
+		num-lanes = <0x01>;
+		phys = <0x12 0x02>;
+		phy-names = "pcie-phy";
+		power-domains = <0x11 0x0f>;
+		ranges = <0x1000000 0x00 0xf4100000 0x00 0xf4100000 0x00 0x100000 0x2000000 0x00 0xf4200000 0x00 0xf4200000 0x00 0x1e00000 0x3000000 0x00 0x40000000 0x03 0x00 0x00 0x40000000>;
+		resets = <0x0f 0xa1>;
+		reset-names = "pipe";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x69>;
+		reset-gpios = <0x5a 0x11 0x00>;
+		vpcie3v3-supply = <0x4f>;
+
+		legacy-interrupt-controller {
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-controller;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0x48 0x01>;
+			phandle = <0x67>;
+		};
+	};
+
+	mmc@fe2b0000 {
+		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe2b0000 0x00 0x4000>;
+		interrupts = <0x00 0x62 0x04>;
+		clocks = <0x0f 0xb0 0x0f 0xb1 0x0f 0x18a 0x0f 0x18b>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0x8f0d180>;
+		resets = <0x0f 0xd4>;
+		reset-names = "reset";
+		status = "okay";
+		bus-width = <0x04>;
+		cap-sd-highspeed;
+		disable-wp;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x6a 0x6b 0x6c 0x6d>;
+		vmmc-supply = <0x6e>;
+		vqmmc-supply = <0x1c>;
+	};
+
+	mmc@fe2c0000 {
+		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0x00 0xfe2c0000 0x00 0x4000>;
+		interrupts = <0x00 0x63 0x04>;
+		clocks = <0x0f 0xb2 0x0f 0xb3 0x0f 0x18c 0x0f 0x18d>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <0x8f0d180>;
+		resets = <0x0f 0xd6>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
+	spi@fe300000 {
+		compatible = "rockchip,sfc";
+		reg = <0x00 0xfe300000 0x00 0x4000>;
+		interrupts = <0x00 0x65 0x04>;
+		clocks = <0x0f 0x78 0x0f 0x76>;
+		clock-names = "clk_sfc", "hclk_sfc";
+		pinctrl-0 = <0x6f>;
+		pinctrl-names = "default";
+		status = "okay";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+
+		flash@0 {
+			compatible = "jedec,spi-nor";
+			reg = <0x00>;
+			spi-max-frequency = <0x632ea00>;
+			spi-rx-bus-width = <0x04>;
+			spi-tx-bus-width = <0x01>;
+		};
+	};
+
+	mmc@fe310000 {
+		compatible = "rockchip,rk3568-dwcmshc";
+		reg = <0x00 0xfe310000 0x00 0x10000>;
+		interrupts = <0x00 0x13 0x04>;
+		assigned-clocks = <0x0f 0x7b 0x0f 0x7d>;
+		assigned-clock-rates = <0xbebc200 0x16e3600>;
+		clocks = <0x0f 0x7c 0x0f 0x7a 0x0f 0x79 0x0f 0x7b 0x0f 0x7d>;
+		clock-names = "core", "bus", "axi", "block", "timer";
+		status = "okay";
+		bus-width = <0x08>;
+		cap-mmc-highspeed;
+		max-frequency = <0xbebc200>;
+		mmc-hs200-1_8v;
+		non-removable;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x70 0x71 0x72 0x73>;
+		vmmc-supply = <0x1d>;
+		vqmmc-supply = <0x1b>;
+	};
+
+	rng@fe388000 {
+		compatible = "rockchip,rk3568-rng";
+		reg = <0x00 0xfe388000 0x00 0x4000>;
+		clocks = <0x0f 0x70 0x0f 0x6f>;
+		clock-names = "core", "ahb";
+		resets = <0x0f 0x6d>;
+		status = "okay";
+	};
+
+	i2s@fe400000 {
+		compatible = "rockchip,rk3568-i2s-tdm";
+		reg = <0x00 0xfe400000 0x00 0x1000>;
+		interrupts = <0x00 0x34 0x04>;
+		assigned-clocks = <0x0f 0x3d 0x0f 0x41>;
+		assigned-clock-rates = <0x46cf7100 0x46cf7100>;
+		clocks = <0x0f 0x3f 0x0f 0x43 0x0f 0x39>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <0x74 0x00>;
+		dma-names = "tx";
+		resets = <0x0f 0x50 0x0f 0x51>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,grf = <0x20>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		phandle = <0x09>;
+	};
+
+	i2s@fe410000 {
+		compatible = "rockchip,rk3568-i2s-tdm";
+		reg = <0x00 0xfe410000 0x00 0x1000>;
+		interrupts = <0x00 0x35 0x04>;
+		assigned-clocks = <0x0f 0x45 0x0f 0x49>;
+		assigned-clock-rates = <0x46cf7100 0x46cf7100>;
+		clocks = <0x0f 0x47 0x0f 0x4b 0x0f 0x3a>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <0x74 0x03 0x74 0x02>;
+		dma-names = "rx", "tx";
+		resets = <0x0f 0x52 0x0f 0x53>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,grf = <0x20>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x75 0x76 0x77 0x78>;
+		#sound-dai-cells = <0x00>;
+		status = "okay";
+		rockchip,trcm-sync-tx-only;
+		phandle = <0xe0>;
+	};
+
+	i2s@fe420000 {
+		compatible = "rockchip,rk3568-i2s-tdm";
+		reg = <0x00 0xfe420000 0x00 0x1000>;
+		interrupts = <0x00 0x36 0x04>;
+		assigned-clocks = <0x0f 0x4d>;
+		assigned-clock-rates = <0x46cf7100>;
+		clocks = <0x0f 0x4f 0x0f 0x4f 0x0f 0x3b>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <0x74 0x04 0x74 0x05>;
+		dma-names = "tx", "rx";
+		resets = <0x0f 0x54>;
+		reset-names = "tx-m";
+		rockchip,grf = <0x20>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0x79 0x7a 0x7b 0x7c>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2s@fe430000 {
+		compatible = "rockchip,rk3568-i2s-tdm";
+		reg = <0x00 0xfe430000 0x00 0x1000>;
+		interrupts = <0x00 0x37 0x04>;
+		clocks = <0x0f 0x53 0x0f 0x57 0x0f 0x3c>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <0x74 0x06 0x74 0x07>;
+		dma-names = "tx", "rx";
+		resets = <0x0f 0x55 0x0f 0x56>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,grf = <0x20>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	pdm@fe440000 {
+		compatible = "rockchip,rk3568-pdm";
+		reg = <0x00 0xfe440000 0x00 0x1000>;
+		interrupts = <0x00 0x4c 0x04>;
+		clocks = <0x0f 0x5a 0x0f 0x59>;
+		clock-names = "pdm_clk", "pdm_hclk";
+		dmas = <0x74 0x09>;
+		dma-names = "rx";
+		pinctrl-0 = <0x7d 0x7e 0x7f 0x80 0x81 0x82>;
+		pinctrl-names = "default";
+		resets = <0x0f 0x58>;
+		reset-names = "pdm-m";
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spdif@fe460000 {
+		compatible = "rockchip,rk3568-spdif";
+		reg = <0x00 0xfe460000 0x00 0x1000>;
+		interrupts = <0x00 0x66 0x04>;
+		clock-names = "mclk", "hclk";
+		clocks = <0x0f 0x5f 0x0f 0x5c>;
+		dmas = <0x74 0x01>;
+		dma-names = "tx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x83>;
+		#sound-dai-cells = <0x00>;
+		status = "disabled";
+	};
+
+	dma-controller@fe530000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0x00 0xfe530000 0x00 0x4000>;
+		interrupts = <0x00 0x0e 0x04 0x00 0x0d 0x04>;
+		arm,pl330-periph-burst;
+		clocks = <0x0f 0x10d>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		phandle = <0x27>;
+	};
+
+	dma-controller@fe550000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0x00 0xfe550000 0x00 0x4000>;
+		interrupts = <0x00 0x10 0x04 0x00 0x0f 0x04>;
+		arm,pl330-periph-burst;
+		clocks = <0x0f 0x10d>;
+		clock-names = "apb_pclk";
+		#dma-cells = <0x01>;
+		phandle = <0x74>;
+	};
+
+	i2c@fe5a0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x00 0xfe5a0000 0x00 0x1000>;
+		interrupts = <0x00 0x2f 0x04>;
+		clocks = <0x0f 0x148 0x0f 0x147>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <0x84>;
+		pinctrl-names = "default";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2c@fe5b0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x00 0xfe5b0000 0x00 0x1000>;
+		interrupts = <0x00 0x30 0x04>;
+		clocks = <0x0f 0x14a 0x0f 0x149>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <0x85>;
+		pinctrl-names = "default";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2c@fe5c0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x00 0xfe5c0000 0x00 0x1000>;
+		interrupts = <0x00 0x31 0x04>;
+		clocks = <0x0f 0x14c 0x0f 0x14b>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <0x86>;
+		pinctrl-names = "default";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2c@fe5d0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x00 0xfe5d0000 0x00 0x1000>;
+		interrupts = <0x00 0x32 0x04>;
+		clocks = <0x0f 0x14e 0x0f 0x14d>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <0x87>;
+		pinctrl-names = "default";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	i2c@fe5e0000 {
+		compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+		reg = <0x00 0xfe5e0000 0x00 0x1000>;
+		interrupts = <0x00 0x33 0x04>;
+		clocks = <0x0f 0x150 0x0f 0x14f>;
+		clock-names = "i2c", "pclk";
+		pinctrl-0 = <0x88>;
+		pinctrl-names = "default";
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "okay";
+
+		rtc@51 {
+			compatible = "haoyu,hym8563";
+			reg = <0x51>;
+			interrupt-parent = <0x23>;
+			interrupts = <0x1b 0x08>;
+			#clock-cells = <0x00>;
+			clock-output-names = "rtcic_32kout";
+			pinctrl-names = "default";
+			pinctrl-0 = <0x89>;
+			wakeup-source;
+		};
+	};
+
+	watchdog@fe600000 {
+		compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
+		reg = <0x00 0xfe600000 0x00 0x100>;
+		interrupts = <0x00 0x95 0x04>;
+		clocks = <0x0f 0x116 0x0f 0x115>;
+		clock-names = "tclk", "pclk";
+	};
+
+	spi@fe610000 {
+		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+		reg = <0x00 0xfe610000 0x00 0x1000>;
+		interrupts = <0x00 0x67 0x04>;
+		clocks = <0x0f 0x152 0x0f 0x151>;
+		clock-names = "spiclk", "apb_pclk";
+		dmas = <0x27 0x14 0x27 0x15>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x8a 0x8b 0x8c>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spi@fe620000 {
+		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+		reg = <0x00 0xfe620000 0x00 0x1000>;
+		interrupts = <0x00 0x68 0x04>;
+		clocks = <0x0f 0x154 0x0f 0x153>;
+		clock-names = "spiclk", "apb_pclk";
+		dmas = <0x27 0x16 0x27 0x17>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x8d 0x8e 0x8f>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spi@fe630000 {
+		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+		reg = <0x00 0xfe630000 0x00 0x1000>;
+		interrupts = <0x00 0x69 0x04>;
+		clocks = <0x0f 0x156 0x0f 0x155>;
+		clock-names = "spiclk", "apb_pclk";
+		dmas = <0x27 0x18 0x27 0x19>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x90 0x91 0x92>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	spi@fe640000 {
+		compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+		reg = <0x00 0xfe640000 0x00 0x1000>;
+		interrupts = <0x00 0x6a 0x04>;
+		clocks = <0x0f 0x158 0x0f 0x157>;
+		clock-names = "spiclk", "apb_pclk";
+		dmas = <0x27 0x1a 0x27 0x1b>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <0x93 0x94 0x95>;
+		#address-cells = <0x01>;
+		#size-cells = <0x00>;
+		status = "disabled";
+	};
+
+	serial@fe650000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe650000 0x00 0x100>;
+		interrupts = <0x00 0x75 0x04>;
+		clocks = <0x0f 0x11f 0x0f 0x11c>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x02 0x27 0x03>;
+		pinctrl-0 = <0x96>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	serial@fe660000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe660000 0x00 0x100>;
+		interrupts = <0x00 0x76 0x04>;
+		clocks = <0x0f 0x123 0x0f 0x120>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x04 0x27 0x05>;
+		pinctrl-0 = <0x97>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "okay";
+	};
+
+	serial@fe670000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe670000 0x00 0x100>;
+		interrupts = <0x00 0x77 0x04>;
+		clocks = <0x0f 0x127 0x0f 0x124>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x06 0x27 0x07>;
+		pinctrl-0 = <0x98>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	serial@fe680000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe680000 0x00 0x100>;
+		interrupts = <0x00 0x78 0x04>;
+		clocks = <0x0f 0x12b 0x0f 0x128>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x08 0x27 0x09>;
+		pinctrl-0 = <0x99>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	serial@fe690000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe690000 0x00 0x100>;
+		interrupts = <0x00 0x79 0x04>;
+		clocks = <0x0f 0x12f 0x0f 0x12c>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x0a 0x27 0x0b>;
+		pinctrl-0 = <0x9a>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	serial@fe6a0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe6a0000 0x00 0x100>;
+		interrupts = <0x00 0x7a 0x04>;
+		clocks = <0x0f 0x133 0x0f 0x130>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x0c 0x27 0x0d>;
+		pinctrl-0 = <0x9b>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	serial@fe6b0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe6b0000 0x00 0x100>;
+		interrupts = <0x00 0x7b 0x04>;
+		clocks = <0x0f 0x137 0x0f 0x134>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x0e 0x27 0x0f>;
+		pinctrl-0 = <0x9c>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+	serial@fe6c0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe6c0000 0x00 0x100>;
+		interrupts = <0x00 0x7c 0x04>;
+		clocks = <0x0f 0x13b 0x0f 0x138>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x10 0x27 0x11>;
+		pinctrl-0 = <0x9d 0x9e 0x9f>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+		uart-has-rtscts;
+	};
+
+	serial@fe6d0000 {
+		compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+		reg = <0x00 0xfe6d0000 0x00 0x100>;
+		interrupts = <0x00 0x7d 0x04>;
+		clocks = <0x0f 0x13f 0x0f 0x13c>;
+		clock-names = "baudclk", "apb_pclk";
+		dmas = <0x27 0x12 0x27 0x13>;
+		pinctrl-0 = <0xa0>;
+		pinctrl-names = "default";
+		reg-io-width = <0x04>;
+		reg-shift = <0x02>;
+		status = "disabled";
+	};
+
+    /*
+        Treating the 6 peripherals as a single timer device with 6 channels. For future reference timer blocks are 0x20 and sit next to one another from a base address.
+    */
+	rktimer@fe5f0000 {
+		compatible = "rockchip,rk3568-timer";
+		reg = <0x00 0xfe5f0000 0x00 0x1000>;
+		interrupts = <0x00 0x6d 0x01 0x00 0x6e 0x01 0x00 0x6f 0x04
+		              0x00 0x70 0x04 0x00 0x71 0x04 0x00 0x72 0x04>;
+		clock-names = "xin24m";
+	};
+
+	thermal-zones {
+
+		cpu-thermal {
+			polling-delay-passive = <0x64>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0xa1 0x00>;
+
+			trips {
+
+				cpu_alert0 {
+					temperature = <0x11170>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0xa2>;
+				};
+
+				cpu_alert1 {
+					temperature = <0x124f8>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+				};
+
+				cpu_crit {
+					temperature = <0x17318>;
+					hysteresis = <0x7d0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+
+				map0 {
+					trip = <0xa2>;
+					cooling-device = <0x0a 0xffffffff 0xffffffff 0x0b 0xffffffff 0xffffffff 0x0c 0xffffffff 0xffffffff 0x0d 0xffffffff 0xffffffff>;
+				};
+			};
+		};
+
+		gpu-thermal {
+			polling-delay-passive = <0x14>;
+			polling-delay = <0x3e8>;
+			thermal-sensors = <0xa1 0x01>;
+
+			trips {
+
+				gpu-threshold {
+					temperature = <0x11170>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+				};
+
+				gpu-target {
+					temperature = <0x124f8>;
+					hysteresis = <0x7d0>;
+					type = "passive";
+					phandle = <0xa3>;
+				};
+
+				gpu-crit {
+					temperature = <0x17318>;
+					hysteresis = <0x7d0>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+
+				map0 {
+					trip = <0xa3>;
+					cooling-device = <0xa4 0xffffffff 0xffffffff>;
+				};
+			};
+		};
+	};
+
+	tsadc@fe710000 {
+		compatible = "rockchip,rk3568-tsadc";
+		reg = <0x00 0xfe710000 0x00 0x100>;
+		interrupts = <0x00 0x73 0x04>;
+		assigned-clocks = <0x0f 0x110 0x0f 0x111>;
+		assigned-clock-rates = <0x1036640 0xaae60>;
+		clocks = <0x0f 0x111 0x0f 0x10f>;
+		clock-names = "tsadc", "apb_pclk";
+		resets = <0x0f 0x181 0x0f 0x182 0x0f 0x1d7>;
+		rockchip,grf = <0x20>;
+		rockchip,hw-tshut-temp = <0x17318>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <0xa5>;
+		pinctrl-1 = <0xa6>;
+		#thermal-sensor-cells = <0x01>;
+		status = "okay";
+		rockchip,hw-tshut-mode = <0x01>;
+		rockchip,hw-tshut-polarity = <0x00>;
+		phandle = <0xa1>;
+	};
+
+	saradc@fe720000 {
+		compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
+		reg = <0x00 0xfe720000 0x00 0x100>;
+		interrupts = <0x00 0x5d 0x04>;
+		clocks = <0x0f 0x113 0x0f 0x112>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <0x0f 0x180>;
+		reset-names = "saradc-apb";
+		#io-channel-cells = <0x01>;
+		status = "okay";
+		vref-supply = <0xa7>;
+	};
+
+	pwm@fe6e0000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6e0000 0x00 0x10>;
+		clocks = <0x0f 0x15a 0x0f 0x159>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xa8>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6e0010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6e0010 0x00 0x10>;
+		clocks = <0x0f 0x15a 0x0f 0x159>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xa9>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6e0020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6e0020 0x00 0x10>;
+		clocks = <0x0f 0x15a 0x0f 0x159>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xaa>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6e0030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6e0030 0x00 0x10>;
+		clocks = <0x0f 0x15a 0x0f 0x159>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xab>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6f0000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6f0000 0x00 0x10>;
+		clocks = <0x0f 0x15d 0x0f 0x15c>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xac>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6f0010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6f0010 0x00 0x10>;
+		clocks = <0x0f 0x15d 0x0f 0x15c>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xad>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6f0020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6f0020 0x00 0x10>;
+		clocks = <0x0f 0x15d 0x0f 0x15c>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xae>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe6f0030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe6f0030 0x00 0x10>;
+		clocks = <0x0f 0x15d 0x0f 0x15c>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xaf>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe700000 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe700000 0x00 0x10>;
+		clocks = <0x0f 0x160 0x0f 0x15f>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xb0>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe700010 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe700010 0x00 0x10>;
+		clocks = <0x0f 0x160 0x0f 0x15f>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xb1>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe700020 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe700020 0x00 0x10>;
+		clocks = <0x0f 0x160 0x0f 0x15f>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xb2>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	pwm@fe700030 {
+		compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
+		reg = <0x00 0xfe700030 0x00 0x10>;
+		clocks = <0x0f 0x160 0x0f 0x15f>;
+		clock-names = "pwm", "pclk";
+		pinctrl-0 = <0xb3>;
+		pinctrl-names = "default";
+		#pwm-cells = <0x03>;
+		status = "disabled";
+	};
+
+	phy@fe830000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x00 0xfe830000 0x00 0x100>;
+		clocks = <0x1f 0x22 0x0f 0x17d 0x0f 0x7f>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <0x1f 0x22>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x0f 0x1c7>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <0xb4>;
+		rockchip,pipe-phy-grf = <0xb5>;
+		#phy-cells = <0x01>;
+		status = "okay";
+		phandle = <0x10>;
+	};
+
+	phy@fe840000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x00 0xfe840000 0x00 0x100>;
+		clocks = <0x1f 0x25 0x0f 0x17e 0x0f 0x7f>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <0x1f 0x25>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x0f 0x1c9>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <0xb4>;
+		rockchip,pipe-phy-grf = <0xb6>;
+		#phy-cells = <0x01>;
+		status = "okay";
+		phandle = <0x12>;
+	};
+
+	phy@fe870000 {
+		compatible = "rockchip,rk3568-csi-dphy";
+		reg = <0x00 0xfe870000 0x00 0x10000>;
+		clocks = <0x0f 0x179>;
+		clock-names = "pclk";
+		#phy-cells = <0x00>;
+		resets = <0x0f 0x1ba>;
+		reset-names = "apb";
+		rockchip,grf = <0x20>;
+		status = "disabled";
+	};
+
+	mipi-dphy@fe850000 {
+		compatible = "rockchip,rk3568-dsi-dphy";
+		reg = <0x00 0xfe850000 0x00 0x10000>;
+		clock-names = "ref", "pclk";
+		clocks = <0x1f 0x17 0x0f 0x17a>;
+		#phy-cells = <0x00>;
+		power-domains = <0x11 0x09>;
+		reset-names = "apb";
+		resets = <0x0f 0x1bb>;
+		status = "disabled";
+		phandle = <0x5d>;
+	};
+
+	mipi-dphy@fe860000 {
+		compatible = "rockchip,rk3568-dsi-dphy";
+		reg = <0x00 0xfe860000 0x00 0x10000>;
+		clock-names = "ref", "pclk";
+		clocks = <0x1f 0x19 0x0f 0x17b>;
+		#phy-cells = <0x00>;
+		power-domains = <0x11 0x09>;
+		reset-names = "apb";
+		resets = <0x0f 0x1bc>;
+		status = "disabled";
+		phandle = <0x5e>;
+	};
+
+	usb2phy@fe8a0000 {
+		compatible = "rockchip,rk3568-usb2phy";
+		reg = <0x00 0xfe8a0000 0x00 0x10000>;
+		clocks = <0x1f 0x13>;
+		clock-names = "phyclk";
+		clock-output-names = "clk_usbphy0_480m";
+		interrupts = <0x00 0x87 0x04>;
+		rockchip,usbgrf = <0xb7>;
+		#clock-cells = <0x00>;
+		status = "okay";
+		phandle = <0x15>;
+
+		host-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phy-supply = <0xb8>;
+			phandle = <0x16>;
+		};
+
+		otg-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phy-supply = <0xb9>;
+			phandle = <0x13>;
+		};
+	};
+
+	usb2phy@fe8b0000 {
+		compatible = "rockchip,rk3568-usb2phy";
+		reg = <0x00 0xfe8b0000 0x00 0x10000>;
+		clocks = <0x1f 0x15>;
+		clock-names = "phyclk";
+		clock-output-names = "clk_usbphy1_480m";
+		interrupts = <0x00 0x88 0x04>;
+		rockchip,usbgrf = <0xba>;
+		#clock-cells = <0x00>;
+		status = "okay";
+
+		host-port {
+			#phy-cells = <0x00>;
+			status = "disabled";
+			phandle = <0x18>;
+		};
+
+		otg-port {
+			#phy-cells = <0x00>;
+			status = "okay";
+			phy-supply = <0xb8>;
+			phandle = <0x17>;
+		};
+	};
+
+	pinctrl {
+		compatible = "rockchip,rk3568-pinctrl";
+		rockchip,grf = <0x20>;
+		rockchip,pmu = <0x66>;
+		#address-cells = <0x02>;
+		#size-cells = <0x02>;
+		ranges;
+		phandle = <0xbb>;
+
+		gpio@fdd60000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfdd60000 0x00 0x100>;
+			interrupts = <0x00 0x21 0x04>;
+			clocks = <0x1f 0x2e 0x1f 0x0c>;
+			gpio-controller;
+			gpio-ranges = <0xbb 0x00 0x00 0x20>;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x23>;
+		};
+
+		gpio@fe740000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfe740000 0x00 0x100>;
+			interrupts = <0x00 0x22 0x04>;
+			clocks = <0x0f 0x163 0x0f 0x164>;
+			gpio-controller;
+			gpio-ranges = <0xbb 0x00 0x20 0x20>;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+		};
+
+		gpio@fe750000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfe750000 0x00 0x100>;
+			interrupts = <0x00 0x23 0x04>;
+			clocks = <0x0f 0x165 0x0f 0x166>;
+			gpio-controller;
+			gpio-ranges = <0xbb 0x00 0x40 0x20>;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0xc9>;
+		};
+
+		gpio@fe760000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfe760000 0x00 0x100>;
+			interrupts = <0x00 0x24 0x04>;
+			clocks = <0x0f 0x167 0x0f 0x168>;
+			gpio-controller;
+			gpio-ranges = <0xbb 0x00 0x60 0x20>;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+			phandle = <0x5a>;
+		};
+
+		gpio@fe770000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x00 0xfe770000 0x00 0x100>;
+			interrupts = <0x00 0x25 0x04>;
+			clocks = <0x0f 0x169 0x0f 0x16a>;
+			gpio-controller;
+			gpio-ranges = <0xbb 0x00 0x80 0x20>;
+			#gpio-cells = <0x02>;
+			interrupt-controller;
+			#interrupt-cells = <0x02>;
+		};
+
+		pcfg-pull-up {
+			bias-pull-up;
+			phandle = <0xbe>;
+		};
+
+		pcfg-pull-none {
+			bias-disable;
+			phandle = <0xbc>;
+		};
+
+		pcfg-pull-none-drv-level-1 {
+			bias-disable;
+			drive-strength = <0x01>;
+			phandle = <0xc0>;
+		};
+
+		pcfg-pull-none-drv-level-2 {
+			bias-disable;
+			drive-strength = <0x02>;
+			phandle = <0xbf>;
+		};
+
+		pcfg-pull-none-drv-level-3 {
+			bias-disable;
+			drive-strength = <0x03>;
+			phandle = <0xc3>;
+		};
+
+		pcfg-pull-up-drv-level-1 {
+			bias-pull-up;
+			drive-strength = <0x01>;
+			phandle = <0xc2>;
+		};
+
+		pcfg-pull-up-drv-level-2 {
+			bias-pull-up;
+			drive-strength = <0x02>;
+			phandle = <0xbd>;
+		};
+
+		pcfg-pull-none-smt {
+			bias-disable;
+			input-schmitt-enable;
+			phandle = <0xc1>;
+		};
+
+		acodec {
+		};
+
+		audiopwm {
+		};
+
+		bt656 {
+		};
+
+		bt1120 {
+		};
+
+		cam {
+		};
+
+		can0 {
+
+			can0m0-pins {
+				rockchip,pins = <0x00 0x0c 0x02 0xbc 0x00 0x0b 0x02 0xbc>;
+				phandle = <0xd4>;
+			};
+		};
+
+		can1 {
+
+			can1m0-pins {
+				rockchip,pins = <0x01 0x00 0x03 0xbc 0x01 0x01 0x03 0xbc>;
+				phandle = <0xd5>;
+			};
+		};
+
+		can2 {
+
+			can2m0-pins {
+				rockchip,pins = <0x04 0x0c 0x03 0xbc 0x04 0x0d 0x03 0xbc>;
+				phandle = <0xd6>;
+			};
+		};
+
+		cif {
+		};
+
+		clk32k {
+
+			clk32k-out0 {
+				rockchip,pins = <0x00 0x08 0x02 0xbc>;
+				phandle = <0x0e>;
+			};
+		};
+
+		cpu {
+		};
+
+		ebc {
+		};
+
+		edpdp {
+		};
+
+		emmc {
+
+			emmc-bus8 {
+				rockchip,pins = <0x01 0x0c 0x01 0xbd 0x01 0x0d 0x01 0xbd 0x01 0x0e 0x01 0xbd 0x01 0x0f 0x01 0xbd 0x01 0x10 0x01 0xbd 0x01 0x11 0x01 0xbd 0x01 0x12 0x01 0xbd 0x01 0x13 0x01 0xbd>;
+				phandle = <0x70>;
+			};
+
+			emmc-clk {
+				rockchip,pins = <0x01 0x15 0x01 0xbd>;
+				phandle = <0x71>;
+			};
+
+			emmc-cmd {
+				rockchip,pins = <0x01 0x14 0x01 0xbd>;
+				phandle = <0x72>;
+			};
+
+			emmc-datastrobe {
+				rockchip,pins = <0x01 0x16 0x01 0xbc>;
+				phandle = <0x73>;
+			};
+		};
+
+		eth0 {
+		};
+
+		eth1 {
+		};
+
+		flash {
+		};
+
+		fspi {
+
+			fspi-pins {
+				rockchip,pins = <0x01 0x18 0x01 0xbc 0x01 0x1b 0x01 0xbc 0x01 0x19 0x01 0xbc 0x01 0x1a 0x01 0xbc 0x01 0x17 0x02 0xbc 0x01 0x1c 0x01 0xbc>;
+				phandle = <0x6f>;
+			};
+		};
+
+		gmac0 {
+
+			gmac0-miim {
+				rockchip,pins = <0x02 0x13 0x02 0xbc 0x02 0x14 0x02 0xbc>;
+				phandle = <0xce>;
+			};
+
+			gmac0-clkinout {
+				rockchip,pins = <0x02 0x12 0x02 0xbc>;
+				phandle = <0xd3>;
+			};
+
+			gmac0-rx-bus2 {
+				rockchip,pins = <0x02 0x0e 0x01 0xbc 0x02 0x0f 0x02 0xbc 0x02 0x10 0x02 0xbc>;
+				phandle = <0xd0>;
+			};
+
+			gmac0-tx-bus2 {
+				rockchip,pins = <0x02 0x0b 0x01 0xbf 0x02 0x0c 0x01 0xbf 0x02 0x0d 0x01 0xbc>;
+				phandle = <0xcf>;
+			};
+
+			gmac0-rgmii-clk {
+				rockchip,pins = <0x02 0x05 0x02 0xbc 0x02 0x08 0x02 0xc0>;
+				phandle = <0xd1>;
+			};
+
+			gmac0-rgmii-bus {
+				rockchip,pins = <0x02 0x03 0x02 0xbc 0x02 0x04 0x02 0xbc 0x02 0x06 0x02 0xbf 0x02 0x07 0x02 0xbf>;
+				phandle = <0xd2>;
+			};
+		};
+
+		gmac1 {
+
+			gmac1m1-miim {
+				rockchip,pins = <0x04 0x0e 0x03 0xbc 0x04 0x0f 0x03 0xbc>;
+				phandle = <0x54>;
+			};
+
+			gmac1m1-clkinout {
+				rockchip,pins = <0x04 0x11 0x03 0xbc>;
+				phandle = <0x59>;
+			};
+
+			gmac1m1-rx-bus2 {
+				rockchip,pins = <0x04 0x07 0x03 0xbc 0x04 0x08 0x03 0xbc 0x04 0x09 0x03 0xbc>;
+				phandle = <0x56>;
+			};
+
+			gmac1m1-tx-bus2 {
+				rockchip,pins = <0x04 0x04 0x03 0xbf 0x04 0x05 0x03 0xbf 0x04 0x06 0x03 0xbc>;
+				phandle = <0x55>;
+			};
+
+			gmac1m1-rgmii-clk {
+				rockchip,pins = <0x04 0x03 0x03 0xbc 0x04 0x00 0x03 0xc0>;
+				phandle = <0x57>;
+			};
+
+			gmac1m1-rgmii-bus {
+				rockchip,pins = <0x04 0x01 0x03 0xbc 0x04 0x02 0x03 0xbc 0x03 0x1e 0x03 0xbf 0x03 0x1f 0x03 0xbf>;
+				phandle = <0x58>;
+			};
+		};
+
+		gpu {
+		};
+
+		hdmitx {
+
+			hdmitxm0-cec {
+				rockchip,pins = <0x04 0x19 0x01 0xbc>;
+				phandle = <0x61>;
+			};
+
+			hdmitx-scl {
+				rockchip,pins = <0x04 0x17 0x01 0xbc>;
+				phandle = <0x5f>;
+			};
+
+			hdmitx-sda {
+				rockchip,pins = <0x04 0x18 0x01 0xbc>;
+				phandle = <0x60>;
+			};
+		};
+
+		i2c0 {
+
+			i2c0-xfer {
+				rockchip,pins = <0x00 0x09 0x01 0xc1 0x00 0x0a 0x01 0xc1>;
+				phandle = <0x21>;
+			};
+		};
+
+		i2c1 {
+
+			i2c1-xfer {
+				rockchip,pins = <0x00 0x0b 0x01 0xc1 0x00 0x0c 0x01 0xc1>;
+				phandle = <0x84>;
+			};
+		};
+
+		i2c2 {
+
+			i2c2m0-xfer {
+				rockchip,pins = <0x00 0x0d 0x01 0xc1 0x00 0x0e 0x01 0xc1>;
+				phandle = <0x85>;
+			};
+		};
+
+		i2c3 {
+
+			i2c3m0-xfer {
+				rockchip,pins = <0x01 0x01 0x01 0xc1 0x01 0x00 0x01 0xc1>;
+				phandle = <0x86>;
+			};
+		};
+
+		i2c4 {
+
+			i2c4m0-xfer {
+				rockchip,pins = <0x04 0x0b 0x01 0xc1 0x04 0x0a 0x01 0xc1>;
+				phandle = <0x87>;
+			};
+		};
+
+		i2c5 {
+
+			i2c5m0-xfer {
+				rockchip,pins = <0x03 0x0b 0x04 0xc1 0x03 0x0c 0x04 0xc1>;
+				phandle = <0x88>;
+			};
+		};
+
+		i2s1 {
+
+			i2s1m0-lrcktx {
+				rockchip,pins = <0x01 0x05 0x01 0xbc>;
+				phandle = <0x76>;
+			};
+
+			i2s1m0-mclk {
+				rockchip,pins = <0x01 0x02 0x01 0xbc>;
+				phandle = <0x25>;
+			};
+
+			i2s1m0-sclktx {
+				rockchip,pins = <0x01 0x03 0x01 0xbc>;
+				phandle = <0x75>;
+			};
+
+			i2s1m0-sdi0 {
+				rockchip,pins = <0x01 0x0b 0x01 0xbc>;
+				phandle = <0x77>;
+			};
+
+			i2s1m0-sdo0 {
+				rockchip,pins = <0x01 0x07 0x01 0xbc>;
+				phandle = <0x78>;
+			};
+		};
+
+		i2s2 {
+
+			i2s2m0-lrcktx {
+				rockchip,pins = <0x02 0x13 0x01 0xbc>;
+				phandle = <0x7a>;
+			};
+
+			i2s2m0-sclktx {
+				rockchip,pins = <0x02 0x12 0x01 0xbc>;
+				phandle = <0x79>;
+			};
+
+			i2s2m0-sdi {
+				rockchip,pins = <0x02 0x15 0x01 0xbc>;
+				phandle = <0x7b>;
+			};
+
+			i2s2m0-sdo {
+				rockchip,pins = <0x02 0x14 0x01 0xbc>;
+				phandle = <0x7c>;
+			};
+		};
+
+		i2s3 {
+		};
+
+		isp {
+		};
+
+		jtag {
+		};
+
+		lcdc {
+		};
+
+		mcu {
+		};
+
+		npu {
+		};
+
+		pcie20 {
+
+			pcie20m1-pins {
+				rockchip,pins = <0x02 0x18 0x04 0xbc 0x03 0x11 0x00 0xbc 0x02 0x19 0x04 0xbc>;
+				phandle = <0x69>;
+			};
+		};
+
+		pcie30x1 {
+		};
+
+		pcie30x2 {
+
+			pcie30x2m1-pins {
+				rockchip,pins = <0x02 0x1c 0x04 0xbc 0x02 0x1e 0x00 0xbc 0x02 0x1d 0x04 0xbc>;
+				phandle = <0xc8>;
+			};
+		};
+
+		pdm {
+
+			pdmm0-clk {
+				rockchip,pins = <0x01 0x06 0x03 0xbc>;
+				phandle = <0x7d>;
+			};
+
+			pdmm0-clk1 {
+				rockchip,pins = <0x01 0x04 0x03 0xbc>;
+				phandle = <0x7e>;
+			};
+
+			pdmm0-sdi0 {
+				rockchip,pins = <0x01 0x0b 0x02 0xbc>;
+				phandle = <0x7f>;
+			};
+
+			pdmm0-sdi1 {
+				rockchip,pins = <0x01 0x0a 0x03 0xbc>;
+				phandle = <0x80>;
+			};
+
+			pdmm0-sdi2 {
+				rockchip,pins = <0x01 0x09 0x03 0xbc>;
+				phandle = <0x81>;
+			};
+
+			pdmm0-sdi3 {
+				rockchip,pins = <0x01 0x08 0x03 0xbc>;
+				phandle = <0x82>;
+			};
+		};
+
+		pmic {
+
+			pmic-int-l {
+				rockchip,pins = <0x00 0x03 0x00 0xbe>;
+				phandle = <0x24>;
+			};
+		};
+
+		pmu {
+		};
+
+		pwm0 {
+
+			pwm0m0-pins {
+				rockchip,pins = <0x00 0x0f 0x01 0xbc>;
+				phandle = <0x29>;
+			};
+		};
+
+		pwm1 {
+
+			pwm1m0-pins {
+				rockchip,pins = <0x00 0x10 0x01 0xbc>;
+				phandle = <0x2a>;
+			};
+		};
+
+		pwm2 {
+
+			pwm2m0-pins {
+				rockchip,pins = <0x00 0x11 0x01 0xbc>;
+				phandle = <0x2b>;
+			};
+		};
+
+		pwm3 {
+
+			pwm3-pins {
+				rockchip,pins = <0x00 0x12 0x01 0xbc>;
+				phandle = <0x2c>;
+			};
+		};
+
+		pwm4 {
+
+			pwm4-pins {
+				rockchip,pins = <0x00 0x13 0x01 0xbc>;
+				phandle = <0xa8>;
+			};
+		};
+
+		pwm5 {
+
+			pwm5-pins {
+				rockchip,pins = <0x00 0x14 0x01 0xbc>;
+				phandle = <0xa9>;
+			};
+		};
+
+		pwm6 {
+
+			pwm6-pins {
+				rockchip,pins = <0x00 0x15 0x01 0xbc>;
+				phandle = <0xaa>;
+			};
+		};
+
+		pwm7 {
+
+			pwm7-pins {
+				rockchip,pins = <0x00 0x16 0x01 0xbc>;
+				phandle = <0xab>;
+			};
+		};
+
+		pwm8 {
+
+			pwm8m0-pins {
+				rockchip,pins = <0x03 0x09 0x05 0xbc>;
+				phandle = <0xac>;
+			};
+		};
+
+		pwm9 {
+
+			pwm9m0-pins {
+				rockchip,pins = <0x03 0x0a 0x05 0xbc>;
+				phandle = <0xad>;
+			};
+		};
+
+		pwm10 {
+
+			pwm10m0-pins {
+				rockchip,pins = <0x03 0x0d 0x05 0xbc>;
+				phandle = <0xae>;
+			};
+		};
+
+		pwm11 {
+
+			pwm11m0-pins {
+				rockchip,pins = <0x03 0x0e 0x05 0xbc>;
+				phandle = <0xaf>;
+			};
+		};
+
+		pwm12 {
+
+			pwm12m0-pins {
+				rockchip,pins = <0x03 0x0f 0x02 0xbc>;
+				phandle = <0xb0>;
+			};
+		};
+
+		pwm13 {
+
+			pwm13m0-pins {
+				rockchip,pins = <0x03 0x10 0x02 0xbc>;
+				phandle = <0xb1>;
+			};
+		};
+
+		pwm14 {
+
+			pwm14m0-pins {
+				rockchip,pins = <0x03 0x14 0x01 0xbc>;
+				phandle = <0xb2>;
+			};
+		};
+
+		pwm15 {
+
+			pwm15m0-pins {
+				rockchip,pins = <0x03 0x15 0x01 0xbc>;
+				phandle = <0xb3>;
+			};
+		};
+
+		refclk {
+		};
+
+		sata {
+		};
+
+		sata0 {
+		};
+
+		sata1 {
+		};
+
+		sata2 {
+		};
+
+		scr {
+		};
+
+		sdmmc0 {
+
+			sdmmc0-bus4 {
+				rockchip,pins = <0x01 0x1d 0x01 0xbd 0x01 0x1e 0x01 0xbd 0x01 0x1f 0x01 0xbd 0x02 0x00 0x01 0xbd>;
+				phandle = <0x6a>;
+			};
+
+			sdmmc0-clk {
+				rockchip,pins = <0x02 0x02 0x01 0xbd>;
+				phandle = <0x6b>;
+			};
+
+			sdmmc0-cmd {
+				rockchip,pins = <0x02 0x01 0x01 0xbd>;
+				phandle = <0x6c>;
+			};
+
+			sdmmc0-det {
+				rockchip,pins = <0x00 0x04 0x01 0xbe>;
+				phandle = <0x6d>;
+			};
+		};
+
+		sdmmc1 {
+		};
+
+		sdmmc2 {
+
+			sdmmc2m0-bus4 {
+				rockchip,pins = <0x03 0x16 0x03 0xbd 0x03 0x17 0x03 0xbd 0x03 0x18 0x03 0xbd 0x03 0x19 0x03 0xbd>;
+				phandle = <0x4c>;
+			};
+
+			sdmmc2m0-clk {
+				rockchip,pins = <0x03 0x1b 0x03 0xbd>;
+				phandle = <0x4d>;
+			};
+
+			sdmmc2m0-cmd {
+				rockchip,pins = <0x03 0x1a 0x03 0xbd>;
+				phandle = <0x4e>;
+			};
+		};
+
+		spdif {
+
+			spdifm0-tx {
+				rockchip,pins = <0x01 0x04 0x04 0xbc>;
+				phandle = <0x83>;
+			};
+		};
+
+		spi0 {
+
+			spi0m0-pins {
+				rockchip,pins = <0x00 0x0d 0x02 0xbc 0x00 0x15 0x02 0xbc 0x00 0x0e 0x02 0xbc>;
+				phandle = <0x8c>;
+			};
+
+			spi0m0-cs0 {
+				rockchip,pins = <0x00 0x16 0x02 0xbc>;
+				phandle = <0x8a>;
+			};
+
+			spi0m0-cs1 {
+				rockchip,pins = <0x00 0x14 0x02 0xbc>;
+				phandle = <0x8b>;
+			};
+		};
+
+		spi1 {
+
+			spi1m0-pins {
+				rockchip,pins = <0x02 0x0d 0x03 0xbc 0x02 0x0e 0x03 0xbc 0x02 0x0f 0x04 0xbc>;
+				phandle = <0x8f>;
+			};
+
+			spi1m0-cs0 {
+				rockchip,pins = <0x02 0x10 0x04 0xbc>;
+				phandle = <0x8d>;
+			};
+
+			spi1m0-cs1 {
+				rockchip,pins = <0x02 0x16 0x03 0xbc>;
+				phandle = <0x8e>;
+			};
+		};
+
+		spi2 {
+
+			spi2m0-pins {
+				rockchip,pins = <0x02 0x11 0x04 0xbc 0x02 0x12 0x04 0xbc 0x02 0x13 0x04 0xbc>;
+				phandle = <0x92>;
+			};
+
+			spi2m0-cs0 {
+				rockchip,pins = <0x02 0x14 0x04 0xbc>;
+				phandle = <0x90>;
+			};
+
+			spi2m0-cs1 {
+				rockchip,pins = <0x02 0x15 0x04 0xbc>;
+				phandle = <0x91>;
+			};
+		};
+
+		spi3 {
+
+			spi3m0-pins {
+				rockchip,pins = <0x04 0x0b 0x04 0xbc 0x04 0x08 0x04 0xbc 0x04 0x0a 0x04 0xbc>;
+				phandle = <0x95>;
+			};
+
+			spi3m0-cs0 {
+				rockchip,pins = <0x04 0x06 0x04 0xbc>;
+				phandle = <0x93>;
+			};
+
+			spi3m0-cs1 {
+				rockchip,pins = <0x04 0x07 0x04 0xbc>;
+				phandle = <0x94>;
+			};
+		};
+
+		tsadc {
+
+			tsadc-shutorg {
+				rockchip,pins = <0x00 0x01 0x02 0xbc>;
+				phandle = <0xa5>;
+			};
+
+			tsadc-pin {
+				rockchip,pins = <0x00 0x01 0x00 0xbc>;
+				phandle = <0xa6>;
+			};
+		};
+
+		uart0 {
+
+			uart0-xfer {
+				rockchip,pins = <0x00 0x10 0x03 0xbe 0x00 0x11 0x03 0xbe>;
+				phandle = <0x28>;
+			};
+		};
+
+		uart1 {
+
+			uart1m0-xfer {
+				rockchip,pins = <0x02 0x0b 0x02 0xbe 0x02 0x0c 0x02 0xbe>;
+				phandle = <0x96>;
+			};
+		};
+
+		uart2 {
+
+			uart2m0-xfer {
+				rockchip,pins = <0x00 0x18 0x01 0xbe 0x00 0x19 0x01 0xbe>;
+				phandle = <0x97>;
+			};
+		};
+
+		uart3 {
+
+			uart3m0-xfer {
+				rockchip,pins = <0x01 0x00 0x02 0xbe 0x01 0x01 0x02 0xbe>;
+				phandle = <0x98>;
+			};
+		};
+
+		uart4 {
+
+			uart4m0-xfer {
+				rockchip,pins = <0x01 0x04 0x02 0xbe 0x01 0x06 0x02 0xbe>;
+				phandle = <0x99>;
+			};
+		};
+
+		uart5 {
+
+			uart5m0-xfer {
+				rockchip,pins = <0x02 0x01 0x03 0xbe 0x02 0x02 0x03 0xbe>;
+				phandle = <0x9a>;
+			};
+		};
+
+		uart6 {
+
+			uart6m0-xfer {
+				rockchip,pins = <0x02 0x03 0x03 0xbe 0x02 0x04 0x03 0xbe>;
+				phandle = <0x9b>;
+			};
+		};
+
+		uart7 {
+
+			uart7m0-xfer {
+				rockchip,pins = <0x02 0x05 0x03 0xbe 0x02 0x06 0x03 0xbe>;
+				phandle = <0x9c>;
+			};
+		};
+
+		uart8 {
+
+			uart8m0-xfer {
+				rockchip,pins = <0x02 0x16 0x02 0xbe 0x02 0x15 0x03 0xbe>;
+				phandle = <0x9d>;
+			};
+
+			uart8m0-ctsn {
+				rockchip,pins = <0x02 0x0a 0x03 0xbc>;
+				phandle = <0x9e>;
+			};
+
+			uart8m0-rtsn {
+				rockchip,pins = <0x02 0x09 0x03 0xbc>;
+				phandle = <0x9f>;
+			};
+		};
+
+		uart9 {
+
+			uart9m0-xfer {
+				rockchip,pins = <0x02 0x07 0x03 0xbe 0x02 0x08 0x03 0xbe>;
+				phandle = <0xa0>;
+			};
+		};
+
+		vop {
+		};
+
+		spi0-hs {
+		};
+
+		spi1-hs {
+		};
+
+		spi2-hs {
+		};
+
+		spi3-hs {
+		};
+
+		gmac-txd-level3 {
+		};
+
+		gmac-txc-level2 {
+		};
+
+		bluetooth {
+
+			bt-reg-on-h {
+				rockchip,pins = <0x04 0x0a 0x00 0xbc>;
+			};
+
+			bt-wake-host-h {
+				rockchip,pins = <0x04 0x0c 0x00 0xbc>;
+			};
+
+			host-wake-bt-h {
+				rockchip,pins = <0x04 0x0d 0x00 0xbc>;
+			};
+		};
+
+		ir-receiver {
+
+			pwm3-ir {
+				rockchip,pins = <0x00 0x12 0x00 0xbc>;
+				phandle = <0xd9>;
+			};
+		};
+
+		leds {
+
+			led {
+				rockchip,pins = <0x00 0x0f 0x00 0xbc>;
+				phandle = <0xda>;
+			};
+		};
+
+		pcie {
+
+			pcie-pwren-h {
+				rockchip,pins = <0x00 0x1c 0x00 0xbc>;
+				phandle = <0xdb>;
+			};
+		};
+
+		rtc {
+
+			rtcic-int-l {
+				rockchip,pins = <0x00 0x1b 0x00 0xbe>;
+				phandle = <0x89>;
+			};
+		};
+
+		usb {
+
+			usb-host-pwren-h {
+				rockchip,pins = <0x00 0x06 0x00 0xbc>;
+				phandle = <0xdc>;
+			};
+
+			usb-otg-pwren-h {
+				rockchip,pins = <0x00 0x05 0x00 0xbc>;
+				phandle = <0xdd>;
+			};
+		};
+
+		wifi {
+
+			wifi-reg-on-h {
+				rockchip,pins = <0x03 0x1c 0x00 0xbc>;
+				phandle = <0xdf>;
+			};
+
+			wifi-wake-host-h {
+				rockchip,pins = <0x03 0x1d 0x00 0xbc>;
+			};
+		};
+	};
+
+	opp-table-0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+		phandle = <0x04>;
+
+		opp-408000000 {
+			opp-hz = <0x00 0x18519600>;
+			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-600000000 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-816000000 {
+			opp-hz = <0x00 0x30a32c00>;
+			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+			opp-suspend;
+		};
+
+		opp-1104000000 {
+			opp-hz = <0x00 0x41cdb400>;
+			opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1416000000 {
+			opp-hz = <0x00 0x54667200>;
+			opp-microvolt = <0xfa3e8 0xfa3e8 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1608000000 {
+			opp-hz = <0x00 0x5fd82200>;
+			opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1800000000 {
+			opp-hz = <0x00 0x6b49d200>;
+			opp-microvolt = <0x118c30 0x118c30 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+
+		opp-1992000000 {
+			opp-hz = <0x00 0x76bb8200>;
+			opp-microvolt = <0x118c30 0x118c30 0x118c30>;
+			clock-latency-ns = <0x9c40>;
+		};
+	};
+
+	opp-table-1 {
+		compatible = "operating-points-v2";
+		phandle = <0x47>;
+
+		opp-200000000 {
+			opp-hz = <0x00 0xbebc200>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
+		};
+
+		opp-300000000 {
+			opp-hz = <0x00 0x11e1a300>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
+		};
+
+		opp-400000000 {
+			opp-hz = <0x00 0x17d78400>;
+			opp-microvolt = <0xcf850 0xcf850 0xf4240>;
+		};
+
+		opp-600000000 {
+			opp-hz = <0x00 0x23c34600>;
+			opp-microvolt = <0xdbba0 0xdbba0 0xf4240>;
+		};
+
+		opp-700000000 {
+			opp-hz = <0x00 0x29b92700>;
+			opp-microvolt = <0xe7ef0 0xe7ef0 0xf4240>;
+		};
+
+		opp-800000000 {
+			opp-hz = <0x00 0x2faf0800>;
+			opp-microvolt = <0xf4240 0xf4240 0xf4240>;
+		};
+	};
+
+	sata@fc000000 {
+		compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
+		reg = <0x00 0xfc000000 0x00 0x1000>;
+		clocks = <0x0f 0x96 0x0f 0x97 0x0f 0x98>;
+		clock-names = "sata", "pmalive", "rxoob";
+		interrupts = <0x00 0x5e 0x04>;
+		phys = <0x14 0x01>;
+		phy-names = "sata-phy";
+		ports-implemented = <0x01>;
+		power-domains = <0x11 0x0f>;
+		status = "disabled";
+	};
+
+	syscon@fdc70000 {
+		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
+		reg = <0x00 0xfdc70000 0x00 0x1000>;
+		phandle = <0xd7>;
+	};
+
+	qos@fe190080 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190080 0x00 0x20>;
+		phandle = <0x40>;
+	};
+
+	qos@fe190100 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190100 0x00 0x20>;
+		phandle = <0x41>;
+	};
+
+	qos@fe190200 {
+		compatible = "rockchip,rk3568-qos", "syscon";
+		reg = <0x00 0xfe190200 0x00 0x20>;
+		phandle = <0x42>;
+	};
+
+	syscon@fdcb8000 {
+		compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon";
+		reg = <0x00 0xfdcb8000 0x00 0x10000>;
+		phandle = <0xc4>;
+	};
+
+	phy@fe8c0000 {
+		compatible = "rockchip,rk3568-pcie3-phy";
+		reg = <0x00 0xfe8c0000 0x00 0x20000>;
+		#phy-cells = <0x00>;
+		clocks = <0x1f 0x26 0x1f 0x27 0x0f 0x177>;
+		clock-names = "refclk_m", "refclk_n", "pclk";
+		resets = <0x0f 0x1be>;
+		reset-names = "phy";
+		rockchip,phy-grf = <0xc4>;
+		status = "okay";
+		phandle = <0xc6>;
+	};
+
+	pcie@fe270000 {
+		compatible = "rockchip,rk3568-pcie";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		bus-range = <0x10 0x1f>;
+		clocks = <0x0f 0x88 0x0f 0x89 0x0f 0x8a 0x0f 0x8b 0x0f 0x8c>;
+		clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
+		device_type = "pci";
+		interrupts = <0x00 0xa0 0x04 0x00 0x9f 0x04 0x00 0x9e 0x04 0x00 0x9d 0x04 0x00 0x9c 0x04>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0xc5 0x00 0x00 0x00 0x00 0x02 0xc5 0x01 0x00 0x00 0x00 0x03 0xc5 0x02 0x00 0x00 0x00 0x04 0xc5 0x03>;
+		linux,pci-domain = <0x01>;
+		num-ib-windows = <0x06>;
+		num-ob-windows = <0x02>;
+		max-link-speed = <0x03>;
+		msi-map = <0x1000 0x68 0x1000 0x1000>;
+		num-lanes = <0x01>;
+		phys = <0xc6>;
+		phy-names = "pcie-phy";
+		power-domains = <0x11 0x0f>;
+		reg = <0x03 0xc0400000 0x00 0x400000 0x00 0xfe270000 0x00 0x10000 0x00 0xf2000000 0x00 0x100000>;
+		ranges = <0x1000000 0x00 0xf2100000 0x00 0xf2100000 0x00 0x100000 0x2000000 0x00 0xf2200000 0x00 0xf2200000 0x00 0x1e00000 0x3000000 0x00 0x40000000 0x03 0x40000000 0x00 0x40000000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <0x0f 0xb1>;
+		reset-names = "pipe";
+		status = "disabled";
+
+		legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0x9d 0x01>;
+			phandle = <0xc5>;
+		};
+	};
+
+	pcie@fe280000 {
+		compatible = "rockchip,rk3568-pcie";
+		#address-cells = <0x03>;
+		#size-cells = <0x02>;
+		bus-range = <0x20 0x2f>;
+		clocks = <0x0f 0x8f 0x0f 0x90 0x0f 0x91 0x0f 0x92 0x0f 0x93>;
+		clock-names = "aclk_mst", "aclk_slv", "aclk_dbi", "pclk", "aux";
+		device_type = "pci";
+		interrupts = <0x00 0xa5 0x04 0x00 0xa4 0x04 0x00 0xa3 0x04 0x00 0xa2 0x04 0x00 0xa1 0x04>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <0x01>;
+		interrupt-map-mask = <0x00 0x00 0x00 0x07>;
+		interrupt-map = <0x00 0x00 0x00 0x01 0xc7 0x00 0x00 0x00 0x00 0x02 0xc7 0x01 0x00 0x00 0x00 0x03 0xc7 0x02 0x00 0x00 0x00 0x04 0xc7 0x03>;
+		linux,pci-domain = <0x02>;
+		num-ib-windows = <0x06>;
+		num-ob-windows = <0x02>;
+		max-link-speed = <0x03>;
+		msi-map = <0x2000 0x68 0x2000 0x1000>;
+		num-lanes = <0x02>;
+		phys = <0xc6>;
+		phy-names = "pcie-phy";
+		power-domains = <0x11 0x0f>;
+		reg = <0x03 0xc0800000 0x00 0x400000 0x00 0xfe280000 0x00 0x10000 0x00 0xf0000000 0x00 0x100000>;
+		ranges = <0x1000000 0x00 0xf0100000 0x00 0xf0100000 0x00 0x100000 0x2000000 0x00 0xf0200000 0x00 0xf0200000 0x00 0x1e00000 0x3000000 0x00 0x40000000 0x03 0x80000000 0x00 0x40000000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <0x0f 0xc1>;
+		reset-names = "pipe";
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xc8>;
+		reset-gpios = <0xc9 0x1e 0x00>;
+
+		legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0x00>;
+			#interrupt-cells = <0x01>;
+			interrupt-parent = <0x01>;
+			interrupts = <0x00 0xa2 0x01>;
+			phandle = <0xc7>;
+		};
+	};
+
+	ethernet@fe2a0000 {
+		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
+		reg = <0x00 0xfe2a0000 0x00 0x10000>;
+		interrupts = <0x00 0x1b 0x04 0x00 0x18 0x04>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		clocks = <0x0f 0x182 0x0f 0x185 0x0f 0x185 0x0f 0xb8 0x0f 0xb4 0x0f 0xb5 0x0f 0x185 0x0f 0xb9>;
+		clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref";
+		resets = <0x0f 0xd7>;
+		reset-names = "stmmaceth";
+		rockchip,grf = <0x20>;
+		snps,axi-config = <0xca>;
+		snps,mixed-burst;
+		snps,mtl-rx-config = <0xcb>;
+		snps,mtl-tx-config = <0xcc>;
+		snps,tso;
+		status = "okay";
+		assigned-clocks = <0x0f 0x185 0x0f 0x182>;
+		assigned-clock-parents = <0x0f 0x183 0x0f 0xb6>;
+		clock_in_out = "input";
+		phy-handle = <0xcd>;
+		phy-mode = "rgmii-id";
+		phy-supply = <0x1d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xce 0xcf 0xd0 0xd1 0xd2 0xd3>;
+
+		mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x01>;
+			#size-cells = <0x00>;
+
+			ethernet-phy@1 {
+				compatible = "ethernet-phy-ieee802.3-c22";
+				reg = <0x01>;
+				reset-assert-us = <0x4e20>;
+				reset-deassert-us = <0xc350>;
+				reset-gpios = <0x5a 0x0f 0x01>;
+				phandle = <0xcd>;
+			};
+		};
+
+		stmmac-axi-config {
+			snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
+			snps,rd_osr_lmt = <0x08>;
+			snps,wr_osr_lmt = <0x04>;
+			phandle = <0xca>;
+		};
+
+		rx-queues-config {
+			snps,rx-queues-to-use = <0x01>;
+			phandle = <0xcb>;
+
+			queue0 {
+			};
+		};
+
+		tx-queues-config {
+			snps,tx-queues-to-use = <0x01>;
+			phandle = <0xcc>;
+
+			queue0 {
+			};
+		};
+	};
+
+	can@fe570000 {
+		compatible = "rockchip,rk3568v2-canfd";
+		reg = <0x00 0xfe570000 0x00 0x1000>;
+		interrupts = <0x00 0x01 0x04>;
+		clocks = <0x0f 0x141 0x0f 0x140>;
+		clock-names = "baud", "pclk";
+		resets = <0x0f 0x155 0x0f 0x154>;
+		reset-names = "core", "apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xd4>;
+		status = "disabled";
+	};
+
+	can@fe580000 {
+		compatible = "rockchip,rk3568v2-canfd";
+		reg = <0x00 0xfe580000 0x00 0x1000>;
+		interrupts = <0x00 0x02 0x04>;
+		clocks = <0x0f 0x143 0x0f 0x142>;
+		clock-names = "baud", "pclk";
+		resets = <0x0f 0x157 0x0f 0x156>;
+		reset-names = "core", "apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xd5>;
+		status = "disabled";
+	};
+
+	can@fe590000 {
+		compatible = "rockchip,rk3568v2-canfd";
+		reg = <0x00 0xfe590000 0x00 0x1000>;
+		interrupts = <0x00 0x03 0x04>;
+		clocks = <0x0f 0x145 0x0f 0x144>;
+		clock-names = "baud", "pclk";
+		resets = <0x0f 0x159 0x0f 0x158>;
+		reset-names = "core", "apb";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xd6>;
+		status = "disabled";
+	};
+
+	phy@fe820000 {
+		compatible = "rockchip,rk3568-naneng-combphy";
+		reg = <0x00 0xfe820000 0x00 0x100>;
+		clocks = <0x1f 0x1f 0x0f 0x17c 0x0f 0x7f>;
+		clock-names = "ref", "apb", "pipe";
+		assigned-clocks = <0x1f 0x1f>;
+		assigned-clock-rates = <0x5f5e100>;
+		resets = <0x0f 0x1c5>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <0xb4>;
+		rockchip,pipe-phy-grf = <0xd7>;
+		#phy-cells = <0x01>;
+		status = "okay";
+		phandle = <0x14>;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+
+			endpoint {
+				remote-endpoint = <0xd8>;
+				phandle = <0x65>;
+			};
+		};
+	};
+
+	ir-receiver {
+		compatible = "gpio-ir-receiver";
+		gpios = <0x23 0x12 0x01>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xd9>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xda>;
+
+		led-0 {
+			color = <0x02>;
+			default-state = "on";
+			function = "heartbeat";
+			gpios = <0x23 0x0f 0x00>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	regulator-3v3-vcc-pi6c-03 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <0x23 0x1c 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xdb>;
+		regulator-name = "vcc3v3_pi6c_03";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		startup-delay-us = <0x2710>;
+		vin-supply = <0x22>;
+	};
+
+	regulator-3v3-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		vin-supply = <0x22>;
+		phandle = <0x26>;
+	};
+
+	regulator-3v3-vcc-sys2 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys2";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x325aa0>;
+		regulator-max-microvolt = <0x325aa0>;
+		vin-supply = <0x22>;
+		phandle = <0x4f>;
+	};
+
+	regulator-5v0-vcc-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		phandle = <0x22>;
+	};
+
+	regulator-5v0-vcc-usb-host {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <0x23 0x06 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xdc>;
+		regulator-name = "vcc5v0_usb_host";
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x22>;
+		phandle = <0xb8>;
+	};
+
+	regulator-5v0-vcc-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpios = <0x23 0x05 0x00>;
+		pinctrl-names = "default";
+		pinctrl-0 = <0xdd>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <0x4c4b40>;
+		regulator-max-microvolt = <0x4c4b40>;
+		vin-supply = <0x22>;
+		phandle = <0xb9>;
+	};
+
+	sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		clocks = <0xde 0x01>;
+		clock-names = "ext_clock";
+		pinctrl-names = "default";
+		pinctrl-0 = <0xdf>;
+		post-power-on-delay-ms = <0x64>;
+		power-off-delay-us = <0x4c4b40>;
+		reset-gpios = <0x5a 0x1c 0x01>;
+		phandle = <0x4b>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,name = "Analog RK809";
+		simple-audio-card,mclk-fs = <0x100>;
+
+		simple-audio-card,cpu {
+			sound-dai = <0xe0>;
+		};
+
+		simple-audio-card,codec {
+			sound-dai = <0xde>;
+		};
+	};
+};
diff --git a/tools/dts/update-dts.sh b/tools/dts/update-dts.sh
index 90b29d168..82ca37a6b 100755
--- a/tools/dts/update-dts.sh
+++ b/tools/dts/update-dts.sh
@@ -62,6 +62,7 @@ freescale/fsl-imx8mq-evk=imx8mq-evk
 freescale/fsl-imx8mm-evk=imx8mm-evk
 rockchip/rk3399-rockpro64=rockpro64
 rockchip/rk3566-quartz64-a=quartz64
+rockchip/rk3568-rock3b=rock3b
 broadcom/bcm2711-rpi-4-b=rpi4
 avnet/maaxboard=maaxboard
 "