forked from Imagelibrary/seL4
CMake: Generate device headers from DTS for spike
The DTS compilation was arm platforms only. Moving it to the top level config file, making it available to RISCV platforms. The generated files are almost identical with minor differences. A new argument(--arch) is added to the hardware_gen.py for the differences.
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@@ -833,6 +833,7 @@ HEADER_TEMPLATE = """
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#ifndef __ASSEMBLER__
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{% if kernel -%}
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static const kernel_frame_t BOOT_RODATA kernel_devices[] = {
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{% for reg in kernel %}{{ reg.get_macro_string() }}
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{ /* {{ ' '.join(sorted(reg.names)) }} */
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@@ -843,13 +844,18 @@ static const kernel_frame_t BOOT_RODATA kernel_devices[] = {
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/* region contains {{ ', '.join(reg.var_names) }} */
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{{ "KDEV_PPTR + 0x%x" % reg.kaddr }},
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{%- endif %}
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{% if args.arch == 'arm' -%}
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{{ "true" if reg.executeNever else "false" }} /* armExecuteNever */
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{%- endif %}
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},
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{% if reg.get_macro_end() -%}
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{{ reg.get_macro_end()}}
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{% endif -%}
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{% endfor %}
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};
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{% else -%}
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static const kernel_frame_t BOOT_RODATA *kernel_devices = NULL;
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{% endif -%}
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static const p_region_t BOOT_RODATA avail_p_regs[] = {
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{%- for reg in memory %}
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@@ -857,6 +863,7 @@ static const p_region_t BOOT_RODATA avail_p_regs[] = {
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{%- endfor %}
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};
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{% if devices -%}
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static const p_region_t BOOT_RODATA dev_p_regs[] = {
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{%- for reg in devices %}
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{%- if reg.user_macro %}
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@@ -868,6 +875,9 @@ static const p_region_t BOOT_RODATA dev_p_regs[] = {
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{%- endif %}
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{%- endfor %}
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};
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{% else -%}
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static const p_region_t BOOT_RODATA *dev_p_regs = NULL;
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{% endif -%}
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#endif /* !__ASSEMBLER__ */
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@@ -891,10 +901,12 @@ static const p_region_t BOOT_RODATA dev_p_regs[] = {
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def add_build_rules(devices, output):
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devices[-1] = devices[-1] + ";"
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# print result to cmake variable
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print(';'.join(devices), file=output)
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if devices:
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devices[-1] = devices[-1] + ";"
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# print result to cmake variable
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print(';'.join(devices), file=output)
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MEGA_PAGE_SIZE = 0x200000
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def output_regions(args, devices, memory, kernel, irqs, fp):
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""" generate the device list for the C header file """
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@@ -929,14 +941,22 @@ def output_regions(args, devices, memory, kernel, irqs, fp):
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kernel += extra_kernel
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kernel.sort(key=lambda a: a.start)
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# make sure physBase is at least 16MB (supersection) aligned for the ELF loader's sake.
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# TODO: this may need to be larger for aarch64. It seems to work OK on currently supported platforms though.
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#
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# XXX: This also assumes that the kernel image is the first memory region
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# described, and propgates that assumption forward. What enforces that?
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paddr = align_up(memory[0].start, 1 << args.phys_align)
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memory[0].size -= paddr - memory[0].start
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memory[0].start = paddr
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if args.arch == 'arm':
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# make sure physBase is at least 16MB (supersection) aligned for the ELF loader's sake.
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# TODO: this may need to be larger for aarch64. It seems to work OK on currently supported platforms though.
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#
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# XXX: This also assumes that the kernel image is the first memory region
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# described, and propagates that assumption forward. What enforces that?
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paddr = align_up(memory[0].start, 1 << args.phys_align)
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memory[0].size -= paddr - memory[0].start
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memory[0].start = paddr
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elif args.arch == 'riscv':
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# BBL is loaded to the physical memory starting from "memory[0].start".
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# Moving up the start to skip the BBL memory, making it unavailable
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# to the kernel.
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paddr = memory[0].start
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memory[0].start += MEGA_PAGE_SIZE
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memory[0].size -= MEGA_PAGE_SIZE
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# Write out what we need to consume in YAML format.
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yaml_out = {
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@@ -1036,6 +1056,7 @@ if __name__ == '__main__':
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parser.add_argument('--page-bits', help='number of bits per page', default=12, type=int)
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parser.add_argument(
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'--phys-align', help='alignment in bits of the base address of the kernel', default=24, type=int)
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parser.add_argument('--arch', help='arch of the targeting platform', default="arm")
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args = parser.parse_args()
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main(args)
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else:
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