forked from Imagelibrary/rtems
204 lines
4.8 KiB
ArmAsm
204 lines
4.8 KiB
ArmAsm
/*
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* Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bspopts.h>
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#include <rtems/score/percpu.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp/vectors.h>
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.globl _start
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.globl bsp_exc_vector_base
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.section ".bsp_start_text", "ax"
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/* Primitive NULL pointer protection */
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.rept 1024
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sc
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.endr
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_start:
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/* Enable time base */
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li r0, 0x4000
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mtspr HID0, r0
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/* Initialize start stack */
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LWI r1, start_stack_end
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subi r1, r1, 16
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li r0, 0
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stw r0, 0(r1)
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SET_SELF_CPU_CONTROL r3, r4
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/* Copy fast text */
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LWI r3, bsp_section_fast_text_begin
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LWI r4, bsp_section_fast_text_load_begin
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LWI r5, bsp_section_fast_text_size
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bl copy
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/* Copy read-only data */
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LWI r3, bsp_section_rodata_begin
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LWI r4, bsp_section_rodata_load_begin
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LWI r5, bsp_section_rodata_size
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bl copy
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/* Copy fast data */
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LWI r3, bsp_section_fast_data_begin
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LWI r4, bsp_section_fast_data_load_begin
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LWI r5, bsp_section_fast_data_size
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bl copy
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/* Copy data */
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LWI r3, bsp_section_data_begin
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LWI r4, bsp_section_data_load_begin
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LWI r5, bsp_section_data_size
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bl copy
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/* Clear SBSS */
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LWI r3, bsp_section_sbss_begin
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LWI r4, bsp_section_sbss_size
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bl bsp_start_zero
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/* Clear BSS */
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LWI r3, bsp_section_bss_begin
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LWI r4, bsp_section_bss_size
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bl bsp_start_zero
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/* Set up EABI and SYSV environment */
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bl __eabi
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/* Clear command line */
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li r3, 0
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bl boot_card
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twiddle:
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b twiddle
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copy:
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cmpw r3, r4
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beqlr
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b memcpy
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/* Exception vector prologues area */
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.section ".bsp_start_text", "ax"
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.align 4
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bsp_exc_vector_base:
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/* Critical input */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 0
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b ppc_exc_fatal_critical
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/* Machine check */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 1
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b ppc_exc_fatal_machine_check
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/* Data storage */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 2
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b ppc_exc_fatal_normal
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/* Instruction storage */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 3
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b ppc_exc_fatal_normal
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/* External input */
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PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 4
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b ppc_exc_interrupt
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/* Alignment */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 5
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b ppc_exc_fatal_normal
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/* Program */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 6
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b ppc_exc_fatal_normal
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/* Floating-point unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 7
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b ppc_exc_fatal_normal
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/* System call */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 8
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b ppc_exc_fatal_normal
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/* APU unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 9
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b ppc_exc_fatal_normal
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/* Decrementer */
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PPC_REG_STORE_UPDATE r1, -PPC_EXC_INTERRUPT_FRAME_SIZE(r1)
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PPC_REG_STORE r3, PPC_EXC_GPR3_PROLOGUE_OFFSET(r1)
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li r3, 10
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b ppc_exc_interrupt
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/* Fixed-interval timer interrupt */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 11
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b ppc_exc_fatal_normal
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/* Watchdog timer interrupt */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 12
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b ppc_exc_fatal_critical
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/* Data TLB error */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 13
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b ppc_exc_fatal_normal
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/* Instruction TLB error */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 14
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b ppc_exc_fatal_normal
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/* Debug */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 15
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b ppc_exc_fatal_debug
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/* SPE APU unavailable or AltiVec unavailable */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 32
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b ppc_exc_fatal_normal
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/* SPE floating-point data exception or AltiVec assist */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 33
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b ppc_exc_fatal_normal
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/* SPE floating-point round exception */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 34
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b ppc_exc_fatal_normal
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/* Performance monitor */
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PPC_REG_STORE_UPDATE r1, -EXC_GENERIC_SIZE(r1)
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PPC_REG_STORE r3, GPR3_OFFSET(r1)
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li r3, 35
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b ppc_exc_fatal_normal
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/* Start stack area */
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.section ".bsp_rwextra", "aw", @nobits
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.align 4
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.space 4096
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start_stack_end:
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