Files
rtems/c
Daniel Hellstrom fa40ec5288 SPARC BSPs: added CPU aware interrupt ctrl operations
The LEON2 and ERC32 maps the new macros to CPU0 since they do not
support SMP. With the LEON3 a specific CPU's interrupt controller
registers can be modified using macros.
2014-10-09 09:07:22 +02:00
..
2012-07-19 15:47:55 +02:00