forked from Imagelibrary/rtems
627 lines
16 KiB
C
627 lines
16 KiB
C
/* L4STAT APB-Register Driver.
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*
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* COPYRIGHT (c) 2017.
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* Cobham Gaisler AB.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <rtems/libio.h>
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#include <stdio.h>
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#include <bsp.h>
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#include <rtems/bspIo.h> /* printk */
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#include <drvmgr/drvmgr.h>
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#include <grlib/ambapp_bus.h>
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#include <grlib/l4stat.h>
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/*#define STATIC*/
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#define STATIC static
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/*#define DEBUG 1*/
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#ifdef DEBUG
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#define DBG(x...) printf(x)
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#else
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#define DBG(x...)
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#endif
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#define REG_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (unsigned int)(val))
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#define REG_READ(addr) (*(volatile unsigned int *)(addr))
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/*
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* L4STAT CCTRL register fields
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* DEFINED IN HEADER file
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*/
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struct l4stat_regs {
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unsigned int cval[32]; /* 0x000 */
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unsigned int cctrl[32]; /* 0x080 */
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unsigned int cmax[32]; /* 0x100 */
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unsigned int timestamp; /* 0x180 */
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};
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struct l4stat_priv {
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struct drvmgr_dev *dev;
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/* L4STAT control registers */
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struct l4stat_regs *regs;
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/* L4STAT driver register */
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char devname[9];
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int ncpu;
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int ncnt;
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/* L4stat capabilities */
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int max_count_support;
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int internalahb_event_support;
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int dsu_event_support;
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int external_event_support;
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int ahbtrace_event_support;
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};
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STATIC struct l4stat_priv *l4statpriv = NULL;
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/* Event names */
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#ifdef DEBUG
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#define L4STAT_BAD_CMD "N/A. Wrong event"
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STATIC const char *l4stat_event_names[] = {
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"Instruction cache miss", /* 0x00 */
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"Instruction MMU TLB miss", /* 0x01 */
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"Instruction cache hold", /* 0x02 */
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"Instruction MMU hold", /* 0x03 */
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L4STAT_BAD_CMD, /* 0x04 */
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L4STAT_BAD_CMD, /* 0x05 */
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L4STAT_BAD_CMD, /* 0x06 */
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L4STAT_BAD_CMD, /* 0x07 */
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"Data cache (read) miss", /* 0x08 */
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"Data MMU TLB miss", /* 0x09 */
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"Data cache hold", /* 0x0a */
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"Data MMU hold", /* 0x0b */
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L4STAT_BAD_CMD, /* 0x0c */
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L4STAT_BAD_CMD, /* 0x0d */
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L4STAT_BAD_CMD, /* 0x0e */
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L4STAT_BAD_CMD, /* 0x0f */
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"Data write buffer hold", /* 0x10 */
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"Total instruction count", /* 0x11 */
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"Integer instruction count", /* 0x12 */
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"Floating-point unit instruction count", /* 0x13 */
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"Branch prediction miss", /* 0x14 */
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"Execution time, exluding debug mode", /* 0x15 */
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L4STAT_BAD_CMD, /* 0x16 */
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"AHB utilization (per AHB master)", /* 0x17 */
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"AHB utilization (total)", /* 0x18 */
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L4STAT_BAD_CMD, /* 0x19 */
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L4STAT_BAD_CMD, /* 0x1a */
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L4STAT_BAD_CMD, /* 0x1b */
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L4STAT_BAD_CMD, /* 0x1c */
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L4STAT_BAD_CMD, /* 0x1d */
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L4STAT_BAD_CMD, /* 0x1e */
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L4STAT_BAD_CMD, /* 0x1f */
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L4STAT_BAD_CMD, /* 0x20 */
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L4STAT_BAD_CMD, /* 0x21 */
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"Integer branches", /* 0x22 */
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L4STAT_BAD_CMD, /* 0x23 */
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L4STAT_BAD_CMD, /* 0x24 */
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L4STAT_BAD_CMD, /* 0x25 */
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L4STAT_BAD_CMD, /* 0x26 */
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L4STAT_BAD_CMD, /* 0x27 */
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"CALL instructions", /* 0x28 */
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L4STAT_BAD_CMD, /* 0x29 */
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L4STAT_BAD_CMD, /* 0x2a */
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L4STAT_BAD_CMD, /* 0x2b */
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L4STAT_BAD_CMD, /* 0x2c */
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L4STAT_BAD_CMD, /* 0x2d */
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L4STAT_BAD_CMD, /* 0x2e */
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L4STAT_BAD_CMD, /* 0x2f */
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"Regular type 2 instructions", /* 0x30 */
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L4STAT_BAD_CMD, /* 0x31 */
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L4STAT_BAD_CMD, /* 0x32 */
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L4STAT_BAD_CMD, /* 0x33 */
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L4STAT_BAD_CMD, /* 0x34 */
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L4STAT_BAD_CMD, /* 0x35 */
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L4STAT_BAD_CMD, /* 0x36 */
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L4STAT_BAD_CMD, /* 0x37 */
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"LOAD and STORE instructions", /* 0x38 */
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"LOAD instructions", /* 0x39 */
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"STORE instructions", /* 0x3a */
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L4STAT_BAD_CMD, /* 0x3b */
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L4STAT_BAD_CMD, /* 0x3c */
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L4STAT_BAD_CMD, /* 0x3d */
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L4STAT_BAD_CMD, /* 0x3e */
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L4STAT_BAD_CMD, /* 0x3f */
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"AHB IDLE cycles", /* 0x40 */
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"AHB BUSY cycles", /* 0x41 */
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"AHB Non-Seq. transfers", /* 0x42 */
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"AHB Seq. transfers", /* 0x43 */
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"AHB read accesses", /* 0x44 */
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"AHB write accesses", /* 0x45 */
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"AHB byte accesses", /* 0x46 */
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"AHB half-word accesses", /* 0x47 */
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"AHB word accesses", /* 0x48 */
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"AHB double word accesses", /* 0x49 */
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"AHB quad word accesses", /* 0x4A */
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"AHB eight word accesses", /* 0x4B */
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"AHB waitstates", /* 0x4C */
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"AHB RETRY responses", /* 0x4D */
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"AHB SPLIT responses", /* 0x4E */
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"AHB SPLIT delay", /* 0x4F */
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"AHB bus locked", /* 0x50 */
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L4STAT_BAD_CMD, /* 0x51 */
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L4STAT_BAD_CMD, /* 0x52 */
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L4STAT_BAD_CMD, /* 0x53 */
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L4STAT_BAD_CMD, /* 0x54 */
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L4STAT_BAD_CMD, /* 0x55 */
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L4STAT_BAD_CMD, /* 0x56 */
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L4STAT_BAD_CMD, /* 0x57 */
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L4STAT_BAD_CMD, /* 0x58 */
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L4STAT_BAD_CMD, /* 0x59 */
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L4STAT_BAD_CMD, /* 0x5a */
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L4STAT_BAD_CMD, /* 0x5b */
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L4STAT_BAD_CMD, /* 0x5c */
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L4STAT_BAD_CMD, /* 0x5d */
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L4STAT_BAD_CMD, /* 0x5e */
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L4STAT_BAD_CMD, /* 0x5f */
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"external event 0", /* 0x60 */
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"external event 1", /* 0x61 */
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"external event 2", /* 0x62 */
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"external event 3", /* 0x63 */
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"external event 4", /* 0x64 */
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"external event 5", /* 0x65 */
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"external event 6", /* 0x66 */
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"external event 7", /* 0x67 */
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"external event 8", /* 0x68 */
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"external event 9", /* 0x69 */
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"external event 10", /* 0x6A */
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"external event 11", /* 0x6B */
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"external event 12", /* 0x6C */
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"external event 13", /* 0x6D */
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"external event 14", /* 0x6E */
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"external event 15", /* 0x6F */
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"AHB IDLE cycles (2)", /* 0x70 */
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"AHB BUSY cycles (2)", /* 0x71 */
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"AHB Non-Seq. transfers (2)", /* 0x72 */
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"AHB Seq. transfers (2)", /* 0x73 */
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"AHB read accesses (2)", /* 0x74 */
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"AHB write accesses (2)", /* 0x75 */
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"AHB byte accesses (2)", /* 0x76 */
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"AHB half-word accesses (2)", /* 0x77 */
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"AHB word accesses (2)", /* 0x78 */
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"AHB double word accesses (2)", /* 0x79 */
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"AHB quad word accesses (2)", /* 0x7A */
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"AHB eight word accesses (2)", /* 0x7B */
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"AHB waitstates (2)", /* 0x7C */
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"AHB RETRY responses (2)", /* 0x7D */
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"AHB SPLIT responses (2)", /* 0x7E */
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"AHB SPLIT delay (2)", /* 0x7F */
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"PMC: master 0 has grant", /* 0x80 */
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"PMC: master 1 has grant", /* 0x81 */
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"PMC: master 2 has grant", /* 0x82 */
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"PMC: master 3 has grant", /* 0x83 */
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"PMC: master 4 has grant", /* 0x84 */
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"PMC: master 5 has grant", /* 0x85 */
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"PMC: master 6 has grant", /* 0x86 */
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"PMC: master 7 has grant", /* 0x87 */
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"PMC: master 8 has grant", /* 0x88 */
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"PMC: master 9 has grant", /* 0x89 */
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"PMC: master 10 has grant", /* 0x8A */
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"PMC: master 11 has grant", /* 0x8B */
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"PMC: master 12 has grant", /* 0x8C */
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"PMC: master 13 has grant", /* 0x8D */
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"PMC: master 14 has grant", /* 0x8E */
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"PMC: master 15 has grant", /* 0x8F */
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"PMC: master 0 lacks grant", /* 0x90 */
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"PMC: master 1 lacks grant", /* 0x91 */
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"PMC: master 2 lacks grant", /* 0x92 */
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"PMC: master 3 lacks grant", /* 0x93 */
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"PMC: master 4 lacks grant", /* 0x94 */
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"PMC: master 5 lacks grant", /* 0x95 */
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"PMC: master 6 lacks grant", /* 0x96 */
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"PMC: master 7 lacks grant", /* 0x97 */
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"PMC: master 8 lacks grant", /* 0x98 */
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"PMC: master 9 lacks grant", /* 0x99 */
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"PMC: master 10 lacks grant", /* 0x9A */
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"PMC: master 11 lacks grant", /* 0x9B */
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"PMC: master 12 lacks grant", /* 0x9C */
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"PMC: master 13 lacks grant", /* 0x9D */
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"PMC: master 14 lacks grant", /* 0x9E */
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"PMC: master 15 lacks grant", /* 0x9F */
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""
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};
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#endif /* DEBUG */
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/* Driver prototypes */
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STATIC int l4stat_init(struct l4stat_priv *priv);
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int l4stat_init1(struct drvmgr_dev *dev);
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struct drvmgr_drv_ops l4stat_ops =
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{
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.init = {l4stat_init1, NULL, NULL, NULL},
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.remove = NULL,
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.info = NULL
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};
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struct amba_dev_id l4stat_ids[] =
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{
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{VENDOR_GAISLER, GAISLER_L4STAT},
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{VENDOR_GAISLER, GAISLER_L3STAT},
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{0, 0} /* Mark end of table */
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};
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struct amba_drv_info l4stat_drv_info =
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{
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{
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DRVMGR_OBJ_DRV, /* Driver */
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NULL, /* Next driver */
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NULL, /* Device list */
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DRIVER_AMBAPP_GAISLER_L4STAT_ID,/* Driver ID */
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"L4STAT_DRV", /* Driver Name */
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DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
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&l4stat_ops,
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NULL, /* Funcs */
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0, /* No devices yet */
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sizeof(struct l4stat_priv), /* Let DRVMGR allocate for us */
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},
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&l4stat_ids[0],
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};
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void l4stat_register_drv (void)
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{
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DBG("Registering L4STAT driver\n");
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drvmgr_drv_register(&l4stat_drv_info.general);
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}
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STATIC int l4stat_init(struct l4stat_priv *priv)
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{
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struct ambapp_apb_info *apb;
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struct amba_dev_info *ainfo = priv->dev->businfo;
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unsigned int tmp;
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unsigned short dev_id;
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/* Find L4STAT core from Plug&Play information */
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apb = ainfo->info.apb_slv;
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/* Check if L4STAT or L3STAT core from Plug&Play information */
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dev_id = ainfo->id.device;
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/* Check if rev 1 of core (only rev 0 supported) */
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if (apb->common.ver != 0) {
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DBG("L4STAT rev 0 only supported.\n");
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return L4STAT_ERR_ERROR;
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}
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/* Found L4STAT core, init private structure */
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priv->regs = (struct l4stat_regs *)apb->start;
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DBG("L4STAT regs 0x%08x\n", (unsigned int) priv->regs);
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/* Find L4STAT capabilities */
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tmp = REG_READ(&priv->regs->cctrl[0]);
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/* The CPU field in the register is just information of the
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* cpus that are connected to the stat unit, but it is not
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* really used for anything else. I can still have more masters
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* on the bus (e.g. IOMMU) that I can collect stats from,
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* so it makes no sense to limit the cpus to the actual cpus.
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* Therefore, I will take the maximum number as 16. */
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/*priv->ncpu = ((tmp & CCTRL_NCPU) >> CCTRL_NCPU_BIT) + 1;*/
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priv->ncpu = 16;
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if (dev_id == GAISLER_L3STAT) {
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priv->ncnt = ((tmp & CCTRL_NCNT_L3STAT) >> CCTRL_NCNT_BIT) + 1;
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}else{
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priv->ncnt = ((tmp & CCTRL_NCNT) >> CCTRL_NCNT_BIT) + 1;
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}
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priv->max_count_support = (tmp & CCTRL_MC) >> CCTRL_MC_BIT;
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priv->internalahb_event_support = (tmp & CCTRL_IA) >> CCTRL_IA_BIT;
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priv->dsu_event_support = (tmp & CCTRL_DS) >> CCTRL_DS_BIT;
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priv->external_event_support = (tmp & CCTRL_EE) >> CCTRL_EE_BIT;
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priv->ahbtrace_event_support = (tmp & CCTRL_AE) >> CCTRL_AE_BIT;
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/* DEBUG print */
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DBG("L4STAT with following capabilities:\n");
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DBG(" -NCPU: %d, NCNT: %d, MaxCNT: %s\n", priv->ncpu, priv->ncnt,
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(priv->max_count_support?"Available":"N/A"));
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DBG(" -Events= InternalAHB: %s, DSU: %s, External: %s, AHBTRACE: %s\n",
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(priv->internalahb_event_support?"Available":"N/A"),
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(priv->dsu_event_support?"Available":"N/A"),
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(priv->external_event_support?"Available":"N/A"),
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(priv->ahbtrace_event_support?"Available":"N/A"));
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return L4STAT_ERR_OK;
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}
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int l4stat_init1(struct drvmgr_dev *dev)
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{
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struct l4stat_priv *priv = dev->priv;
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DBG("L4STAT[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
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if (l4statpriv) {
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DBG("Driver only supports one L4STAT core\n");
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return DRVMGR_FAIL;
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}
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if (priv == NULL) {
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return DRVMGR_NOMEM;
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}
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priv->dev = dev;
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l4statpriv = priv;
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/* Initilize driver struct */
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if (l4stat_init(priv) != L4STAT_ERR_OK) {
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return DRVMGR_FAIL;
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}
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/* Startup Action:
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* - None
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*/
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/* Device name */
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sprintf(priv->devname, "l4stat0");
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return DRVMGR_OK;
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}
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int l4stat_counter_enable(unsigned int counter, int event, int cpu, int options)
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{
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struct l4stat_priv *priv = l4statpriv;
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unsigned int ctrl;
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if (priv == NULL) {
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DBG("L4STAT Device not initialized\n");
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return L4STAT_ERR_EINVAL;
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}
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if (counter >= priv->ncnt) {
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DBG("L4STAT Wrong counter\n");
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return L4STAT_ERR_EINVAL;
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}
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if ((cpu < 0) || (cpu >= priv->ncpu)) {
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DBG("L4STAT Wrong cpu\n");
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return L4STAT_ERR_EINVAL;
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}
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if ((options & L4STAT_OPTIONS_MAXIMUM_DURATION) ||
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(options & L4STAT_OPTIONS_EVENT_LEVEL_ENABLE)) {
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if (priv->max_count_support == 0) {
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DBG("L4STAT maximum duration count not supported\n");
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return L4STAT_ERR_IMPLEMENTED;
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}
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}
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/* Check event is supported */
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if ((event < 0) || (event >= 0x80)) {
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DBG("L4STAT Wrong event\n");
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return L4STAT_ERR_EINVAL;
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}
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if ((event == 0x18) || (event == 0x17)) {
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if (priv->internalahb_event_support == 0) {
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DBG("L4STAT internal ahb event not supported\n");
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return L4STAT_ERR_IMPLEMENTED;
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}
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}
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if ((event >= 0x40) && (event < 0x60)) {
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if (priv->dsu_event_support == 0) {
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DBG("L4STAT dsu event not supported\n");
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return L4STAT_ERR_IMPLEMENTED;
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}
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}
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if ((event >= 0x60) && (event < 0x70)) {
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if (priv->external_event_support == 0) {
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DBG("L4STAT external event not supported\n");
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return L4STAT_ERR_IMPLEMENTED;
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}
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}
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if ((event >= 0x70) && (event < 0x80)) {
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if (priv->ahbtrace_event_support == 0) {
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DBG("L4STAT ahbtrace event not supported\n");
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return L4STAT_ERR_IMPLEMENTED;
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}
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}
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/* Prepare counter control */
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ctrl = (options & ~(CCTRL_EVENTID | CCTRL_CPUAHBM));
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/* Put event id */
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ctrl = (ctrl | ((event << CCTRL_EVENTID_BIT) & CCTRL_EVENTID));
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/* Put cpu id */
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ctrl = (ctrl | ((cpu << CCTRL_CPUAHBM_BIT) & CCTRL_CPUAHBM));
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/* Enable counter */
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ctrl = (ctrl | CCTRL_EN);
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REG_WRITE(&priv->regs->cctrl[counter], ctrl);
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/* DEBUG print */
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DBG("L4STAT COUNTER[%d] enabled with event: %s, cpu: %d\n", counter,
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l4stat_event_names[event],cpu);
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return L4STAT_ERR_OK;
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}
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int l4stat_counter_disable(unsigned int counter)
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{
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struct l4stat_priv *priv = l4statpriv;
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if (priv == NULL) {
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DBG("L4STAT Device not initialized\n");
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return L4STAT_ERR_EINVAL;
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}
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if (counter >= priv->ncnt) {
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DBG("L4STAT Wrong counter\n");
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return L4STAT_ERR_EINVAL;
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}
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/* Disable counter */
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REG_WRITE(&priv->regs->cctrl[counter], 0);
|
|
|
|
/* DEBUG print */
|
|
DBG("L4STAT COUNTER[%d] disabled\n", counter);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_counter_get(unsigned int counter, uint32_t * val)
|
|
{
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (counter >= priv->ncnt) {
|
|
DBG("L4STAT Wrong counter\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (val == NULL) {
|
|
DBG("L4STAT Wrong pointer\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
*val = REG_READ(&priv->regs->cval[counter]);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_counter_set(unsigned int counter, uint32_t val)
|
|
{
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (counter >= priv->ncnt) {
|
|
DBG("L4STAT Wrong counter\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
REG_WRITE(&priv->regs->cval[counter],val);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_counter_max_get(unsigned int counter, uint32_t * val)
|
|
{
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (counter >= priv->ncnt) {
|
|
DBG("L4STAT Wrong counter\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (val == NULL) {
|
|
DBG("L4STAT Wrong pointer\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
*val = REG_READ(&priv->regs->cmax[counter]);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_counter_max_set(unsigned int counter, uint32_t val)
|
|
{
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (counter >= priv->ncnt) {
|
|
DBG("L4STAT Wrong counter\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
REG_WRITE(&priv->regs->cmax[counter],val);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_tstamp_get(uint32_t * val)
|
|
{
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (val == NULL) {
|
|
DBG("L4STAT Wrong pointer\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
*val = REG_READ(&priv->regs->timestamp);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_tstamp_set(uint32_t val)
|
|
{
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
REG_WRITE(&priv->regs->timestamp,val);
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
int l4stat_counter_print(unsigned int counter)
|
|
{
|
|
#ifdef DEBUG
|
|
struct l4stat_priv *priv = l4statpriv;
|
|
unsigned int val;
|
|
unsigned int ctrl;
|
|
unsigned int event;
|
|
|
|
if (priv == NULL) {
|
|
DBG("L4STAT Device not initialized\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
if (counter >= priv->ncnt) {
|
|
DBG("L4STAT Wrong counter\n");
|
|
return L4STAT_ERR_EINVAL;
|
|
}
|
|
|
|
/* Get counter val*/
|
|
val = REG_READ(&priv->regs->cval[counter]);
|
|
|
|
/* Get counter info*/
|
|
ctrl = REG_READ(&priv->regs->cctrl[counter]);
|
|
if ((ctrl & CCTRL_EN) == 0) {
|
|
DBG("L4STAT COUNTER[%d] disabled\n", counter);
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|
|
event = (ctrl & CCTRL_EVENTID) >> CCTRL_EVENTID_BIT;
|
|
|
|
/* DEBUG print */
|
|
DBG("L4STAT COUNTER[%d], Event: %s, Count: %d [0x%08x]\n",
|
|
counter, l4stat_event_names[event],val,val);
|
|
#endif /* DEBUG */
|
|
|
|
return L4STAT_ERR_OK;
|
|
}
|
|
|