forked from Imagelibrary/rtems
330 lines
8.7 KiB
ArmAsm
330 lines
8.7 KiB
ArmAsm
/*
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* This file contains the implementation of the function described in irq.h
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*/
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/*
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* Copyright (C) 1998 valette@crf.canon.fr
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*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <rtems/system.h>
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#include <bspopts.h>
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#include <bsp/irq_asm.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/percpu.h>
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#include <bsp.h> /* to establish dependency on prototype */
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#ifndef CPU_STACK_ALIGNMENT
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#error "Missing header? CPU_STACK_ALIGNMENT is not defined here"
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#endif
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/* Stack frame we use for intermediate storage */
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#define ARG_OFF 0
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#define MSK_OFF 4
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#define EBX_OFF 8 /* ebx */
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#define EBP_OFF 12 /* code restoring ebp/esp relies on */
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#define ESP_OFF 16 /* esp being on top of ebp! */
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#ifdef __SSE__
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/* need to be on 16 byte boundary for SSE, add 12 to do that */
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#define FRM_SIZ (20+12+512)
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#define SSE_OFF 32
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#else
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#define FRM_SIZ 20
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#endif
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BEGIN_CODE
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SYM (_ISR_Handler):
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/*
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* Before this was point is reached the vectors unique
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* entry point did the following:
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*
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* 1. saved scratch registers registers eax edx ecx"
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* 2. put the vector number in ecx.
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*
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* BEGINNING OF ESTABLISH SEGMENTS
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*
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* WARNING: If an interrupt can occur when the segments are
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* not correct, then this is where we should establish
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* the segments. In addition to establishing the
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* segments, it may be necessary to establish a stack
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* in the current data area on the outermost interrupt.
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*
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* NOTE: If the previous values of the segment registers are
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* pushed, do not forget to adjust SAVED_REGS.
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*
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* NOTE: Make sure the exit code which restores these
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* when this type of code is needed.
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*/
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/***** ESTABLISH SEGMENTS CODE GOES HERE ******/
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/*
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* END OF ESTABLISH SEGMENTS
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*/
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/*
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* Establish an aligned stack frame
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* original sp
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* saved ebx
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* saved ebp
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* saved irq mask
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* vector arg to C_dispatch_isr <- aligned SP
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*/
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movl esp, eax
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subl $FRM_SIZ, esp
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andl $ - CPU_STACK_ALIGNMENT, esp
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movl ebx, EBX_OFF(esp)
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movl eax, ESP_OFF(esp)
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movl ebp, EBP_OFF(esp)
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#ifdef __SSE__
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/* NOTE: SSE only is supported if the BSP enables fxsave/fxrstor
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* to save/restore SSE context! This is so far only implemented
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* for pc386!.
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*/
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/* We save SSE here (on the task stack) because we possibly
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* call other C-code (besides the ISR, namely _Thread_Dispatch())
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*/
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/* don't wait here; a possible exception condition will eventually be
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* detected when the task resumes control and executes a FP instruction
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fwait
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*/
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fxsave SSE_OFF(esp)
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fninit /* clean-slate FPU */
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movl $0x1f80, ARG_OFF(esp) /* use ARG_OFF as scratch space */
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ldmxcsr ARG_OFF(esp) /* clean-slate MXCSR */
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#endif
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/* Do not disable any 8259 interrupts if this isn't from one */
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cmp ecx, 16 /* is this a PIC IRQ? */
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jge .check_stack_switch
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/*
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* acknowledge the interrupt
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*/
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movw SYM (i8259s_cache), ax /* save current i8259 interrupt mask */
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movl eax, MSK_OFF(esp) /* save in stack frame */
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/*
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* compute the new PIC mask:
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*
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* <new mask> = <old mask> | irq_mask_or_tbl[<intr number aka ecx>]
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*/
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movw SYM (irq_mask_or_tbl) (,ecx,2), dx
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orw dx, ax
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/*
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* Install new computed value on the i8259 and update cache
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* accordingly
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*/
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movw ax, SYM (i8259s_cache)
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outb $PIC_MASTER_IMR_IO_PORT
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movb ah, al
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outb $PIC_SLAVE_IMR_IO_PORT
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movb $PIC_EOI, al
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cmpl $7, ecx
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jbe .master
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outb $PIC_SLAVE_COMMAND_IO_PORT
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.master:
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outb $PIC_MASTER_COMMAND_IO_PORT
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/*
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* Now switch stacks if necessary
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*/
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PUBLIC (ISR_STOP)
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ISR_STOP:
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.check_stack_switch:
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movl esp, ebp /* ebp = previous stack pointer */
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#ifdef RTEMS_SMP
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call SYM(_CPU_SMP_Get_current_processor)
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sall $PER_CPU_CONTROL_SIZE_LOG2, eax
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addl $SYM(_Per_CPU_Information), eax
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movl eax, ebx
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#else
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movl $SYM(_Per_CPU_Information), ebx
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#endif
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/* is this the outermost interrupt? */
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cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx)
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jne nested /* No, then continue */
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movl PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp
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/*
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* We want to insure that the old stack pointer is in ebp
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* By saving it on every interrupt, all we have to do is
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* movl ebp->esp near the end of every interrupt.
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*/
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nested:
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incl PER_CPU_ISR_NEST_LEVEL(ebx) /* one nest level deeper */
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incl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx) /* disable
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multitasking */
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/*
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* GCC versions starting with 4.3 no longer place the cld
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* instruction before string operations. We need to ensure
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* it is set correctly for ISR handlers.
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*/
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cld
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/*
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* re-enable interrupts at processor level as the current
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* interrupt source is now masked via i8259
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*/
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sti
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/*
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* ECX is preloaded with the vector number; store as arg
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* on top of stack. Note that _CPU_Interrupt_stack_high
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* was adjusted in _CPU_Interrupt_stack_setup() (score/rtems/cpu.h)
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* to make sure there is space.
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*/
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movl ecx, ARG_OFF(esp) /* store vector arg in stack */
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call C_dispatch_isr
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/*
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* disable interrupts_again
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*/
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cli
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movl ARG_OFF(esp), ecx /* grab vector arg from stack */
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/*
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* Restore stack. This moves back to the task stack
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* when all interrupts are unnested.
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*/
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movl ebp, esp
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/*
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* restore the original i8259 masks
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*/
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/* Do not touch 8259 interrupts if this isn't from one */
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cmp ecx, 16 /* is this a PIC IRQ? */
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jge .dont_restore_i8259
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movw SYM (i8259s_super_imr), dx
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movl MSK_OFF(esp), eax
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orw dx, ax
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movw ax, SYM (i8259s_cache)
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outb $PIC_MASTER_IMR_IO_PORT
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movb ah, al
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outb $PIC_SLAVE_IMR_IO_PORT
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.dont_restore_i8259:
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decl PER_CPU_ISR_NEST_LEVEL(ebx) /* one less ISR nest level */
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/* If interrupts are nested, */
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/* then dispatching is disabled */
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decl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx)
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/* unnest multitasking */
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/* Is dispatch disabled */
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jne .exit /* Yes, then exit */
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cmpb $0, PER_CPU_DISPATCH_NEEDED(ebx)
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/* Is task switch necessary? */
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jne .schedule /* Yes, then call the scheduler */
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jmp .exit /* No, exit */
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.schedule:
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/*
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* the scratch registers have already been saved and we are already
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* back on the thread system stack. So we can call _Thread_Dispatch
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* directly
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*/
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call _Thread_Dispatch
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/*
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* fall through exit to restore complete contex (scratch registers
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* eip, CS, Flags).
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*/
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.exit:
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#ifdef __SSE__
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fwait
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fxrstor SSE_OFF(esp)
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#endif
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/* restore ebx, ebp and original esp */
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addl $EBX_OFF, esp
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popl ebx
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popl ebp
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popl esp
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/*
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* BEGINNING OF DE-ESTABLISH SEGMENTS
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*
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* NOTE: Make sure there is code here if code is added to
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* load the segment registers.
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*
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*/
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/******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/
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/*
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* END OF DE-ESTABLISH SEGMENTS
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*/
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popl edx
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popl ecx
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popl eax
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iret
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#define DISTINCT_INTERRUPT_ENTRY(_vector) \
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.p2align 4 ; \
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PUBLIC (rtems_irq_prologue_ ## _vector ) ; \
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SYM (rtems_irq_prologue_ ## _vector ): \
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pushl eax ; \
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pushl ecx ; \
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pushl edx ; \
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movl $ _vector, ecx ; \
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jmp SYM (_ISR_Handler) ;
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DISTINCT_INTERRUPT_ENTRY(0)
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DISTINCT_INTERRUPT_ENTRY(1)
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DISTINCT_INTERRUPT_ENTRY(2)
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DISTINCT_INTERRUPT_ENTRY(3)
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DISTINCT_INTERRUPT_ENTRY(4)
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DISTINCT_INTERRUPT_ENTRY(5)
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DISTINCT_INTERRUPT_ENTRY(6)
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DISTINCT_INTERRUPT_ENTRY(7)
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DISTINCT_INTERRUPT_ENTRY(8)
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DISTINCT_INTERRUPT_ENTRY(9)
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DISTINCT_INTERRUPT_ENTRY(10)
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DISTINCT_INTERRUPT_ENTRY(11)
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DISTINCT_INTERRUPT_ENTRY(12)
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DISTINCT_INTERRUPT_ENTRY(13)
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DISTINCT_INTERRUPT_ENTRY(14)
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DISTINCT_INTERRUPT_ENTRY(15)
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DISTINCT_INTERRUPT_ENTRY(16)
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/*
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* routine used to initialize the IDT by default
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*/
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PUBLIC (default_raw_idt_handler)
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PUBLIC (raw_idt_notify)
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SYM (default_raw_idt_handler):
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pusha
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cld
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mov esp, ebp
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andl $ - CPU_STACK_ALIGNMENT, esp
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call raw_idt_notify
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mov ebp, esp
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popa
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iret
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END_CODE
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END
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