forked from Imagelibrary/rtems
81aec18146
We have to be careful with instructions which operate explicitly on words or doublewords. Update #3082.
116 lines
2.1 KiB
ArmAsm
116 lines
2.1 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup bsp_start
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*
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* @brief bsp_start_zero() implementation.
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*/
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/*
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* Copyright (c) 2010-2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <libcpu/powerpc-utility.h>
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#include <bspopts.h>
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.globl bsp_start_zero
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.globl bsp_start_zero_begin
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.globl bsp_start_zero_end
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.globl bsp_start_zero_size
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.section ".bsp_start_text", "ax"
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.type bsp_start_zero, @function
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bsp_start_zero:
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bsp_start_zero_begin:
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li r0, 0
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subi r11, r3, 1
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CLEAR_RIGHT_IMMEDIATE r11, r11, PPC_CACHE_ALIGN_POWER
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addi r10, r11, PPC_CACHE_ALIGNMENT
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subf r11, r3, r10
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COMPARE_LOGICAL cr7, r11, r4
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add r9, r3, r4
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ble- cr7, head_end_done
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mr r10, r9
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head_end_done:
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subf r11, r3, r10
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addi r11, r11, 1
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mtctr r11
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/* Head loop */
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b head_loop_update
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head_loop_begin:
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stb r0, 0(r3)
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addi r3, r3, 1
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head_loop_update:
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bdnz+ head_loop_begin
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subf r11, r3, r9
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SHIFT_RIGHT_IMMEDIATE r11, r11, PPC_CACHE_ALIGN_POWER
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addi r11, r11, 1
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mtctr r11
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/* Main loop */
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b main_loop_update
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main_loop_begin:
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#if BSP_DATA_CACHE_ENABLED
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dcbz r0, r3
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dcbf r0, r3
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#else
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#if PPC_CACHE_ALIGNMENT == 32 || PPC_CACHE_ALIGNMENT == 64
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stw r0, 0(r3)
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stw r0, 4(r3)
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stw r0, 8(r3)
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stw r0, 12(r3)
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stw r0, 16(r3)
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stw r0, 20(r3)
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stw r0, 24(r3)
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stw r0, 28(r3)
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#if PPC_CACHE_ALIGNMENT == 64
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stw r0, 32(r3)
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stw r0, 36(r3)
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stw r0, 40(r3)
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stw r0, 44(r3)
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stw r0, 48(r3)
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stw r0, 52(r3)
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stw r0, 56(r3)
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stw r0, 60(r3)
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#endif
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#else
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#error "unsupported cache alignment"
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#endif
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#endif
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addi r3, r3, PPC_CACHE_ALIGNMENT
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main_loop_update:
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bdnz+ main_loop_begin
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subf r9, r3, r9
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addi r9, r9, 1
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mtctr r9
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/* Tail loop */
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b tail_loop_update
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tail_loop_begin:
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stb r0, 0(r3)
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addi r3, r3, 1
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tail_loop_update:
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bdnz+ tail_loop_begin
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/* Return */
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sync
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isync
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blr
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bsp_start_zero_end:
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.set bsp_start_zero_size, bsp_start_zero_end - bsp_start_zero_begin
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