forked from Imagelibrary/rtems
198 lines
6.3 KiB
Plaintext
198 lines
6.3 KiB
Plaintext
Pulse Width Modulation subsystem includes EPWM, ECAP , EQEP. There are
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different instances available for each one. For PWM there are three
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different individual EPWM module 0 , 1 and 2. So wherever pwmss word is
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used that affects whole PWM sub system such as EPWM, ECAP and EQEP. This code
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has only implementation Non high resolution PWM module. APIs for high
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resolution PWM has been yet to develop.
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For Each EPWM instance, has two PWM channels, e.g. EPWM0 has two channel
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EPWM0A and EPWM0B. If you configure two PWM outputs(e.g. EPWM0A , EPWM0B)
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in the same device, then they *must* be configured with the same frequency.
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Changing frequency on one channel (e.g EPWMxA) will automatically change
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frequency on another channel(e.g. EPWMxB). However, it is possible to set
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different pulse-width/duty cycle to different channel at a time. So always
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set the frequency first and then pulse-width/duty cycle.
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For more you can refer :
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http://www.ofitselfso.com/BBBCSIO/Source/PWMPortEnum.cs.html
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Pulse Width Modulation uses the system frequency of Beagle Bone Black.
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System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT(By Default)
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SYCLKOUT = 100 MHz
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Please visit following link to check why SYSCLKDIV = 100MHz:
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https://groups.google.com/forum/#!topic/beagleboard/Ed2J9Txe_E4
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(Refer Technical Reference Manual (TRM) Table 15-41 as well)
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To generate different frequencies with the help of PWM module , SYSCLKOUT
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need to be scaled down, which will act as TBCLK and TBCLK will be base clock
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for the pwm subsystem.
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TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV)
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|----------------|
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| clock |
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SYSCLKOUT---> | |---> TBCLK
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| prescale |
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|----------------|
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^ ^
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TBCTL[CLKDIV]----- ------TBCTL[HSPCLKDIV]
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CLKDIV and HSPCLKDIV bits are part of the TBCTL register (Refer TRM).
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CLKDIV - These bits determine part of the time-base clock prescale value.
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Please use the following values of CLKDIV to scale down sysclk respectively.
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0h (R/W) = /1
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1h (R/W) = /2
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2h (R/W) = /4
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3h (R/W) = /8
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4h (R/W) = /16
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5h (R/W) = /32
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6h (R/W) = /64
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7h (R/W) = /128
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These bits determine part of the time-base clock prescale value.
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Please use following value of HSPCLKDIV to scale down sysclk respectively
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0h (R/W) = /1
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1h (R/W) = /2
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2h (R/W) = /4
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3h (R/W) = /6
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4h (R/W) = /8
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5h (R/W) = /10
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6h (R/W) = /12
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7h (R/W) = /14
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For example, if you set CLKDIV = 3h and HSPCLKDIV= 2h Then
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SYSCLKOUT will be divided by (1/8)(1/4). It means SYSCLKOUT/32
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How to generate frequency ?
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freq = 1/Period
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TBPRD register is responsible to generate the frequency. These bits determine
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the period of the time-base counter.
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By default TBCLK = SYSCLKOUT = 100 MHz
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Here by default period is 1/100MHz = 10 nsec
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Following example shows value to be loaded into TBPRD
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e.g. TBPRD = 1 = 1 count
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count x Period = 1 x 1ns = 1ns
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freq = 1/Period = 1 / 1ns = 100 MHz
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For duty cycle CMPA and CMPB are the responsible registers.
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To generate single with 50% Duty cycle & 100MHz freq.
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CMPA = count x Duty Cycle
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= TBPRD x Duty Cycle
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= 1 x 50/100
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= 0.2
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The value in the active CMPA register is continuously compared to
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the time-base counter (TBCNT). When the values are equal, the
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counter-compare module generates a "time-base counter equal to
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counter compare A" event. This event is sent to the action-qualifier
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where it is qualified and converted it into one or more actions.
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These actions can be applied to either the EPWMxA or the
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EPWMxB output depending on the configuration of the AQCTLA and
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AQCTLB registers.
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List of pins for that can be used for different PWM instance :
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------------------------------------------------
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| EPWM2 | EPWM1 | EPWM0 |
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------------------------------------------------
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| BBB_P8_13_2B | BBB_P8_34_1B | BBB_P9_21_0B |
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| BBB_P8_19_2A | BBB_P8_36_1A | BBB_P9_22_0A |
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| BBB_P8_45_2A | BBB_P9_14_1A | BBB_P9_29_0B |
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| BBB_P8_46_2B | BBB_P9_16_1B | BBB_P9_31_0A |
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------------------------------------------------
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BBB_P8_13_2B represents P8 Header , pin number 13 , 2nd PWM instance and B channel.
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Following sample program can be used to generate 7 Hz frequency.
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/test.h>
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#include <bsp.h>
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#include <bsp/gpio.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <bsp/bbb-pwm.h>
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const char rtems_test_name[] = "Testing PWM driver";
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rtems_printer rtems_test_printer;
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static void inline delay_sec(int sec)
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{
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rtems_task_wake_after(sec*rtems_clock_get_ticks_per_second());
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}
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rtems_task Init(rtems_task_argument argument);
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rtems_task Init(
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rtems_task_argument ignored
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)
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{
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rtems_test_begin();
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printf("Starting PWM Testing");
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/*Initialize GPIO pins in BBB*/
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rtems_gpio_initialize();
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/* Set P9 Header , 21 Pin number , PWM B channel and 0 PWM instance to generate frequency*/
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beagle_epwm_pinmux_setup(BBB_P9_21_0B,BBB_PWMSS0);
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/** Initialize clock for PWM sub system
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* Turn on time base clock for PWM o instance
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*/
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beagle_pwm_init(BBB_PWMSS0);
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float PWM_HZ = 7.0f ; /* 7 Hz */
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float duty_A = 20.0f ; /* 20% Duty cycle for PWM 0_A output */
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const float duty_B = 50.0f ; /* 50% Duty cycle for PWM 0_B output*/
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/*Note: Always check whether pwmss clocks are enabled or not before configuring PWM*/
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bool is_running = beagle_pwmss_is_running(BBB_PWMSS2);
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if(is_running) {
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/*To analyse the two different duty cycle Output should be observed at P8_45 and P8_46 pin number */
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beagle_pwm_configure(BBB_PWMSS0, PWM_HZ ,duty_A , duty_B);
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printf("PWM enable for 10s ....\n");
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/*Set Up counter and enable pwm module */
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beagle_pwm_enable(BBB_PWMSS0);
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delay_sec(10);
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/*freeze the counter and disable pwm module*/
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beagle_epwm_disable(BBB_PWMSS0);
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}
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}
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/* NOTICE: the clock driver is enabled */
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#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
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#define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER
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#define CONFIGURE_MAXIMUM_TASKS 1
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#define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM
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#define CONFIGURE_MAXIMUM_SEMAPHORES 1
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#define CONFIGURE_RTEMS_INIT_TASKS_TABLE
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#define CONFIGURE_EXTRA_TASK_STACKS (2 * RTEMS_MINIMUM_STACK_SIZE)
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#define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION
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#define CONFIGURE_INIT
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#include <rtems/confdefs.h>
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