forked from Imagelibrary/rtems
f6083f08dd
* shared/lpc/include/lpc-emc.h, shared/lpc/include/lpc-lcd.h: New files. * shared/lpc/include/lpc-dma.h: API changes. * shared/lpc/clock/lpc-clock-config.c: Fixed nano seconds extension. * shared/lpc/network/lpc-ethernet.c: Format. Multicast hash filter support.
171 lines
3.5 KiB
C
171 lines
3.5 KiB
C
/**
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* @file
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*
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* @ingroup lpc_emc
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*
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* @brief EMC support API.
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*/
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/*
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* Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H
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#define LIBBSP_ARM_SHARED_LPC_EMC_H
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#include <bsp/utility.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @defgroup lpc_emc EMC Support
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*
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* @ingroup lpc24xx
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* @ingroup lpc32xx
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*
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* @brief EMC Support
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*
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* @{
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*/
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/**
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* @name EMC Control Register (EMCControl)
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*
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* @{
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*/
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#define EMC_CTRL_E BSP_BIT32(0)
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#define EMC_CTRL_M BSP_BIT32(0)
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#define EMC_CTRL_L BSP_BIT32(2)
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/** @} */
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/**
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* @name EMC Dynamic Memory Control Register (EMCDynamicControl)
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*
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* @{
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*/
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#define EMC_DYN_CTRL_CE BSP_BIT32(0)
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#define EMC_DYN_CTRL_CS BSP_BIT32(1)
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#define EMC_DYN_CTRL_SR BSP_BIT32(2)
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#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
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#define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
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#define EMC_DYN_CTRL_MCC BSP_BIT32(5)
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#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
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#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
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#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
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#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
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#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
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#define EMC_DYN_CTRL_DP BSP_BIT32(13)
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/** @} */
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/**
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* @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
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*
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* @{
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*/
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#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
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#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
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#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
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#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
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/** @} */
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/**
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* @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN)
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*
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* @{
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*/
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#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4)
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#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2)
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#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
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#define EMC_DYN_CFG_B BSP_BIT32(19)
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#define EMC_DYN_CFG_P BSP_BIT32(20)
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/** @} */
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/**
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* @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN)
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*
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* @{
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*/
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#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3)
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#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10)
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/** @} */
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#define EMC_DYN_CHIP_COUNT 4
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#define EMC_STATIC_CHIP_COUNT 4
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typedef struct {
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uint32_t config;
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uint32_t rascas;
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uint32_t reserved_0 [6];
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} lpc_emc_dynamic;
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typedef struct {
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uint32_t config;
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uint32_t waitwen;
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uint32_t waitoen;
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uint32_t waitrd;
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uint32_t waitpage;
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uint32_t waitwr;
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uint32_t waitturn;
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uint32_t reserved_0 [1];
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} lpc_emc_static;
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typedef struct {
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uint32_t control;
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uint32_t status;
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uint32_t config;
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uint32_t reserved_0 [5];
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uint32_t dynamiccontrol;
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uint32_t dynamicrefresh;
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uint32_t dynamicreadconfig;
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uint32_t reserved_1;
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uint32_t dynamictrp;
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uint32_t dynamictras;
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uint32_t dynamictsrex;
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uint32_t dynamictapr;
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uint32_t dynamictdal;
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uint32_t dynamictwr;
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uint32_t dynamictrc;
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uint32_t dynamictrfc;
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uint32_t dynamictxsr;
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uint32_t dynamictrrd;
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uint32_t dynamictmrd;
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uint32_t dynamictcdlr;
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uint32_t reserved_3 [8];
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uint32_t staticextendedwait;
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uint32_t reserved_4 [31];
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lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
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uint32_t reserved_5 [32];
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lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
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} lpc_emc;
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */
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