forked from Imagelibrary/rtems
128 lines
4.5 KiB
C
128 lines
4.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* This routine does the bulk of the system initialization.
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*/
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/*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* MVME147 port for TNI - Telecom Bretagne
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* by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
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* May 1996
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*/
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#include <bsp.h>
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#include <bsp/bootcard.h>
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void bsp_start( void )
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{
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rtems_isr_entry *monitors_vector_table;
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int index;
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uint8_t node_number;
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monitors_vector_table = (rtems_isr_entry *)0; /* 147Bug Vectors are at 0 */
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m68k_set_vbr( monitors_vector_table );
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for ( index=2 ; index<=255 ; index++ )
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M68Kvec[ index ] = monitors_vector_table[ 32 ];
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M68Kvec[ 2 ] = monitors_vector_table[ 2 ]; /* bus error vector */
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M68Kvec[ 4 ] = monitors_vector_table[ 4 ]; /* breakpoints vector */
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M68Kvec[ 9 ] = monitors_vector_table[ 9 ]; /* trace vector */
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M68Kvec[ 47 ] = monitors_vector_table[ 47 ]; /* system call vector */
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m68k_set_vbr( &M68Kvec );
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pcc->int_base_vector = PCC_BASE_VECTOR & 0xF0;
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/* Set the PCC int vectors base */
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/* VME shared memory configuration */
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/* Only the first node shares its top 128k DRAM */
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vme_lcsr->utility_interrupt_vector = VME_BASE_VECTOR & 0xF8;
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/* Set VMEchip base interrupt vector */
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vme_lcsr->utility_interrupt_mask |= 0x02;
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/* Enable SIGLP interruption (see shm support) */
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pcc->general_purpose_control &= 0x10;
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/* Enable VME master interruptions */
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if (vme_lcsr->system_controller & 0x01) {
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/* the board is system controller */
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vme_lcsr->system_controller = 0x08;
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/* Make VME access round-robin */
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}
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#if defined(RTEMS_MULTIPROCESSING)
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node_number = (uint8_t)
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(rtems_configuration_get_user_multiprocessing_table()->node - 1) & 0xF;
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#else
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node_number = 1;
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#endif
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/* Get and store node ID, first node_number = 0 */
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vme_gcsr->board_identification = node_number;
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vme_lcsr->gcsr_base_address = node_number;
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/* Setup the base address of this board's gcsr */
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vme_lcsr->timer_configuration = 0x6a;
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/* Enable VME time outs, maximum periods */
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if (node_number == 0) {
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pcc->slave_base_address = 0x01;
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/* Set local DRAM base address on the VME bus to the DRAM size */
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vme_lcsr->vme_bus_requester = 0x80;
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while (! (vme_lcsr->vme_bus_requester & 0x40));
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/* Get VMEbus mastership */
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vme_lcsr->slave_address_modifier = 0xfb;
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/* Share everything */
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vme_lcsr->slave_configuration = 0x80;
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/* Share local DRAM */
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vme_lcsr->vme_bus_requester = 0x0;
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/* release bus */
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} else {
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pcc->slave_base_address = 0;
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/* Set local DRAM base address on the VME bus to 0 */
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vme_lcsr->vme_bus_requester = 0x80;
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while (! (vme_lcsr->vme_bus_requester & 0x40));
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/* Get VMEbus mastership */
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vme_lcsr->slave_address_modifier = 0x08;
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/* Share only the short adress range */
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vme_lcsr->slave_configuration = 0;
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/* Don't share local DRAM */
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vme_lcsr->vme_bus_requester = 0x0;
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/* release bus */
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}
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vme_lcsr->master_address_modifier = 0;
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/* Automatically set the address modifier */
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vme_lcsr->master_configuration = 1;
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/* Disable D32 transfers : they don't work on my VMEbus rack */
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rtems_cache_enable_instruction();
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rtems_cache_enable_data();
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}
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