forked from Imagelibrary/rtems
105 lines
2.7 KiB
Plaintext
105 lines
2.7 KiB
Plaintext
#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 -v -d
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target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0
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#monitor set remote-debug 1
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#monitor set debug 1
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monitor bdm-reset
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#
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# Show the exception stack frame.
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#
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define show-exception-sframe
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set $frsr = *(unsigned short *)((unsigned long)$sp + 2)
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set $frpc = *(unsigned long *)((unsigned long)$sp + 4)
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set $frfvo = *(unsigned short *)((unsigned long)$sp + 0)
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set $frcode = $frfvo >> 12
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set $frvect = ($frfvo & 0xFFF) >> 2
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set $frstatus = ((($frfvo >> 10) & 3) << 2) | ($frfvo & 3)
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printf "EXCEPTION -- SR:0x%X PC:0x%X FRAME:0x%x VECTOR:%d STATUS:%d\n", $frsr, $frpc, $frcode, $frvect, $frstatus
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if $frstatus == 4
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printf " Fault Type: Error on instruction fetch"
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end
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if $frstatus == 8
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printf " Fault Type: Error on operand write"
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end
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if $frstatus == 12
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printf " Fault Type: Error on operand read"
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end
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if $frstatus == 9
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printf " Fault Type: Attempted write to write-protected space"
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end
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end
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# I have to do this as there seems to be a problem with me setting up the
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# chip selects. As far as I can tell, gdb is probing whats at the program
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# counter. It issues a 2 byte read (smallest instruction) followed by a
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# 4 byte read (depending on the result of the 2 byte read). gdb issues these
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# reads after each and every write that the .gdbinit script issues. This means
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# that as I'm initializing the chip selects the gdb reads can happen in an
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# invalid memory address and this causes a target bus error. For now I'm just
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# setting pc to 0, which seems to stop gdb from probing around to read
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# assembler. This lets me setup chip selects without error.
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set $pc = 0x00000000
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# Turn on RAMBAR1 at address 80000000
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monitor bdm-ctl-set 0x0C05 0x80000221
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# Set VBR to the beginning of what will be SDRAM
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# VBR is an absolute CPU register
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monitor bdm-ctl-set 0x0801 0x40000000
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# Disable watchdog timer
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set *((short*) 0xFC098000) = 0x0000
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#Init CS0
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set *((long*) 0xFC008000) = 0x00000000
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set *((long*) 0xFC008008) = 0x00001FA0
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set *((long*) 0xFC008004) = 0x001F0001
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# SDRAM Initialization
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monitor delay-ms 100
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# SDCS0
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set *((long*) 0xFC0B8110) = 0x40000018
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# SDCFG1
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set *((long*) 0xFC0B8008) = 0x53722730
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# SDCFG2
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set *((long*) 0xFC0B800C) = 0x56670000
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# Issue PALL
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# SDCR
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set *((long*) 0xFC0B8004) = 0xE1092002
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# Issue LEMR
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# SDMR
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set *((long*) 0xFC0B8000) = 0x40010000
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# Write mode register
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# SDMR
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set *((long*) 0xFC0B8000) = 0x058D0000
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# Wait a bit
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monitor delay-ms 600
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# Issue PALL
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# SDCR
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set *((long*) 0xFC0B8004) = 0xE1092002
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# Perform two refresh cycles
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# SDCR
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set *((long*) 0xFC0B8004) = 0xE1092004
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# SDCR
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set *((long*) 0xFC0B8004) = 0xE1092004
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# SDMR
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set *((long*) 0xFC0B8000) = 0x018D0000
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# SDCR
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set *((long*) 0xFC0B8004) = 0x71092C00
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# Wait a bit
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monitor delay-ms 100
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load
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