forked from Imagelibrary/rtems
127 lines
3.8 KiB
C
127 lines
3.8 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2007, 2014 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#define CPU_DATA_CACHE_ALIGNMENT 16
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT 16
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/*
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* There is no complete cache lock (only 2 ways of 4 can be locked)
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*/
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static inline void _CPU_cache_freeze_data(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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/* Do nothing */
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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bsp_cacr_clear_flags( MCF548X_CACR_IDCM);
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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bsp_cacr_set_flags( MCF548X_CACR_IDCM);
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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bsp_cacr_set_self_clear_flags( MCF548X_CACR_ICINVA);
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}
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static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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uint32_t a = (uint32_t) addr & ~0x3;
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x0));
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x1));
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x2));
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__asm__ volatile ("cpushl %%ic,(%0)" :: "a" (a | 0x3));
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}
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static inline void _CPU_cache_enable_data(void)
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{
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bsp_cacr_clear_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
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}
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static inline void _CPU_cache_disable_data(void)
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{
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bsp_cacr_set_flags( MCF548X_CACR_DDCM( DCACHE_OFF_IMPRECISE));
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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bsp_cacr_set_self_clear_flags( MCF548X_CACR_DCINVA);
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}
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static inline void _CPU_cache_invalidate_1_data_line( const void *addr)
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{
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uint32_t a = (uint32_t) addr & ~0x3;
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
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}
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static inline void _CPU_cache_flush_1_data_line( const void *addr)
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{
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uint32_t a = (uint32_t) addr & ~0x3;
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x0));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x1));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x2));
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__asm__ volatile ("cpushl %%dc,(%0)" :: "a" (a | 0x3));
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}
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static inline void _CPU_cache_flush_entire_data( void)
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{
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uint32_t line = 0;
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for (line = 0; line < 512; ++line) {
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_CPU_cache_flush_1_data_line( (const void *) (line * 16));
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}
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}
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#include "../../../shared/cache/cacheimpl.h"
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