forked from Imagelibrary/rtems
8d7393ad5f
* BSP_TIMES, ChangeLog, Makefile.am, arm.texi, bsp.t, callconv.t, cpumodel.t, cputable.t, fatalerr.t, intr_NOTIMES.t, memmodel.t, preface.texi, stamp-vti, timeBSP.t, timing.texi, version.texi, wksheets.texi: New files as ARM supplement initial version added.
114 lines
4.7 KiB
Perl
114 lines
4.7 KiB
Perl
@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@include common/timemac.texi
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@tex
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\global\advance \smallskipamount by -4pt
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@end tex
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@chapter MYBSP Timing Data
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@section Introduction
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The timing data for the ARM version of RTEMS is
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provided along with the target dependent aspects concerning the
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gathering of the timing data. The hardware platform used to
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gather the times is described to give the reader a better
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understanding of each directive time provided. Also, provided
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is a description of the interrupt latency and the context switch
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times as they pertain to the ARM version of RTEMS.
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@section Hardware Platform
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All times reported except for the maximum period
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interrupts are disabled by RTEMS were measured using a Motorola
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MYBSP CPU board. The MYBSP is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
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Mhz board with SDRAM and no numeric coprocessor. A
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countdown timer on this board was used to measure
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elapsed time with a 20 nanosecond resolution. All
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sources of hardware interrupts were disabled, although the
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interrupt level of the ARM microprocessor allows all interrupts.
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The maximum period interrupts are disabled was
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measured by summing the number of CPU cycles required by each
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assembly language instruction executed while interrupts were
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disabled. The worst case times of the ARM9DTMI microprocessor
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were used for each instruction. Zero wait state memory was
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assumed. The total CPU cycles executed with interrupts
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disabled, including the instructions to disable and enable
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interrupts, was divided by TBD to simulate a TBD Mhz processor. It
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should be noted that the worst case instruction times
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assume that the internal cache is disabled and that no
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instructions overlap.
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@section Interrupt Latency
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The maximum period with interrupts disabled within
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RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD
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microseconds including the instructions
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which disable and re-enable interrupts. The time required for
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the processor to vector an interrupt and for the RTEMS entry
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overhead before invoking the user's interrupt handler are a
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total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
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microseconds. These combine to yield a worst case
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interrupt latency of less than
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RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
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microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
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Mhz. [NOTE: The maximum period with interrupts
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disabled was last determined for Release
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RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
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It should be noted again that the maximum period with
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interrupts disabled within RTEMS is hand-timed and based upon
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worst case (i.e. CPU cache disabled and no instruction overlap)
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times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor.
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The interrupt vector and entry
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overhead time was generated on an MYBSP benchmark platform
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using the Multiprocessing Communications registers to generate
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as the interrupt source.
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@section Context Switch
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The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
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microseconds on the MYBSP benchmark platform when no floating
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point context is saved or restored. Additional execution time
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is required when a TASK_SWITCH user extension is configured.
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The use of the TASK_SWITCH extension is application dependent.
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Thus, its execution time is not considered part of the raw
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context switch time.
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The ARM processor benchmarked does not have a floating point
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unit and consequently no FPU results are reported.
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@c Since RTEMS was designed specifically for embedded
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@c missile applications which are floating point intensive, the
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@c executive is optimized to avoid unnecessarily saving and
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@c restoring the state of the numeric coprocessor. The state of
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@c the numeric coprocessor is only saved when an FLOATING_POINT
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@c task is dispatched and that task was not the last task to
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@c utilize the coprocessor. In a system with only one
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@c FLOATING_POINT task, the state of the numeric coprocessor will
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@c never be saved or restored. When the first FLOATING_POINT task
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@c is dispatched, RTEMS does not need to save the current state of
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@c the numeric coprocessor.
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@c The exact amount of time required to save and restore
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@c floating point context is dependent on whether an XXX or
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@c XXX is being used as well as the state of the numeric
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@c coprocessor. These numeric coprocessors define three operating
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@c states: initialized, idle, and busy. RTEMS places the
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@c coprocessor in the initialized state when a task is started or
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@c restarted. Once the task has utilized the coprocessor, it is in
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@c the idle state when floating point instructions are not
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@c executing and the busy state when floating point instructions
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@c are executing. The state of the coprocessor is task specific.
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The following table summarizes the context switch
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times for the MYBSP benchmark platform:
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