forked from Imagelibrary/rtems
123 lines
4.1 KiB
Perl
123 lines
4.1 KiB
Perl
@c
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@c Interrupt Stack Frame Picture
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@c
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c
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@c $Id$
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@c
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@chapter Interrupt Processing
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@section Introduction
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Different types of processors respond to the
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occurrence of an interrupt in its own unique fashion. In
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addition, each processor type provides a control mechanism to
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allow for the proper handling of an interrupt. The processor
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dependent response to the interrupt modifies the current
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execution state and results in a change in the execution stream.
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Most processors require that an interrupt handler utilize some
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special control mechanisms to return to the normal processing
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stream. Although RTEMS hides many of the processor dependent
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details of interrupt processing, it is important to understand
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how the RTEMS interrupt manager is mapped onto the processor's
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unique architecture. Discussed in this chapter are the ARM's
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interrupt response and control mechanisms as they pertain to
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RTEMS.
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The ARM has 7 exception types:
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@itemize @bullet
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@item Reset
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@item Undefined instruction
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@item Software interrupt (SWI)
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@item Prefetch Abort
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@item Data Abort
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@item Interrupt (IRQ)
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@item Fast Interrupt (FIQ)
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@end itemize
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Of these types, only IRQ and FIQ are handled through RTEMS's interrupt
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vectoring.
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@section Vectoring of an Interrupt Handler
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Unlike many other architectures, the ARM has seperate stacks for each
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interrupt. When the CPU receives an interrupt, it:
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@itemize @bullet
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@item switches to the exception mode corresponding to the interrupt,
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@item saves the Current Processor Status Register (CPSR) to the
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exception mode's Saved Processor Status Register (SPSR),
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@item masks off the IRQ and if the interrupt source was FIQ, the FIQ
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is masked off as well,
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@item saves the Program Counter (PC) to the exception mode's Link
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Register (LR - same as R14),
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@item and sets the PC to the exception's vector address.
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@end itemize
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The vectors for both IRQ and FIQ point to the _ISR_Handler function.
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_ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before
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calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so
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that it is safe to call C functions. Even ExecuteITHandler() can be written
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in C.
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@section Interrupt Levels
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The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ
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has a higher priority than IRQ, and has its own version of register R8 - R14,
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however RTEMS does not take advantage of them. Both interrupts are enabled
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through the CPSR.
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The RTEMS interrupt level mapping scheme for the AEM is not a numeric level
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as on most RTEMS ports. It is a bit mapping that corresponds the enable
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bits's postions in the CPSR:
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@table @b
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@item FIQ
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Setting bit 6 (0 is least significant bit) disables the FIQ.
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@item IRQ
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Setting bit 7 (0 is least significant bit) disables the IRQ.
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@end table
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@section Disabling of Interrupts by RTEMS
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During the execution of directive calls, critical
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sections of code may be executed. When these sections are
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encountered, RTEMS disables interrupts to level seven (7) before
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the execution of this section and restores them to the previous
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level upon completion of the section. RTEMS has been optimized
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to insure that interrupts are disabled for less than
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RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a
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RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with
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zero wait states. These numbers will vary based the
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number of wait states and processor speed present on the target board.
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[NOTE: The maximum period with interrupts disabled is hand calculated. This
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calculation was last performed for Release
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RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
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Non-maskable interrupts (NMI) cannot be disabled, and
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ISRs which execute at this level MUST NEVER issue RTEMS system
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calls. If a directive is invoked, unpredictable results may
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occur due to the inability of RTEMS to protect its critical
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sections. However, ISRs that make no system calls may safely
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execute as non-maskable interrupts.
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@section Interrupt Stack
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RTEMS expects the interrupt stacks to be set up in bsp_start(). The memory
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for the stacks is reserved in the linker script.
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