forked from Imagelibrary/rtems
8ef38186fa
<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart <Darlene.Stewart@nrc.ca> to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860
333 lines
9.1 KiB
C
333 lines
9.1 KiB
C
/*
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* cpu.h
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*
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* This file contains some powerpc MSR and registers access definitions.
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*
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* It is a stripped down version of linux ppc processor.h file...
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*
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* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
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* Canon Centre Recherche France.
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#ifndef __PPC_CPU_H
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#define __PPC_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Bit encodings for Machine State Register (MSR) */
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#define MSR_POW (1<<18) /* Enable Power Management */
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#define MSR_TGPR (1<<17) /* TLB Update registers in use */
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#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
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#define MSR_EE (1<<15) /* External Interrupt enable */
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#define MSR_PR (1<<14) /* Supervisor/User privilege */
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#define MSR_FP (1<<13) /* Floating Point enable */
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#define MSR_ME (1<<12) /* Machine Check enable */
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#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
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#define MSR_SE (1<<10) /* Single Step */
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#define MSR_BE (1<<9) /* Branch Trace */
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR (1<<5) /* Instruction MMU enable */
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#define MSR_DR (1<<4) /* Data MMU enable */
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#define MSR_RI (1<<1) /* Recoverable Exception */
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#define MSR_LE (1<<0) /* Little-Endian enable */
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#define MSR_ MSR_ME|MSR_RI
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#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
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#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
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/* Bit encodings for Hardware Implementation Register (HID0)
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on PowerPC 603, 604, etc. processors (not 601). */
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#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
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#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
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#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
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#define HID0_SBCLK (1<<27)
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#define HID0_EICE (1<<26)
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#define HID0_ECLK (1<<25)
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#define HID0_PAR (1<<24)
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#define HID0_DOZE (1<<23)
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#define HID0_NAP (1<<22)
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#define HID0_SLEEP (1<<21)
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#define HID0_DPM (1<<20)
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#define HID0_ICE (1<<15) /* Instruction Cache Enable */
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#define HID0_DCE (1<<14) /* Data Cache Enable */
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#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
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#define HID0_DLOCK (1<<12) /* Data Cache Lock */
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#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
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#define HID0_DCI (1<<10) /* Data Cache Invalidate */
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#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */
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#define HID0_BHTE (1<<2) /* Branch History Table Enable */
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#define HID0_BTCD (1<<1) /* Branch target cache disable */
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/* fpscr settings */
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#define FPSCR_FX (1<<31)
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#define FPSCR_FEX (1<<30)
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#define _MACH_prep 1
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#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */
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#define _MACH_chrp 4 /* chrp machine */
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#define _MACH_mbx 8 /* Motorola MBX board */
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#define _MACH_apus 16 /* amiga with phase5 powerup */
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#define _MACH_fads 32 /* Motorola FADS board */
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/* see residual.h for these */
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#define _PREP_Motorola 0x01 /* motorola prep */
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#define _PREP_Firm 0x02 /* firmworks prep */
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#define _PREP_IBM 0x00 /* ibm prep */
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#define _PREP_Bull 0x03 /* bull prep */
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/* these are arbitrary */
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#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
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#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
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#define _GLOBAL(n)\
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.globl n;\
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n:
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#define TBRU 269 /* Time base Upper/Lower (Reading) */
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#define TBRL 268
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#define TBWU 284 /* Time base Upper/Lower (Writing) */
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#define TBWL 285
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#define XER 1
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#define LR 8
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#define CTR 9
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#define HID0 1008 /* Hardware Implementation */
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#define PVR 287 /* Processor Version */
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#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */
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#define IBAT0L 529
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#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */
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#define IBAT1L 531
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#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */
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#define IBAT2L 533
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#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */
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#define IBAT3L 535
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#define DBAT0U 536 /* Data BAT #0 Upper/Lower */
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#define DBAT0L 537
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#define DBAT1U 538 /* Data BAT #1 Upper/Lower */
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#define DBAT1L 539
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#define DBAT2U 540 /* Data BAT #2 Upper/Lower */
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#define DBAT2L 541
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#define DBAT3U 542 /* Data BAT #3 Upper/Lower */
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#define DBAT3L 543
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#define DMISS 976 /* TLB Lookup/Refresh registers */
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#define DCMP 977
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#define HASH1 978
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#define HASH2 979
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#define IMISS 980
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#define ICMP 981
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#define RPA 982
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#define SDR1 25 /* MMU hash base register */
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#define DAR 19 /* Data Address Register */
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#define SPR0 272 /* Supervisor Private Registers */
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#define SPRG0 272
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#define SPR1 273
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#define SPRG1 273
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#define SPR2 274
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#define SPRG2 274
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#define SPR3 275
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#define SPRG3 275
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#define DSISR 18
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#define SRR0 26 /* Saved Registers (exception) */
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#define SRR1 27
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#define IABR 1010 /* Instruction Address Breakpoint */
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#define DEC 22 /* Decrementer */
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#define EAR 282 /* External Address Register */
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#define L2CR 1017 /* PPC 750 L2 control register */
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#define THRM1 1020
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#define THRM2 1021
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#define THRM3 1022
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#define THRM1_TIN 0x1
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#define THRM1_TIV 0x2
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#define THRM1_THRES (0x7f<<2)
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#define THRM1_TID (1<<29)
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#define THRM1_TIE (1<<30)
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#define THRM1_V (1<<31)
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#define THRM3_E (1<<31)
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/* Segment Registers */
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#define SR0 0
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#define SR1 1
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#define SR2 2
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#define SR3 3
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#define SR4 4
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#define SR5 5
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#define SR6 6
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#define SR7 7
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#define SR8 8
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#define SR9 9
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#define SR10 10
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#define SR11 11
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#define SR12 12
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#define SR13 13
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#define SR14 14
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#define SR15 15
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#ifndef ASM
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typedef enum {
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PPC_601 = 0x1,
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PPC_603 = 0x3,
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PPC_604 = 0x4,
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PPC_603e = 0x6,
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PPC_603ev = 0x7,
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PPC_750 = 0x8,
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PPC_604e = 0x9,
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PPC_604r = 0xA,
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PPC_620 = 0x16,
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PPC_860 = 0x50,
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PPC_821 = PPC_860,
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PPC_UNKNOWN = 0xff
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} ppc_cpu_id_t;
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typedef unsigned short ppc_cpu_revision_t;
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extern ppc_cpu_id_t get_ppc_cpu_type();
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extern ppc_cpu_id_t current_ppc_cpu;
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extern ppc_cpu_revision_t get_ppc_cpu_revision();
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extern ppc_cpu_revision_t current_ppc_revision;
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/*
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* Routines to access the time base register
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*/
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static inline unsigned long long PPC_Get_timebase_register( void )
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{
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unsigned long tbr_low;
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unsigned long tbr_high;
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unsigned long tbr_high_old;
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unsigned long long tbr;
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do {
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asm volatile( "mftbu %0" : "=r" (tbr_high_old));
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asm volatile( "mftb %0" : "=r" (tbr_low));
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asm volatile( "mftbu %0" : "=r" (tbr_high));
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} while ( tbr_high_old != tbr_high );
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tbr = tbr_high;
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tbr <<= 32;
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tbr |= tbr_low;
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return tbr;
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}
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static inline void PPC_Set_timebase_register (unsigned long long tbr)
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{
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unsigned long tbr_low;
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unsigned long tbr_high;
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tbr_low = (tbr & 0xffffffff) ;
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tbr_high = (tbr >> 32) & 0xffffffff;
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asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
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asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
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}
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#endif
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#define _CPU_MSR_GET( _msr_value ) \
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do { \
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_msr_value = 0; \
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asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
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} while (0)
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#define _CPU_MSR_SET( _msr_value ) \
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{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
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#define _CPU_ISR_Disable( _isr_cookie ) \
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{ register unsigned int _disable_mask = MSR_EE; \
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_isr_cookie = 0; \
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asm volatile ( \
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"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
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"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
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"0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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/*
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* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
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* This indicates the end of an RTEMS critical section. The parameter
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* _isr_cookie is not modified.
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*/
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#define _CPU_ISR_Enable( _isr_cookie ) \
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{ \
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asm volatile ( "mtmsr %0" : \
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"=r" ((_isr_cookie)) : \
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"0" ((_isr_cookie))); \
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}
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/*
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* This temporarily restores the interrupt to _isr_cookie before immediately
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* disabling them again. This is used to divide long RTEMS critical
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* sections into two or more parts. The parameter _isr_cookie is not
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* modified.
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*
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* NOTE: The version being used is not very optimized but it does
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* not trip a problem in gcc where the disable mask does not
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* get loaded. Check this for future (post 10/97 gcc versions.
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*/
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#define _CPU_ISR_Flash( _isr_cookie ) \
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{ register unsigned int _disable_mask = MSR_EE; \
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asm volatile ( \
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"mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
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"=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
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"0" ((_isr_cookie)), "1" ((_disable_mask)) \
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); \
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}
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/* end of ISR handler macros */
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/*
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* Simple spin delay in microsecond units for device drivers.
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* This is very dependent on the clock speed of the target.
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*/
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#define CPU_Get_timebase_low( _value ) \
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asm volatile( "mftb %0" : "=r" (_value) )
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#define delay( _microseconds ) \
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do { \
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unsigned32 start, ticks, now; \
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CPU_Get_timebase_low( start ) ; \
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ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
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do \
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CPU_Get_timebase_low( now ) ; \
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while (now - start < ticks); \
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} while (0)
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#define delay_in_bus_cycles( _cycles ) \
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do { \
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unsigned32 start, now; \
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CPU_Get_timebase_low( start ); \
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do \
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CPU_Get_timebase_low( now ); \
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while (now - start < (_cycles)); \
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} while (0)
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#define PPC_Set_decrementer( _clicks ) \
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do { \
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asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
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} while (0)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PPC_CPU_H */
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