forked from Imagelibrary/rtems
e831de8559
* bootloader/bootldr.h, bootloader/em86.c, bootloader/em86real.S, bootloader/exception.S, bootloader/head.S, bootloader/lib.c, bootloader/misc.c, bootloader/mm.c, bootloader/pci.c, clock/p_clock.c, console/console.c, console/consoleIo.h, console/inch.c, console/keyboard.h, console/polled_io.c, include/bsp.h, irq/i8259.c, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, motorola/motorola.c, motorola/motorola.h, openpic/openpic.c, openpic/openpic.h, pci/pci.c, residual/residual.c, start/start.S, startup/bspstart.c, vectors/vectors.h, vectors/vectors_init.c: URL for license changed.
449 lines
8.9 KiB
ArmAsm
449 lines
8.9 KiB
ArmAsm
/*
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* head.S -- Bootloader Entry point
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*
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* Copyright (C) 1998, 1999 Gabriel Paubert, paubert@iram.es
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*
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* Modified to compile in RTEMS development environment
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* by Eric Valette
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*
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* Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <asm.h>
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#include <rtems/score/cpu.h>
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#include "bootldr.h"
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#define TEST_PPCBUG_CALLS
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#undef TEST_PPCBUG_CALLS
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#define FRAME_SIZE 32
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#define LOCK_CACHES (HID0_DLOCK | HID0_ILOCK)
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#define INVL_CACHES (HID0_DCI | HID0_ICFI)
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#define ENBL_CACHES (HID0_DCE | HID0_ICE)
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#define USE_PPCBUG
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#undef USE_PPCBUG
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#define PRINT_CHAR(c) \
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addi r20,r3,0 ; \
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li r3,c ; \
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li r10,0x20 ; \
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sc ; \
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addi r3,r20,0 ; \
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li r10,0x26 ; \
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sc
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#define MONITOR_ENTER \
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mfmsr r10 ; \
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ori r10,r10,MSR_IP ; \
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mtmsr r10 ; \
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li r10,0x63 ; \
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sc
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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GOT_ENTRY(.bss)
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GOT_ENTRY(codemove)
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GOT_ENTRY(0)
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GOT_ENTRY(__bd)
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GOT_ENTRY(moved)
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GOT_ENTRY(_binary_rtems_gz_start)
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GOT_ENTRY(_binary_initrd_gz_start)
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GOT_ENTRY(_binary_initrd_gz_end)
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#ifdef TEST_PPCBUG_CALLS
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GOT_ENTRY(banner_start)
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GOT_ENTRY(banner_end)
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#endif
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END_GOT
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.globl start
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.type start,@function
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/* Point the stack into the PreP partition header in the x86 reserved
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* code area, so that simple C routines can be called.
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*/
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start:
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#ifdef USE_PPCBUG
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MONITOR_ENTER
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#endif
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bl 1f
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1: mflr r1
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li r0,0
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stwu r0,start-1b-0x400+0x1b0-FRAME_SIZE(r1)
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stmw r26,FRAME_SIZE-24(r1)
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GET_GOT
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mfmsr r28 /* Turn off interrupts */
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ori r0,r28,MSR_EE
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xori r0,r0,MSR_EE
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mtmsr r0
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/* Enable the caches, from now on cr2.eq set means processor is 601 */
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mfpvr r0
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mfspr r29,HID0
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srwi r0,r0,16
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cmplwi cr2,r0,1
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beq 2,2f
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/*
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* commented out, 11/7/2002, gregm. This instruction sequence seems to
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* be pathological on the 603e.
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*
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#ifndef USE_PPCBUG
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ori r0,r29,ENBL_CACHES|INVL_CACHES|LOCK_CACHES
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xori r0,r0,INVL_CACHES|LOCK_CACHES
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sync
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isync
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mtspr HID0,r0
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#endif
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*/
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2: bl reloc
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/* save all the parameters and the orginal msr/hid0/r31 */
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lwz bd,GOT(__bd)
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stw r3,0(bd)
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stw r4,4(bd)
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stw r5,8(bd)
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stw r6,12(bd)
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lis r3,__size@sectoff@ha
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stw r7,16(bd)
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stw r8,20(bd)
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addi r3,r3,__size@sectoff@l
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stw r9,24(bd)
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stw r10,28(bd)
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stw r28,o_msr(bd)
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stw r29,o_hid0(bd)
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stw r31,o_r31(bd)
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/* Call the routine to fill boot_data structure from residual data.
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* And to find where the code has to be moved.
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*/
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bl early_setup
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/* Now we need to relocate ourselves, where we are told to. First put a
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* copy of the codemove routine to some place in memory.
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* (which may be where the 0x41 partition was loaded, so size is critical).
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*/
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lwz r4,GOT(codemove)
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li r5,_size_codemove
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lwz r3,mover(bd)
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lwz r6,cache_lsize(bd)
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bl codemove
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mtctr r3 # Where the temporary codemove is.
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lwz r3,image(bd)
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lis r5,_edata@sectoff@ha
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lwz r4,GOT(0) # Our own address
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addi r5,r5,_edata@sectoff@l
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lwz r6,cache_lsize(bd)
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lwz r8,GOT(moved)
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sub r7,r3,r4 # Difference to adjust pointers.
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add r8,r8,r7
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add r30,r30,r7
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add bd,bd,r7
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/* Call the copy routine but return to the new area. */
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mtlr r8 # for the return address
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bctr # returns to the moved instruction
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/* Establish the new top stack frame. */
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moved: lwz r1,stack(bd)
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li r0,0
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stwu r0,-16(r1)
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/* relocate again */
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bl reloc
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/* Clear all of BSS */
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lwz r10,GOT(.bss)
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li r0,__bss_words@sectoff@l
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subi r10,r10,4
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cmpwi r0,0
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mtctr r0
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li r0,0
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beq 4f
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3: stwu r0,4(r10)
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bdnz 3b
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/* Final memory initialization. First switch to unmapped mode
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* in case the FW had set the MMU on, and flush the TLB to avoid
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* stale entries from interfering. No I/O access is allowed
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* during this time!
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*/
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4:
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#ifdef USE_PPCBUG
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PRINT_CHAR('M')
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#endif
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bl MMUoff
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#ifdef USE_PPCBUG
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PRINT_CHAR('B')
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#endif
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bl flush_tlb
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/* Some firmware versions leave stale values in the BATs, it's time
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* to invalidate them to avoid interferences with our own mappings.
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* But the 601 valid bit is in the BATL (IBAT only) and others are in
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* the [ID]BATU. Bloat, bloat.. fortunately thrown away later.
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*/
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#ifdef USE_PPCBUG
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PRINT_CHAR('T')
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#endif
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li r3,0
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beq cr2,5f
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mtdbatu 0,r3
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mtdbatu 1,r3
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mtdbatu 2,r3
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mtdbatu 3,r3
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5: mtibatu 0,r3
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mtibatl 0,r3
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mtibatu 1,r3
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mtibatl 1,r3
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mtibatu 2,r3
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mtibatl 2,r3
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mtibatu 3,r3
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mtibatl 3,r3
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lis r3,__size@sectoff@ha
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addi r3,r3,__size@sectoff@l
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sync # We are going to touch SDR1 !
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#ifdef USE_PPCBUG
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PRINT_CHAR('i')
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#endif
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bl mm_init
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#ifdef USE_PPCBUG
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PRINT_CHAR('M')
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#endif
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bl MMUon
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/* Now we are mapped and can perform I/O if we want */
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#ifdef TEST_PPCBUG_CALLS
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/* Experience seems to show that PPCBug can only be called with the
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* data cache disabled and with MMU disabled. Bummer.
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*/
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li r10,0x22 # .OUTLN
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lwz r3,GOT(banner_start)
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lwz r4,GOT(banner_end)
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sc
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#endif
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#ifdef USE_PPCBUG
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PRINT_CHAR('H')
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#endif
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bl setup_hw
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lwz r4,GOT(_binary_rtems_gz_start)
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lis r5,_rtems_gz_size@sectoff@ha
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lwz r6,GOT(_binary_initrd_gz_start)
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lis r3,_rtems_size@sectoff@ha
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lwz r7,GOT(_binary_initrd_gz_end)
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addi r5,r5,_rtems_gz_size@sectoff@l
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addi r3,r3,_rtems_size@sectoff@l
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sub r7,r7,r6
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bl decompress_kernel
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/* Back here we are unmapped and we start the kernel, passing up to eight
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* parameters just in case, only r3 to r7 used for now. Flush the tlb so
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* that the loaded image starts in a clean state.
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*/
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bl flush_tlb
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lwz r3,0(bd)
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lwz r4,4(bd)
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lwz r5,8(bd)
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lwz r6,12(bd)
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lwz r7,16(bd)
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lwz r8,20(bd)
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lwz r9,24(bd)
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lwz r10,28(bd)
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lwz r30,0(0)
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mtctr r30
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/*
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* Linux code again
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*
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lis r30,0xdeadc0de@ha
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addi r30,r30,0xdeadc0de@l
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stw r30,0(0)
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li r30,0
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*/
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dcbst 0,r30 /* Make sure it's in memory ! */
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/* We just flash invalidate and disable the dcache, unless it's a 601,
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* critical areas have been flushed and we don't care about the stack
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* and other scratch areas.
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*/
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beq cr2,1f
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mfspr r0,HID0
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ori r0,r0,HID0_DCI|HID0_DCE
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sync
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mtspr HID0,r0
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xori r0,r0,HID0_DCI|HID0_DCE
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mtspr HID0,r0
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/* Provisional return to FW, works for PPCBug */
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#if 0
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MONITOR_ENTER
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#else
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1: bctr
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#endif
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/* relocation function, r30 must point to got2+0x8000 */
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reloc:
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/* Adjust got2 pointers, no need to check for 0, this code already puts
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* a few entries in the table.
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*/
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li r0,__got2_entries@sectoff@l
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la r12,GOT(_GOT2_TABLE_)
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lwz r11,GOT(_GOT2_TABLE_)
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mtctr r0
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sub r11,r12,r11
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addi r12,r12,-4
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1: lwzu r0,4(r12)
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add r0,r0,r11
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stw r0,0(r12)
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bdnz 1b
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/* Now adjust the fixups and the pointers to the fixups in case we need
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* to move ourselves again.
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*/
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2: li r0,__fixup_entries@sectoff@l
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lwz r12,GOT(_FIXUP_TABLE_)
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cmpwi r0,0
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mtctr r0
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addi r12,r12,-4
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beqlr
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3: lwzu r10,4(r12)
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lwzux r0,r10,r11
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add r0,r0,r11
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stw r10,0(r12)
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stw r0,0(r10)
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bdnz 3b
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blr
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/* Set the MMU on and off: code is always mapped 1:1 and does not need MMU,
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* but it does not cost so much to map it also and it catches calls through
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* NULL function pointers.
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*/
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.globl MMUon
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.type MMUon,@function
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MMUon: blr
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nop
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/*
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mfmsr r0
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ori r0,r0,MSR_IR|MSR_DR|MSR_IP
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mflr r11
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xori r0,r0,MSR_IP
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mtsrr0 r11
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mtsrr1 r0
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rfi
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*/
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.globl MMUoff
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.type MMUoff,@function
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MMUoff: blr
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nop
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/*
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mfmsr r0
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ori r0,r0,MSR_IR|MSR_DR|MSR_IP
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mflr r11
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xori r0,r0,MSR_IR|MSR_DR
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mtsrr0 r11
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mtsrr1 r0
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rfi
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*/
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/* Due to the PPC architecture (and according to the specifications), a
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* series of tlbie which goes through a whole 256 MB segment always flushes
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* the whole TLB. This is obviously overkill and slow, but who cares ?
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* It takes about 1 ms on a 200 MHz 603e and works even if residual data
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* get the number of TLB entries wrong.
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*/
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flush_tlb:
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lis r11,0x1000
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1: addic. r11,r11,-0x1000
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tlbie r11
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bnl 1b
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/* tlbsync is not implemented on 601, so use sync which seems to be a superset
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* of tlbsync in all cases and do not bother with CPU dependant code
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*/
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sync
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blr
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.globl codemove
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codemove:
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.type codemove,@function
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/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
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cmplw cr1,r3,r4
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addi r0,r5,3
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srwi. r0,r0,2
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beq cr1,4f /* In place copy is not necessary */
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beq 7f /* Protect against 0 count */
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mtctr r0
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bge cr1,2f
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la r8,-4(r4)
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la r7,-4(r3)
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1: lwzu r0,4(r8)
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stwu r0,4(r7)
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bdnz 1b
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b 4f
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2: slwi r0,r0,2
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add r8,r4,r0
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add r7,r3,r0
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3: lwzu r0,-4(r8)
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stwu r0,-4(r7)
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bdnz 3b
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/* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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*/
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4: cmpwi r6,0
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add r5,r3,r5
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beq 7f /* Always flush prefetch queue in any case */
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subi r0,r6,1
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andc r3,r3,r0
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mr r4,r3
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5: cmplw r4,r5
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dcbst 0,r4
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add r4,r4,r6
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blt 5b
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sync /* Wait for all dcbst to complete on bus */
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mr r4,r3
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6: cmplw r4,r5
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icbi 0,r4
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add r4,r4,r6
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blt 6b
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7: sync /* Wait for all icbi to complete on bus */
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isync
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blr
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.size codemove,.-codemove
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_size_codemove=.-codemove
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.section ".data" # .rodata
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.align 2
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#ifdef TEST_PPCBUG_CALLS
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banner_start:
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.ascii "This message was printed by PPCBug with MMU enabled"
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banner_end:
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#endif
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