forked from Imagelibrary/rtems
586 lines
18 KiB
C
586 lines
18 KiB
C
/*===============================================================*\
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| Project: RTEMS generic MPC83xx BSP |
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+-----------------------------------------------------------------+
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| Copyright (c) 2007 |
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| Embedded Brains GmbH |
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| Obere Lagerstr. 30 |
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| D-82178 Puchheim |
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| Germany |
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| rtems@embedded-brains.de |
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+-----------------------------------------------------------------+
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| The license and distribution terms for this file may be |
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| found in the file LICENSE in this distribution or at |
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| |
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| http://www.rtems.org/license/LICENSE. |
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+-----------------------------------------------------------------+
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| this file integrates the IPIC irq controller |
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\*===============================================================*/
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#include <mpc83xx/mpc83xx.h>
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#include <rtems.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp/vectors.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#define MPC83XX_IPIC_VECTOR_NUMBER 92
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#define MPC83XX_IPIC_IS_VALID_VECTOR( vector) ((vector) >= 0 && (vector) < MPC83XX_IPIC_VECTOR_NUMBER)
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#define MPC83XX_IPIC_INVALID_MASK_POSITION 255
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typedef struct {
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volatile uint32_t *pend_reg;
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volatile uint32_t *mask_reg;
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const uint32_t bit_num;
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} BSP_isrc_rsc_t;
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/*
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* data structure to handle all mask registers in the IPIC
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*
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* Mask positions:
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* simsr [0] : 0 .. 31
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* simsr [1] : 32 .. 63
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* semsr : 64 .. 95
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* sermr : 96 .. 127
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*/
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typedef struct {
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uint32_t simsr_mask [2];
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uint32_t semsr_mask;
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uint32_t sermr_mask;
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} mpc83xx_ipic_mask_t;
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static const BSP_isrc_rsc_t mpc83xx_ipic_isrc_rsc [MPC83XX_IPIC_VECTOR_NUMBER] = {
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/* vector 0 */
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{&mpc83xx.ipic.sersr, &mpc83xx.ipic.sermr, 31},
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{NULL, NULL, 0},
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{NULL, NULL, 0},
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{NULL, NULL, 0},
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{NULL, NULL, 0},
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{NULL, NULL, 0},
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{NULL, NULL, 0},
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{NULL, NULL, 0},
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/* vector 8 */
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{NULL, NULL, 0}, /* reserved vector 8 */
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/* vector 9: UART1 SIxxR_H, Bit 24 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 24},
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/* vector 10: UART2 SIxxR_H, Bit 25 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 25},
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/* vector 11: SEC SIxxR_H, Bit 26 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 26},
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{NULL, NULL, 0}, /* reserved vector 12 */
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{NULL, NULL, 0}, /* reserved vector 13 */
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/* vector 14: I2C1 SIxxR_H, Bit 29 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 29},
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/* vector 15: I2C2 SIxxR_H, Bit 30 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 30},
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/* vector 16: SPI SIxxR_H, Bit 31 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 31},
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/* vector 17: IRQ1 SExxR , Bit 1 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 1},
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/* vector 18: IRQ2 SExxR , Bit 2 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 2},
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/* vector 19: IRQ3 SExxR , Bit 3 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 3},
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/* vector 20: IRQ4 SExxR , Bit 4 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 4},
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/* vector 21: IRQ5 SExxR , Bit 5 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 5},
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/* vector 22: IRQ6 SExxR , Bit 6 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 6},
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/* vector 23: IRQ7 SExxR , Bit 7 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 7},
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{NULL, NULL, 0}, /* reserved vector 24 */
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{NULL, NULL, 0}, /* reserved vector 25 */
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{NULL, NULL, 0}, /* reserved vector 26 */
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{NULL, NULL, 0}, /* reserved vector 27 */
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{NULL, NULL, 0}, /* reserved vector 28 */
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{NULL, NULL, 0}, /* reserved vector 29 */
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{NULL, NULL, 0}, /* reserved vector 30 */
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{NULL, NULL, 0}, /* reserved vector 31 */
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/* vector 32: TSEC1 Tx SIxxR_H , Bit 0 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 0},
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/* vector 33: TSEC1 Rx SIxxR_H , Bit 1 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 1},
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/* vector 34: TSEC1 Err SIxxR_H , Bit 2 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 2},
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/* vector 35: TSEC2 Tx SIxxR_H , Bit 3 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 3},
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/* vector 36: TSEC2 Rx SIxxR_H , Bit 4 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 4},
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/* vector 37: TSEC2 Err SIxxR_H , Bit 5 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 5},
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/* vector 38: USB DR SIxxR_H , Bit 6 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 6},
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/* vector 39: USB MPH SIxxR_H , Bit 7 */
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{&mpc83xx.ipic.sipnr [0], &mpc83xx.ipic.simsr [0], 7},
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{NULL, NULL, 0}, /* reserved vector 40 */
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{NULL, NULL, 0}, /* reserved vector 41 */
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{NULL, NULL, 0}, /* reserved vector 42 */
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{NULL, NULL, 0}, /* reserved vector 43 */
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{NULL, NULL, 0}, /* reserved vector 44 */
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{NULL, NULL, 0}, /* reserved vector 45 */
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{NULL, NULL, 0}, /* reserved vector 46 */
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{NULL, NULL, 0}, /* reserved vector 47 */
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/* vector 48: IRQ0 SExxR , Bit 0 */
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{&mpc83xx.ipic.sepnr, &mpc83xx.ipic.semsr, 0},
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{NULL, NULL, 0}, /* reserved vector 49 */
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{NULL, NULL, 0}, /* reserved vector 50 */
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{NULL, NULL, 0}, /* reserved vector 51 */
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{NULL, NULL, 0}, /* reserved vector 52 */
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{NULL, NULL, 0}, /* reserved vector 53 */
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{NULL, NULL, 0}, /* reserved vector 54 */
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{NULL, NULL, 0}, /* reserved vector 55 */
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{NULL, NULL, 0}, /* reserved vector 56 */
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{NULL, NULL, 0}, /* reserved vector 57 */
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{NULL, NULL, 0}, /* reserved vector 58 */
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{NULL, NULL, 0}, /* reserved vector 59 */
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{NULL, NULL, 0}, /* reserved vector 60 */
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{NULL, NULL, 0}, /* reserved vector 61 */
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{NULL, NULL, 0}, /* reserved vector 62 */
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{NULL, NULL, 0}, /* reserved vector 63 */
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/* vector 64: RTC SEC SIxxR_L , Bit 0 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 0},
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/* vector 65: PIT SIxxR_L , Bit 1 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 1},
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/* vector 66: PCI1 SIxxR_L , Bit 2 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 2},
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/* vector 67: PCI2 SIxxR_L , Bit 3 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 3},
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/* vector 68: RTC ALR SIxxR_L , Bit 4 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 4},
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/* vector 69: MU SIxxR_L , Bit 5 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 5},
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/* vector 70: SBA SIxxR_L , Bit 6 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 6},
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/* vector 71: DMA SIxxR_L , Bit 7 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 7},
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/* vector 72: GTM4 SIxxR_L , Bit 8 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 8},
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/* vector 73: GTM8 SIxxR_L , Bit 9 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 9},
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/* vector 74: GPIO1 SIxxR_L , Bit 10 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 10},
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/* vector 75: GPIO2 SIxxR_L , Bit 11 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 11},
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/* vector 76: DDR SIxxR_L , Bit 12 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 12},
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/* vector 77: LBC SIxxR_L , Bit 13 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 13},
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/* vector 78: GTM2 SIxxR_L , Bit 14 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 14},
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/* vector 79: GTM6 SIxxR_L , Bit 15 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 15},
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/* vector 80: PMC SIxxR_L , Bit 16 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 16},
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{NULL, NULL, 0}, /* reserved vector 81 */
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{NULL, NULL, 0}, /* reserved vector 82 */
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{NULL, NULL, 0}, /* reserved vector 63 */
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/* vector 84: GTM3 SIxxR_L , Bit 20 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 20},
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/* vector 85: GTM7 SIxxR_L , Bit 21 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 21},
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{NULL, NULL, 0}, /* reserved vector 81 */
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{NULL, NULL, 0}, /* reserved vector 82 */
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{NULL, NULL, 0}, /* reserved vector 63 */
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{NULL, NULL, 0}, /* reserved vector 63 */
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/* vector 90: GTM1 SIxxR_L , Bit 26 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 26},
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/* vector 91: GTM5 SIxxR_L , Bit 27 */
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{&mpc83xx.ipic.sipnr [1], &mpc83xx.ipic.simsr [1], 27}
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};
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static const uint8_t mpc83xx_ipic_mask_position_table [MPC83XX_IPIC_VECTOR_NUMBER] = {
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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7,
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6,
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5,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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2,
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1,
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0,
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94,
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93,
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92,
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91,
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90,
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89,
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88,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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31,
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30,
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29,
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28,
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27,
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26,
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25,
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24,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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95,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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63,
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62,
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61,
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60,
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59,
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58,
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57,
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56,
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55,
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54,
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53,
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52,
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51,
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50,
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49,
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48,
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47,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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43,
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42,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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MPC83XX_IPIC_INVALID_MASK_POSITION,
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37,
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36
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};
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/*
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* this array will be filled with mask values needed
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* to temporarily disable all IRQ soures with lower or same
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* priority of the current source (whose vector is the array index)
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*/
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static mpc83xx_ipic_mask_t mpc83xx_ipic_prio2mask [MPC83XX_IPIC_VECTOR_NUMBER];
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rtems_status_code mpc83xx_ipic_set_mask( rtems_vector_number vector, rtems_vector_number mask_vector, bool mask)
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{
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uint8_t pos = 0;
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mpc83xx_ipic_mask_t *mask_entry;
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uint32_t *mask_reg;
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rtems_interrupt_level level;
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/* Parameter check */
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if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector) || !MPC83XX_IPIC_IS_VALID_VECTOR( mask_vector)) {
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return RTEMS_INVALID_NUMBER;
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} else if (vector == mask_vector) {
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return RTEMS_RESOURCE_IN_USE;
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}
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/* Position and mask entry */
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pos = mpc83xx_ipic_mask_position_table [mask_vector];
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mask_entry = &mpc83xx_ipic_prio2mask [vector];
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/* Mask register and position */
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if (pos < 32) {
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mask_reg = &mask_entry->simsr_mask [0];
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} else if (pos < 64) {
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pos -= 32;
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mask_reg = &mask_entry->simsr_mask [1];
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} else if (pos < 96) {
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pos -= 64;
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mask_reg = &mask_entry->semsr_mask;
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} else if (pos < 128) {
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pos -= 96;
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mask_reg = &mask_entry->sermr_mask;
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} else {
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return RTEMS_NOT_IMPLEMENTED;
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}
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/* Mask or unmask */
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if (mask) {
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rtems_interrupt_disable( level);
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*mask_reg &= ~(1 << pos);
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rtems_interrupt_enable( level);
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} else {
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rtems_interrupt_disable( level);
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*mask_reg |= 1 << pos;
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rtems_interrupt_enable( level);
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code mpc83xx_ipic_set_highest_priority_interrupt( rtems_vector_number vector, int type)
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{
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rtems_interrupt_level level;
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uint32_t reg = 0;
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if (!MPC83XX_IPIC_IS_VALID_VECTOR( vector)) {
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return RTEMS_INVALID_NUMBER;
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} else if (type < 0 || type > MPC83XX_IPIC_INTERRUPT_CRITICAL) {
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return RTEMS_INVALID_NUMBER;
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}
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rtems_interrupt_disable( level);
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reg = mpc83xx.ipic.sicfr;
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mpc83xx.ipic.sicfr = (reg & ~0x7f000300) | (vector << 24) | (type << 8);
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rtems_interrupt_enable( level);
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return RTEMS_SUCCESSFUL;
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}
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/*
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* functions to enable/disable a source at the ipic
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*/
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rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
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{
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rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
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const BSP_isrc_rsc_t *rsc_ptr;
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if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
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rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
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if (rsc_ptr->mask_reg != NULL) {
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uint32_t bit = 1U << (31 - rsc_ptr->bit_num);
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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*(rsc_ptr->mask_reg) |= bit;
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rtems_interrupt_enable(level);
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}
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
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{
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rtems_vector_number vecnum = irqnum - BSP_IPIC_IRQ_LOWEST_OFFSET;
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const BSP_isrc_rsc_t *rsc_ptr;
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if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
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rsc_ptr = &mpc83xx_ipic_isrc_rsc [vecnum];
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if (rsc_ptr->mask_reg != NULL) {
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uint32_t bit = 1U << (31 - rsc_ptr->bit_num);
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
|
|
*(rsc_ptr->mask_reg) &= ~bit;
|
|
rtems_interrupt_enable(level);
|
|
}
|
|
}
|
|
|
|
return RTEMS_SUCCESSFUL;
|
|
}
|
|
|
|
/*
|
|
* IRQ Handler: this is called from the primary exception dispatcher
|
|
*/
|
|
static int BSP_irq_handle_at_ipic( unsigned excNum)
|
|
{
|
|
int32_t vecnum;
|
|
#ifdef GEN83XX_ENABLE_INTERRUPT_NESTING
|
|
mpc83xx_ipic_mask_t mask_save;
|
|
const mpc83xx_ipic_mask_t *mask_ptr;
|
|
uint32_t msr = 0;
|
|
rtems_interrupt_level level;
|
|
#endif
|
|
|
|
/* Get vector number */
|
|
switch (excNum) {
|
|
case ASM_EXT_VECTOR:
|
|
vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr);
|
|
break;
|
|
case ASM_E300_SYSMGMT_VECTOR:
|
|
vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr);
|
|
break;
|
|
case ASM_E300_CRIT_VECTOR:
|
|
vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr);
|
|
break;
|
|
default:
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Check the vector number, mask lower priority interrupts, enable
|
|
* exceptions and dispatch the handler.
|
|
*/
|
|
if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) {
|
|
#ifdef GEN83XX_ENABLE_INTERRUPT_NESTING
|
|
mask_ptr = &mpc83xx_ipic_prio2mask [vecnum];
|
|
|
|
rtems_interrupt_disable( level);
|
|
|
|
/* Save current mask registers */
|
|
mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0];
|
|
mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1];
|
|
mask_save.semsr_mask = mpc83xx.ipic.semsr;
|
|
mask_save.sermr_mask = mpc83xx.ipic.sermr;
|
|
|
|
/* Mask all lower priority interrupts */
|
|
mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0];
|
|
mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1];
|
|
mpc83xx.ipic.semsr &= mask_ptr->semsr_mask;
|
|
mpc83xx.ipic.sermr &= mask_ptr->sermr_mask;
|
|
|
|
rtems_interrupt_enable( level);
|
|
|
|
/* Enable all interrupts */
|
|
if (excNum != ASM_E300_CRIT_VECTOR) {
|
|
msr = ppc_external_exceptions_enable();
|
|
}
|
|
#endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */
|
|
|
|
/* Dispatch interrupt handlers */
|
|
bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET);
|
|
|
|
#ifdef GEN83XX_ENABLE_INTERRUPT_NESTING
|
|
/* Restore machine state */
|
|
if (excNum != ASM_E300_CRIT_VECTOR) {
|
|
ppc_external_exceptions_disable( msr);
|
|
}
|
|
|
|
/* Restore initial masks */
|
|
rtems_interrupt_disable( level);
|
|
mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0];
|
|
mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1];
|
|
mpc83xx.ipic.semsr = mask_save.semsr_mask;
|
|
mpc83xx.ipic.sermr = mask_save.sermr_mask;
|
|
rtems_interrupt_enable( level);
|
|
#endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */
|
|
} else {
|
|
bsp_interrupt_handler_default( vecnum);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Fill the array mpc83xx_ipic_prio2mask to allow masking of lower prio sources
|
|
* to implement nested interrupts.
|
|
*/
|
|
rtems_status_code mpc83xx_ipic_calc_prio2mask( void)
|
|
{
|
|
rtems_status_code rc = RTEMS_SUCCESSFUL;
|
|
|
|
/*
|
|
* FIXME: fill the array
|
|
*/
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* Activate the interrupt controller
|
|
*/
|
|
rtems_status_code mpc83xx_ipic_initialize( void)
|
|
{
|
|
/*
|
|
* mask off all interrupts
|
|
*/
|
|
mpc83xx.ipic.simsr [0] = 0;
|
|
mpc83xx.ipic.simsr [1] = 0;
|
|
mpc83xx.ipic.semsr = 0;
|
|
mpc83xx.ipic.sermr = 0;
|
|
/*
|
|
* set desired configuration as defined in bspopts.h
|
|
* normally, the default values should be fine
|
|
*/
|
|
#if defined( BSP_SICFR_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.sicfr = BSP_SICFR_VAL;
|
|
#endif
|
|
|
|
/*
|
|
* set desired priorities as defined in bspopts.h
|
|
* normally, the default values should be fine
|
|
*/
|
|
#if defined( BSP_SIPRR0_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.siprr [0] = BSP_SIPRR0_VAL;
|
|
#endif
|
|
|
|
#if defined( BSP_SIPRR1_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.siprr [1] = BSP_SIPRR1_VAL;
|
|
#endif
|
|
|
|
#if defined( BSP_SIPRR2_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.siprr [2] = BSP_SIPRR2_VAL;
|
|
#endif
|
|
|
|
#if defined( BSP_SIPRR3_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.siprr [3] = BSP_SIPRR3_VAL;
|
|
#endif
|
|
|
|
#if defined( BSP_SMPRR0_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.smprr [0] = BSP_SMPRR0_VAL;
|
|
#endif
|
|
|
|
#if defined( BSP_SMPRR1_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.smprr [1] = BSP_SMPRR1_VAL;
|
|
#endif
|
|
|
|
#if defined( BSP_SECNR_VAL) /* defined in bspopts.h ? */
|
|
mpc83xx.ipic.secnr = BSP_SECNR_VAL;
|
|
#endif
|
|
|
|
/*
|
|
* calculate priority masks
|
|
*/
|
|
return mpc83xx_ipic_calc_prio2mask();
|
|
}
|
|
|
|
int mpc83xx_exception_handler( BSP_Exception_frame *frame, unsigned exception_number)
|
|
{
|
|
return BSP_irq_handle_at_ipic( exception_number);
|
|
}
|
|
|
|
rtems_status_code bsp_interrupt_facility_initialize()
|
|
{
|
|
/* Install exception handler */
|
|
if (ppc_exc_set_handler( ASM_EXT_VECTOR, mpc83xx_exception_handler)) {
|
|
return RTEMS_IO_ERROR;
|
|
}
|
|
if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, mpc83xx_exception_handler)) {
|
|
return RTEMS_IO_ERROR;
|
|
}
|
|
if (ppc_exc_set_handler( ASM_E300_CRIT_VECTOR, mpc83xx_exception_handler)) {
|
|
return RTEMS_IO_ERROR;
|
|
}
|
|
|
|
/* Initialize the interrupt controller */
|
|
return mpc83xx_ipic_initialize();
|
|
}
|