forked from Imagelibrary/rtems
211 lines
11 KiB
C
211 lines
11 KiB
C
/*===============================================================*\
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| Project: RTEMS generic MPC5200 BSP |
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+-----------------------------------------------------------------+
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| Partially based on the code references which are named below. |
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| Adaptions, modifications, enhancements and any recent parts of |
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| the code are: |
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| Copyright (c) 2005, 2010 |
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| embedded brains GmbH |
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| Obere Lagerstr. 30 |
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| 82178 Puchheim |
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| Germany |
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| rtems@embedded-brains.de |
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+-----------------------------------------------------------------+
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| The license and distribution terms for this file may be |
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| found in the file LICENSE in this distribution or at |
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| http://www.rtems.org/license/LICENSE. |
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+-----------------------------------------------------------------+
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| this file contains declarations for the irq controller handler |
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\*===============================================================*/
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/***********************************************************************/
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/* */
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/* Module: irq.h */
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/* Date: 07/17/2003 */
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/* Purpose: RTEMS MPC5x00 CPU interrupt header file */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Description: This include file describe the data structure and */
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/* the functions implemented by rtems to write */
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/* interrupt handlers. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Code */
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/* References: MPC8260ads CPU interrupt header file */
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/* Module: irq.h */
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/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
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/* Version 1.1 */
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/* Date: 10/10/2002 */
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/* */
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/* Author(s) / Copyright(s): */
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/* */
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/* Copyright (C) 1999 valette@crf.canon.fr */
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/* */
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/* This code is heavilly inspired by the public specification of */
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/* STREAM V2 that can be found at: */
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/* */
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/* <http://www.chorus.com/Documentation/index.html> by following */
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/* the STREAM API Specification Document link. */
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/* */
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/* Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk> */
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/* Surrey Satellite Technology Limited */
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/* The interrupt handling on the mpc8260 seems quite different from */
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/* the 860 (I don't know the 860 well). Although some interrupts */
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/* are routed via the CPM irq and some are direct to the SIU they */
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/* all appear logically the same.Therefore I removed the distinction */
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/* between SIU and CPM interrupts. */
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/* */
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/* The license and distribution terms for this file may be */
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/* found in the file LICENSE in this distribution or at */
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/* http://www.rtems.org/license/LICENSE. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Partially based on the code references which are named above. */
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/* Adaptions, modifications, enhancements and any recent parts of */
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/* the code are under the right of */
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/* */
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/* IPR Engineering, Dachauer Straße 38, D-80335 München */
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/* Copyright(C) 2003 */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* IPR Engineering makes no representation or warranties with */
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/* respect to the performance of this computer program, and */
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/* specifically disclaims any responsibility for any damages, */
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/* special or consequential, connected with the use of this program. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Version history: 1.0 */
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/* */
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/***********************************************************************/
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#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
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#define LIBBSP_POWERPC_GEN5200_IRQ_H
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#define PMCE_CE_SHADOW (1U << (31 - 31))
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#define PMCE_CSE_STICKY (1U << (31 - 21))
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#define PMCE_MSE_STICKY (1U << (31 - 10))
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#define PMCE_PSE_STICKY (1U << (31 - 2))
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#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U)
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#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU)
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#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU)
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/*
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* Peripheral IRQ handlers related definitions
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*/
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#define BSP_PER_IRQ_NUMBER 22
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#define BSP_PER_IRQ_LOWEST_OFFSET 0
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#define BSP_PER_IRQ_MAX_OFFSET \
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(BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */
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/*
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* Main IRQ handlers related definitions
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*/
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#define BSP_MAIN_IRQ_NUMBER 17
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#define BSP_MAIN_IRQ_LOWEST_OFFSET BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
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#define BSP_MAIN_IRQ_MAX_OFFSET \
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(BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */
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/*
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* Critical IRQ handlers related definitions
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*/
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#define BSP_CRIT_IRQ_NUMBER 4
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#define BSP_CRIT_IRQ_LOWEST_OFFSET BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
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#define BSP_CRIT_IRQ_MAX_OFFSET \
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(BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */
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/*
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* Summary of SIU interrupts
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*/
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#define BSP_SIU_IRQ_NUMBER BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
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#define BSP_SIU_IRQ_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
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#define BSP_SIU_IRQ_MAX_OFFSET BSP_CRIT_IRQ_MAX_OFFSET /* 42 */
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/*
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* Processor IRQ handlers related definitions
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*/
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#define BSP_PROCESSOR_IRQ_NUMBER 3
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#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44 */
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#define BSP_PROCESSOR_IRQ_MAX_OFFSET \
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(BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */
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/*
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* Summary
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*/
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#define BSP_IRQ_NUMBER BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
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#define BSP_LOWEST_OFFSET BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
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#define BSP_MAX_OFFSET BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
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#ifndef ASM
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#include <rtems.h>
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#include <rtems/irq.h>
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#include <rtems/irq-extension.h>
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/*
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* index table for the module specific handlers, a few entries are only placeholders
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*/
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typedef enum {
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BSP_SIU_IRQ_SMARTCOMM = BSP_PER_IRQ_LOWEST_OFFSET + 0,
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BSP_SIU_IRQ_PSC1 = BSP_PER_IRQ_LOWEST_OFFSET + 1,
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BSP_SIU_IRQ_PSC2 = BSP_PER_IRQ_LOWEST_OFFSET + 2,
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BSP_SIU_IRQ_PSC3 = BSP_PER_IRQ_LOWEST_OFFSET + 3,
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BSP_SIU_IRQ_PSC6 = BSP_PER_IRQ_LOWEST_OFFSET + 4,
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BSP_SIU_IRQ_ETH = BSP_PER_IRQ_LOWEST_OFFSET + 5,
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BSP_SIU_IRQ_USB = BSP_PER_IRQ_LOWEST_OFFSET + 6,
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BSP_SIU_IRQ_ATA = BSP_PER_IRQ_LOWEST_OFFSET + 7,
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BSP_SIU_IRQ_PCI_CRT = BSP_PER_IRQ_LOWEST_OFFSET + 8,
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BSP_SIU_IRQ_PCI_SC_RX = BSP_PER_IRQ_LOWEST_OFFSET + 9,
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BSP_SIU_IRQ_PCI_SC_TX = BSP_PER_IRQ_LOWEST_OFFSET + 10,
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BSP_SIU_IRQ_PSC4 = BSP_PER_IRQ_LOWEST_OFFSET + 11,
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BSP_SIU_IRQ_PSC5 = BSP_PER_IRQ_LOWEST_OFFSET + 12,
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BSP_SIU_IRQ_SPI_MODF = BSP_PER_IRQ_LOWEST_OFFSET + 13,
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BSP_SIU_IRQ_SPI_SPIF = BSP_PER_IRQ_LOWEST_OFFSET + 14,
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BSP_SIU_IRQ_I2C1 = BSP_PER_IRQ_LOWEST_OFFSET + 15,
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BSP_SIU_IRQ_I2C2 = BSP_PER_IRQ_LOWEST_OFFSET + 16,
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BSP_SIU_IRQ_MSCAN1 = BSP_PER_IRQ_LOWEST_OFFSET + 17,
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BSP_SIU_IRQ_MSCAN2 = BSP_PER_IRQ_LOWEST_OFFSET + 18,
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BSP_SIU_IRQ_IR_RX = BSP_PER_IRQ_LOWEST_OFFSET + 19,
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BSP_SIU_IRQ_IR_TX = BSP_PER_IRQ_LOWEST_OFFSET + 20,
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BSP_SIU_IRQ_XLB_ARB = BSP_PER_IRQ_LOWEST_OFFSET + 21,
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/* SL_TIMER1 -- handler entry only used in case of SMI */
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BSP_SIU_IRQ_SL_TIMER1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 0,
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BSP_SIU_IRQ_IRQ1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
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BSP_SIU_IRQ_IRQ2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
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BSP_SIU_IRQ_IRQ3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
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/* LO_INT -- handler entry never used (only placeholder) */
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BSP_SIU_IRQ_LO_INT = BSP_MAIN_IRQ_LOWEST_OFFSET + 4,
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BSP_SIU_IRQ_RTC_PER = BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
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BSP_SIU_IRQ_RTC_STW = BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
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BSP_SIU_IRQ_GPIO_STD = BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
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BSP_SIU_IRQ_GPIO_WKUP = BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
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BSP_SIU_IRQ_TMR0 = BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
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BSP_SIU_IRQ_TMR1 = BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
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BSP_SIU_IRQ_TMR2 = BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
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BSP_SIU_IRQ_TMR3 = BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
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BSP_SIU_IRQ_TMR4 = BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
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BSP_SIU_IRQ_TMR5 = BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
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BSP_SIU_IRQ_TMR6 = BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
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BSP_SIU_IRQ_TMR7 = BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
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BSP_SIU_IRQ_IRQ0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
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BSP_SIU_IRQ_SL_TIMER0 = BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
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/* HI_INT -- handler entry never used (only placeholder) */
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BSP_SIU_IRQ_HI_INT = BSP_CRIT_IRQ_LOWEST_OFFSET + 2,
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BSP_SIU_IRQ_CSS_WKUP = BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
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BSP_DECREMENTER = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
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BSP_SYSMGMT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
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BSP_EXT = BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
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} rtems_irq_symbolic_name;
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#define BSP_CRIT_IRQ_PRIO_LEVELS 4
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#define BSP_PERIODIC_TIMER BSP_SIU_IRQ_TMR6
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#define BSP_INTERRUPT_VECTOR_COUNT (BSP_MAX_OFFSET + 1)
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#endif
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#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */
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