forked from Imagelibrary/rtems
e463f8c968
This batch of relicensing was enabled by the combination of Eric Valette and Andy Dachs giving permission. Updates #3053
452 lines
14 KiB
C
452 lines
14 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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*
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* This file contains the implementation of the function described in irq.h
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*/
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/*
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* Copyright (C) 2000, 2002 Andy Dachs <a.dachs@sstl.co.uk>
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* Copyright (C) 1998, 1999 Eric Valette <eric.valette@free.fr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <rtems.h>
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#include <rtems/bspIo.h>
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#include <bsp/vectors.h>
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#include <mpc8260.h>
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/*
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* Check if symbolic IRQ name is an CPM IRQ
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*/
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static inline int is_cpm_irq(const rtems_irq_number irqLine)
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{
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return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) &
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((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET)
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);
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}
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typedef struct {
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uint32_t mask_h; /* mask for sipnr_h and simr_h */
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uint32_t mask_l; /* mask for sipnr_l and simr_l */
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uint32_t priority_h; /* mask this and lower priority ints */
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uint32_t priority_l;
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} m82xxIrqMasks_t;
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static unsigned char irqPrioTable[BSP_CPM_IRQ_NUMBER]={
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/*
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* actual priorities for interrupt :
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*/
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/*
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* CPM Interrupts
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*/
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0, 45, 63, 44, 66, 68, 35, 39, 50, 62, 34, 0, 30, 40, 52, 58,
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2, 3, 0, 5, 15, 16, 17, 18, 49, 51, 0, 0, 0, 0, 0, 0,
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6, 7, 8, 0, 11, 12, 0, 0, 20, 21, 22, 23, 0, 0, 0, 0,
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29, 31, 33, 37, 38, 41, 47, 48, 55, 56, 57, 60, 64, 65, 69, 70,
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};
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/*
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* Mask fields should have a '1' in the bit position for that
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* interrupt.
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* Priority masks calculated later based on priority table
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*/
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static m82xxIrqMasks_t SIU_MaskBit[BSP_CPM_IRQ_NUMBER] =
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{
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* err */
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{ 0x00000000, 0x00008000, 0x00000000, 0x00000000 }, /* i2c */
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{ 0x00000000, 0x00004000, 0x00000000, 0x00000000 }, /* spi */
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{ 0x00000000, 0x00002000, 0x00000000, 0x00000000 }, /* rtt */
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{ 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, /* smc1 */
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{ 0x00000000, 0x00000800, 0x00000000, 0x00000000 }, /* smc2 */
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{ 0x00000000, 0x00000400, 0x00000000, 0x00000000 }, /* idma1 */
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{ 0x00000000, 0x00000200, 0x00000000, 0x00000000 }, /* idma2 */
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{ 0x00000000, 0x00000100, 0x00000000, 0x00000000 }, /* idma3 */
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{ 0x00000000, 0x00000080, 0x00000000, 0x00000000 }, /* idma4 */
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{ 0x00000000, 0x00000040, 0x00000000, 0x00000000 }, /* sdma */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, /* tmr1 */
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{ 0x00000000, 0x00000008, 0x00000000, 0x00000000 }, /* tmr2 */
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{ 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, /* tmr3 */
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{ 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, /* tmr4 */
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{ 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* tmcnt */
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{ 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* pit */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00004000, 0x00000000, 0x00000000, 0x00000000 }, /* irq1 */
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{ 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* irq2 */
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{ 0x00001000, 0x00000000, 0x00000000, 0x00000000 }, /* irq3 */
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{ 0x00000800, 0x00000000, 0x00000000, 0x00000000 }, /* irq4 */
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{ 0x00000400, 0x00000000, 0x00000000, 0x00000000 }, /* irq5 */
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{ 0x00000200, 0x00000000, 0x00000000, 0x00000000 }, /* irq6 */
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{ 0x00000100, 0x00000000, 0x00000000, 0x00000000 }, /* irq7 */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x80000000, 0x00000000, 0x00000000 }, /* fcc1 */
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{ 0x00000000, 0x40000000, 0x00000000, 0x00000000 }, /* fcc2 */
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{ 0x00000000, 0x20000000, 0x00000000, 0x00000000 }, /* fcc3 */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x08000000, 0x00000000, 0x00000000 }, /* mcc1 */
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{ 0x00000000, 0x04000000, 0x00000000, 0x00000000 }, /* mcc2 */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00800000, 0x00000000, 0x00000000 }, /* scc1 */
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{ 0x00000000, 0x00400000, 0x00000000, 0x00000000 }, /* scc2 */
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{ 0x00000000, 0x00200000, 0x00000000, 0x00000000 }, /* scc3 */
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{ 0x00000000, 0x00100000, 0x00000000, 0x00000000 }, /* scc4 */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* reserved */
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{ 0x00010000, 0x00000000, 0x00000000, 0x00000000 }, /* pc15 */
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{ 0x00020000, 0x00000000, 0x00000000, 0x00000000 }, /* pc14 */
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{ 0x00040000, 0x00000000, 0x00000000, 0x00000000 }, /* pc13 */
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{ 0x00080000, 0x00000000, 0x00000000, 0x00000000 }, /* pc12 */
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{ 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* pc11 */
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{ 0x00200000, 0x00000000, 0x00000000, 0x00000000 }, /* pc10 */
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{ 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* pc9 */
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{ 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* pc8 */
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{ 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc7 */
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{ 0x02000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc6 */
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{ 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc5 */
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{ 0x08000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc4 */
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{ 0x10000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc3 */
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{ 0x20000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc2 */
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{ 0x40000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc1 */
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{ 0x80000000, 0x00000000, 0x00000000, 0x00000000 }, /* pc0 */
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};
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/*
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* ------------------------ RTEMS Irq helper functions ----------------
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*/
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/*
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* Caution : this function assumes the variable "internal_config"
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* is already set and that the tables it contains are still valid
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* and accessible.
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*/
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static void compute_SIU_IvectMask_from_prio (void)
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{
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/*
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* The actual masks defined
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* correspond to the priorities defined
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* for the SIU in irq_init.c.
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*/
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int i,j;
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for( i=0; i<BSP_CPM_IRQ_NUMBER; i++ )
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{
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for( j=0;j<BSP_CPM_IRQ_NUMBER; j++ )
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if( irqPrioTable[j] < irqPrioTable[i] )
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{
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SIU_MaskBit[i].priority_h |= SIU_MaskBit[j].mask_h;
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SIU_MaskBit[i].priority_l |= SIU_MaskBit[j].mask_l;
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}
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}
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}
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int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine)
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{
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int cpm_irq_index;
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if (!is_cpm_irq(irqLine))
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return 1;
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cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
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m8260.simr_h |= SIU_MaskBit[cpm_irq_index].mask_h;
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m8260.simr_l |= SIU_MaskBit[cpm_irq_index].mask_l;
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return 0;
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}
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int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine)
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{
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int cpm_irq_index;
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if (!is_cpm_irq(irqLine))
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return 1;
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cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
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m8260.simr_h &= ~(SIU_MaskBit[cpm_irq_index].mask_h);
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m8260.simr_l &= ~(SIU_MaskBit[cpm_irq_index].mask_l);
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return 0;
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}
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int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine)
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{
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int cpm_irq_index;
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if (!is_cpm_irq(irqLine))
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return 0;
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cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET);
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return ((m8260.simr_h & SIU_MaskBit[cpm_irq_index].mask_h) ||
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(m8260.simr_l & SIU_MaskBit[cpm_irq_index].mask_l));
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}
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#ifdef DISPATCH_HANDLER_STAT
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volatile unsigned int maxLoop = 0;
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#endif
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/*
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* High level IRQ handler called from shared_raw_irq_code_entry
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*/
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static int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned excNum)
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{
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register unsigned int irq;
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#if 0
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register unsigned oldMask; /* old siu pic masks */
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#endif
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register unsigned msr;
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register unsigned new_msr;
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register unsigned old_simr_h;
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register unsigned old_simr_l;
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#ifdef DISPATCH_HANDLER_STAT
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unsigned loopCounter;
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#endif
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/*
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* Handle decrementer interrupt
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*/
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if (excNum == ASM_DEC_VECTOR) {
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_CPU_MSR_GET(msr);
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new_msr = msr | MSR_EE;
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_CPU_MSR_SET(new_msr);
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bsp_interrupt_handler_dispatch(BSP_DECREMENTER);
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_CPU_MSR_SET(msr);
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return 0;
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}
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/*
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* Handle external interrupt generated by SIU on PPC core
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*/
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#ifdef DISPATCH_HANDLER_STAT
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loopCounter = 0;
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#endif
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while (1) {
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if( ((m8260.sipnr_h & m8260.simr_h) | (m8260.sipnr_l & m8260.simr_l)) == 0 ) {
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#ifdef DISPATCH_HANDLER_STAT
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if (loopCounter > maxLoop) maxLoop = loopCounter;
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#endif
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break;
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}
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irq = (m8260.sivec >> 26) + BSP_CPM_IRQ_LOWEST_OFFSET;
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/* Clear mask and pending register */
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if( irq <= BSP_CPM_IRQ_MAX_OFFSET ) {
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/* save interrupt masks */
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old_simr_h = m8260.simr_h;
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old_simr_l = m8260.simr_l;
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/* mask off current interrupt and lower priority ones */
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m8260.simr_h &= SIU_MaskBit[irq].priority_h;
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m8260.simr_l &= SIU_MaskBit[irq].priority_l;
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/* clear pending bit */
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m8260.sipnr_h |= SIU_MaskBit[irq].mask_h;
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m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
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/*
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* make sure, that the masking operations in
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* ICTL and MSR are executed in order
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*/
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__asm__ volatile("sync":::"memory");
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/* re-enable external exceptions */
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_CPU_MSR_GET(msr);
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new_msr = msr | MSR_EE;
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_CPU_MSR_SET(new_msr);
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/* call handler */
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bsp_interrupt_handler_dispatch(irq);
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/* disable exceptions again */
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_CPU_MSR_SET(msr);
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/*
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* make sure, that the masking operations in
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* ICTL and MSR are executed in order
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*/
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__asm__ volatile("sync":::"memory");
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/* restore interrupt masks */
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m8260.simr_h = old_simr_h;
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m8260.simr_l = old_simr_l;
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}
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#ifdef DISPATCH_HANDLER_STAT
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++ loopCounter;
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#endif
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}
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return 0;
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}
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/*
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* Initialize CPM interrupt management
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*/
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static void
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BSP_CPM_irq_init(void)
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{
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m8260.simr_l = 0;
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m8260.simr_h = 0;
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m8260.sipnr_l = 0xffffffff;
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m8260.sipnr_h = 0xffffffff;
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m8260.sicr = 0;
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/*
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* Initialize the interrupt priorities.
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*/
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m8260.siprr = 0x05309770; /* reset value */
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m8260.scprr_h = 0x05309770; /* reset value */
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m8260.scprr_l = 0x05309770; /* reset value */
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}
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rtems_status_code bsp_interrupt_get_attributes(
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rtems_vector_number vector,
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rtems_interrupt_attributes *attributes
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)
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{
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_is_pending(
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rtems_vector_number vector,
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bool *pending
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(pending != NULL);
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*pending = false;
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_vector_is_enabled(
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rtems_vector_number vector,
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bool *enabled
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(enabled != NULL);
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*enabled = false;
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(irqnum));
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if (is_cpm_irq(irqnum)) {
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/*
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* Enable interrupt at PIC level
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*/
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BSP_irq_enable_at_cpm (irqnum);
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(irqnum));
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if (is_cpm_irq(irqnum)) {
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/*
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* disable interrupt at PIC level
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*/
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BSP_irq_disable_at_cpm (irqnum);
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}
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_set_priority(
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rtems_vector_number vector,
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uint32_t priority
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_get_priority(
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rtems_vector_number vector,
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uint32_t *priority
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(priority != NULL);
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return RTEMS_UNSATISFIED;
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}
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void bsp_interrupt_facility_initialize()
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{
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rtems_status_code sc;
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/* Install exception handler */
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sc = ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler);
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_Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL);
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sc = ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler);
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_Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL);
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/* Fill in priority masks */
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compute_SIU_IvectMask_from_prio();
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/* Initialize the interrupt controller */
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BSP_CPM_irq_init();
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}
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