forked from Imagelibrary/rtems
4cf93658ef
The previous cache manager support used a single souce file (cache_manager.c) which included an implementation header (cache_.h). This required the use of specialized include paths to find the right header file. Change this to include a generic implementation header (cacheimpl.h) in specialized source files. Use the following directories and files: * bsps/shared/cache * bsps/@RTEMS_CPU@/shared/cache * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c Update #3285.
135 lines
4.1 KiB
C
135 lines
4.1 KiB
C
/* Blackfin Cache Support
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*
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* Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
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* written by Allan Hessenflow <allanh@kallisti.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <bsp.h>
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#include <libcpu/memoryRegs.h>
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#define CPU_DATA_CACHE_ALIGNMENT 32
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
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#ifdef BSP_DATA_CACHE_CONFIG
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#define LIBCPU_DATA_CACHE_CONFIG BSP_DATA_CACHE_CONFIG
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#else
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/* use 16K of each SRAM bank */
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#define LIBCPU_DATA_CACHE_CONFIG (3 << DMEM_CONTROL_DMC_SHIFT)
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#endif
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/* There are many syncs in the following code because they should be
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harmless except for wasting time, and this is easier than figuring out
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exactly where they're needed to protect from the effects of write
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buffers and queued reads. Many of them are likely unnecessary. */
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static void _CPU_cache_flush_1_data_line(const void *d_addr) {
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__asm__ __volatile__ ("ssync; flush [%0]; ssync" :: "a" (d_addr));
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}
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/* Blackfins can't just invalidate cache; they can only do flush +
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invalidate. If the line isn't dirty then this is equivalent to
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just an invalidate. Even if it is dirty, this should still be
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okay since with a pure invalidate method the caller would have no
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way to insure the dirty line hadn't been written out anyway prior
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to the invalidate. */
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static void _CPU_cache_invalidate_1_data_line(const void *d_addr) {
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__asm__ __volatile__ ("ssync; flushinv [%0]; ssync" :: "a" (d_addr));
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}
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static void _CPU_cache_freeze_data(void) {
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}
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static void _CPU_cache_unfreeze_data(void) {
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}
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static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) {
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__asm__ __volatile__ ("ssync; iflush [%0]; ssync" :: "a" (d_addr));
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}
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static void _CPU_cache_freeze_instruction(void) {
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}
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static void _CPU_cache_unfreeze_instruction(void) {
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}
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/* incredibly inefficient... It would be better to make use of the
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DTEST_COMMAND/DTEST_DATAx registers to find the addresses in each
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cache line and flush just those. However the documentation I've
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seen on those is a bit sketchy, and I sure wouldn't want to get it
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wrong. */
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static void _CPU_cache_flush_entire_data(void) {
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uint32_t i;
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i = 0;
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__asm__ __volatile__ ("ssync");
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do {
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__asm__ __volatile__ ("flush [%0]" :: "a" (i));
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i += CPU_DATA_CACHE_ALIGNMENT;
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} while (i);
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__asm__ __volatile__ ("ssync");
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}
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static void _CPU_cache_invalidate_entire_data(void) {
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uint32_t dmemControl;
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__asm__ __volatile__ ("ssync");
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dmemControl = *(uint32_t volatile *) DMEM_CONTROL;
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*(uint32_t volatile *) DMEM_CONTROL = dmemControl & ~DMEM_CONTROL_DMC_MASK;
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*(uint32_t volatile *) DMEM_CONTROL = dmemControl;
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__asm__ __volatile__ ("ssync");
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}
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/* this does not actually enable data cache unless CPLBs are also enabled.
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LIBCPU_DATA_CACHE_CONFIG contains the DMEM_CONTROL_DMC bits to set. */
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static void _CPU_cache_enable_data(void) {
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__asm__ __volatile__ ("ssync");
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*(uint32_t volatile *) DMEM_CONTROL |= LIBCPU_DATA_CACHE_CONFIG;
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__asm__ __volatile__ ("ssync");
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}
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static void _CPU_cache_disable_data(void) {
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__asm__ __volatile__ ("ssync");
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*(uint32_t volatile *) DMEM_CONTROL &= ~DMEM_CONTROL_DMC_MASK;
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__asm__ __volatile__ ("ssync");
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}
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static void _CPU_cache_invalidate_entire_instruction(void) {
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uint32_t imemControl;
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__asm__ __volatile__ ("ssync");
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imemControl = *(uint32_t volatile *) IMEM_CONTROL;
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*(uint32_t volatile *) IMEM_CONTROL = imemControl & ~IMEM_CONTROL_IMC;
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*(uint32_t volatile *) IMEM_CONTROL = imemControl;
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__asm__ __volatile__ ("ssync");
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}
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/* this only actually enables the instruction cache if the CPLBs are also
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enabled. */
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static void _CPU_cache_enable_instruction(void) {
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__asm__ __volatile__ ("ssync");
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*(uint32_t volatile *) IMEM_CONTROL |= IMEM_CONTROL_IMC;
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__asm__ __volatile__ ("ssync");
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}
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static void _CPU_cache_disable_instruction(void) {
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__asm__ __volatile__ ("ssync");
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*(uint32_t volatile *) IMEM_CONTROL &= ~IMEM_CONTROL_IMC;
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__asm__ __volatile__ ("ssync");
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}
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#include "../../../shared/cache/cacheimpl.h"
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