forked from Imagelibrary/rtems
2afb22b7e1
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
214 lines
4.4 KiB
C
214 lines
4.4 KiB
C
/**
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* @file
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*
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* @ingroup lpc_lcd
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*
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* @brief LCD support API.
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*/
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/*
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* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H
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#define LIBBSP_ARM_SHARED_LPC_LCD_H
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#include <bsp/utility.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup lpc_lcd LCD Support
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*
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* @ingroup lpc
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* @ingroup arm_lpc32xx
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*
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* @brief LCD support.
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*
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* @{
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*/
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typedef struct {
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uint8_t img [1024];
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uint32_t ctrl;
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uint32_t cfg;
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uint32_t pal0;
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uint32_t pal1;
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uint32_t xy;
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uint32_t clip;
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uint32_t intmsk;
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uint32_t intclr;
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uint32_t intraw;
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uint32_t intstat;
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} lpc_cursor;
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typedef struct {
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uint32_t timh;
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uint32_t timv;
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uint32_t pol;
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uint32_t le;
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uint32_t upbase;
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uint32_t lpbase;
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uint32_t ctrl;
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uint32_t intmsk;
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uint32_t intraw;
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uint32_t intstat;
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uint32_t intclr;
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uint32_t upcurr;
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uint32_t lpcurr;
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uint8_t reserved_0 [0x200 - 0x034];
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uint16_t pal [256];
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uint8_t reserved_1 [0x800 - 0x400];
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lpc_cursor crsr;
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} lpc_lcd;
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/**
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* @name LCD Configuration Register
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*
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* @{
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*/
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#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4)
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#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5)
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#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7)
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#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8)
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/** @} */
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/**
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* @name LCD Horizontal Timing Register
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*
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* @{
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*/
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#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7)
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#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
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#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15)
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#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
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#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23)
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#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
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#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31)
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#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
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/** @} */
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/**
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* @name LCD Vertical Timing Register
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*
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* @{
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*/
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#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9)
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#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
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#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15)
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#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
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#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23)
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#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
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#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31)
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#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
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/** @} */
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/**
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* @name LCD Clock and Signal Polarity Register
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*
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* @{
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*/
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#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4)
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#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
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#define LCD_POL_CLKSEL BSP_BIT32(5)
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#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10)
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#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
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#define LCD_POL_IVS BSP_BIT32(11)
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#define LCD_POL_IHS BSP_BIT32(12)
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#define LCD_POL_IPC BSP_BIT32(13)
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#define LCD_POL_IOE BSP_BIT32(14)
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#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25)
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#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
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#define LCD_POL_BCD BSP_BIT32(26)
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#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31)
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#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
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/** @} */
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/**
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* @name LCD Line End Control Register
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*
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* @{
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*/
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#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6)
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#define LCD_LE_LEE BSP_BIT32(16)
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/** @} */
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/**
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* @name LCD Control Register
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*
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* @{
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*/
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#define LCD_CTRL_LCDEN BSP_BIT32(0)
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#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3)
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#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
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#define LCD_CTRL_LCDBW BSP_BIT32(4)
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#define LCD_CTRL_LCDTFT BSP_BIT32(5)
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#define LCD_CTRL_LCDMONO8 BSP_BIT32(6)
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#define LCD_CTRL_LCDDUAL BSP_BIT32(7)
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#define LCD_CTRL_BGR BSP_BIT32(8)
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#define LCD_CTRL_BEBO BSP_BIT32(9)
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#define LCD_CTRL_BEPO BSP_BIT32(10)
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#define LCD_CTRL_LCDPWR BSP_BIT32(11)
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#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13)
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#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
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#define LCD_CTRL_WATERMARK BSP_BIT32(16)
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/** @} */
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/**
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* @name LCD Interrupt Registers
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*
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* @{
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*/
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#define LCD_INT_FUF BSP_BIT32(1)
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#define LCD_INT_LNBU BSP_BIT32(2)
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#define LCD_INT_VCOMP BSP_BIT32(3)
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#define LCD_INT_BER BSP_BIT32(4)
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/** @} */
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/**
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* @name LCD Color Palette Register
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*
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* @{
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*/
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#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
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#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
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#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
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#define LCD_PAL_I BSP_BIT16(15)
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/** @} */
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */
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